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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
bf9e3b38 | 2 | /* |
bf9e3b38 WD |
3 | * (C) Copyright 2000-2004 |
4 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
5 | * | |
32dbaafa | 6 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
a1436a84 | 7 | * TsiChung Liew ([email protected]) |
bf9e3b38 WD |
8 | */ |
9 | ||
10 | #include <common.h> | |
c30b7adb | 11 | #include <irq_func.h> |
bf9e3b38 WD |
12 | #include <watchdog.h> |
13 | #include <asm/processor.h> | |
83ec20bc | 14 | #include <asm/immap.h> |
32dbaafa | 15 | #include <asm/io.h> |
eacbd317 | 16 | |
bf9e3b38 | 17 | #ifdef CONFIG_M5272 |
83ec20bc | 18 | int interrupt_init(void) |
bf9e3b38 | 19 | { |
32dbaafa | 20 | intctrl_t *intp = (intctrl_t *) (MMAP_INTC); |
bf9e3b38 | 21 | |
83ec20bc | 22 | /* disable all external interrupts */ |
32dbaafa AW |
23 | out_be32(&intp->int_icr1, 0x88888888); |
24 | out_be32(&intp->int_icr2, 0x88888888); | |
25 | out_be32(&intp->int_icr3, 0x88888888); | |
26 | out_be32(&intp->int_icr4, 0x88888888); | |
27 | out_be32(&intp->int_pitr, 0x00000000); | |
28 | ||
83ec20bc | 29 | /* initialize vector register */ |
32dbaafa | 30 | out_8(&intp->int_pivr, 0x40); |
bf9e3b38 | 31 | |
83ec20bc | 32 | enable_interrupts(); |
bf9e3b38 | 33 | |
83ec20bc | 34 | return 0; |
bf9e3b38 WD |
35 | } |
36 | ||
83ec20bc TL |
37 | #if defined(CONFIG_MCFTMR) |
38 | void dtimer_intr_setup(void) | |
bf9e3b38 | 39 | { |
32dbaafa | 40 | intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); |
bf9e3b38 | 41 | |
32dbaafa AW |
42 | clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); |
43 | setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI); | |
bf9e3b38 | 44 | } |
83ec20bc TL |
45 | #endif /* CONFIG_MCFTMR */ |
46 | #endif /* CONFIG_M5272 */ | |
bf9e3b38 | 47 | |
bf9a5215 TL |
48 | #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \ |
49 | defined(CONFIG_M5271) || defined(CONFIG_M5275) | |
83ec20bc | 50 | int interrupt_init(void) |
bf9e3b38 | 51 | { |
32dbaafa | 52 | int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); |
bf9e3b38 | 53 | |
83ec20bc | 54 | /* Make sure all interrupts are disabled */ |
bf9a5215 | 55 | #if defined(CONFIG_M5208) |
32dbaafa AW |
56 | out_be32(&intp->imrl0, 0xffffffff); |
57 | out_be32(&intp->imrh0, 0xffffffff); | |
bf9a5215 | 58 | #else |
32dbaafa | 59 | setbits_be32(&intp->imrl0, 0x1); |
bf9a5215 | 60 | #endif |
bf9e3b38 | 61 | |
83ec20bc TL |
62 | enable_interrupts(); |
63 | return 0; | |
bf9e3b38 WD |
64 | } |
65 | ||
83ec20bc TL |
66 | #if defined(CONFIG_MCFTMR) |
67 | void dtimer_intr_setup(void) | |
bf9e3b38 | 68 | { |
32dbaafa | 69 | int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); |
bf9e3b38 | 70 | |
32dbaafa AW |
71 | out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); |
72 | clrbits_be32(&intp->imrl0, 0x00000001); | |
73 | clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); | |
bf9e3b38 | 74 | } |
83ec20bc | 75 | #endif /* CONFIG_MCFTMR */ |
f71d9d91 | 76 | #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ |
bf9e3b38 | 77 | |
a1436a84 | 78 | #if defined(CONFIG_M5249) || defined(CONFIG_M5253) |
83ec20bc | 79 | int interrupt_init(void) |
bf9e3b38 | 80 | { |
83ec20bc | 81 | enable_interrupts(); |
bf9e3b38 WD |
82 | |
83 | return 0; | |
84 | } | |
bf9e3b38 | 85 | |
83ec20bc TL |
86 | #if defined(CONFIG_MCFTMR) |
87 | void dtimer_intr_setup(void) | |
8c725b93 | 88 | { |
83ec20bc | 89 | mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); |
6d0f6bcf | 90 | mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); |
8c725b93 | 91 | } |
83ec20bc | 92 | #endif /* CONFIG_MCFTMR */ |
a1436a84 | 93 | #endif /* CONFIG_M5249 || CONFIG_M5253 */ |