[J-u-boot.git] / include / configs / ipam390.h

/*
 * (C) Heiko Schocher, DENX Software Engineering, [email protected].
 * Based on:
 * U-Boot:include/configs/da850evm.h
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on davinci_dvevm.h. Original Copyrights follow:
 *
 * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_BARIX_IPAM390

/*
 * SoC Configuration
 */
#define CONFIG_MACH_DAVINCI_DA850_EVM
#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
#define CONFIG_SOC_DA850		/* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ		24000000
#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SYS_TEXT_BASE		0xc1080000

/*
 * Memory Info
 */
#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/

/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)

/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END	(CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)

#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */

#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART0 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC)

/*
 * PLL configuration
 */
#define CONFIG_SYS_DV_CLKMODE          0
#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005

#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002

#define CONFIG_SYS_DA850_PLL0_PLLM     24
#define CONFIG_SYS_DA850_PLL1_PLLM     24

/*
 * DDR2 memory configuration
 */
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDRCR	0x00000498

#define CONFIG_SYS_DA850_DDR2_SDBCR2	0x00000004
#define CONFIG_SYS_DA850_DDR2_PBBPR	0x00000020

#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
	(13 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
	(2 << DV_DDR_SDTMR1_WR_SHIFT) |		\
	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
	(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
	(2 << DV_DDR_SDTMR2_XP_SHIFT) |		\
	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
	(14 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
	(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
	(1 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
	(2 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
	(2 << DV_DDR_SDCR_CL_SHIFT) |	\
	(3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

#define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(1)	| \
				DAVINCI_ABCR_WSTROBE(2)	| \
				DAVINCI_ABCR_WHOLD(0)	| \
				DAVINCI_ABCR_RSETUP(1)	| \
				DAVINCI_ABCR_RSTROBE(2)	| \
				DAVINCI_ABCR_RHOLD(1)	| \
				DAVINCI_ABCR_TA(0)	| \
				DAVINCI_ABCR_ASIZE_8BIT)

/*
 * Serial Driver info
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
#define CONFIG_BAUDRATE		115200		/* Default baud rate */

/*
 * Flash & Environment
 */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE			(128 << 10)
#define	CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define	CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS		3
#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE		0x10
#define CONFIG_SYS_NAND_MASK_ALE		0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x120000
#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
					CONFIG_SYS_NAND_U_BOOT_SIZE - \
					CONFIG_SYS_MALLOC_LEN -       \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS		{				\
			6,   7,  8,  9, 10,	11, 12, 13, 14, 15,	\
			22, 23, 24, 25, 26,	27, 28, 29, 30, 31,	\
			38, 39, 40, 41, 42,	43, 44, 45, 46, 47,	\
			54, 55, 56, 57, 58,	59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	10
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_LOAD

/*
 * Network & Ethernet Configuration
 */
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#endif

/*
 * U-Boot general configuration
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG		/* enable hwconfig */
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_EXTRA_ENV_SETTINGS \
	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
		"root=/dev/mtdblock5 rw noinitrd " \
		"rootfstype=jffs2 noinitrd\0" \
	"hwconfig=dsp:wake=yes\0" \
	"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
	"bootfile=uImage\0" \
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
	"mtddevname=uboot-env\0" \
	"mtddevnum=0\0" \
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"u-boot=/tftpboot/ipam390/u-boot.ais\0"			\
	"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
		"nand write c0000000 20000 ${filesize}\0"	\
	"setbootparms=nand read c0100000 200000 400000;"	\
		"run defbootargs addmtd;"			\
		"spl export atags c0100000;"			\
		"nand erase.part bootparms;"			\
		"nand write c0000100 180000 20000\0"		\
	"\0"

/*
 * U-Boot commands
 */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_SAVES

#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

#ifndef CONFIG_DRIVER_TI_EMAC
#endif

#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS

#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO
#define CONFIG_RBTREE
#define CONFIG_CMD_UBIFS

#define MTDIDS_NAME_STR		"davinci_nand.0"
#define MTDIDS_DEFAULT		"nand0=" MTDIDS_NAME_STR
#define MTDPARTS_DEFAULT	"mtdparts=" MTDIDS_NAME_STR ":" \
					"128k(u-boot-env),"	\
					"1408k(u-boot),"	\
					"128k(bootparms),"	\
					"384k(factory-info),"	\
					"4M(kernel),"	\
					"-(rootfs)"

/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
						CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
#define CONFIG_SPL_STACK	0x8001ff00
#define CONFIG_SPL_TEXT_BASE	0x80000000
#define CONFIG_SPL_MAX_SIZE	0x20000
#define CONFIG_SPL_MAX_FOOTPRINT	32768

/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0xc0000000

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
					GENERATED_GBL_DATA_SIZE)

/* add FALCON boot mode */
#define CONFIG_CMD_SPL
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000
#define CONFIG_SYS_SPL_ARGS_ADDR	LINUX_BOOT_PARAM_ADDR
#define CONFIG_CMD_SPL_NAND_OFS		0x00180000
#define CONFIG_CMD_SPL_WRITE_SIZE	0x400

/* GPIO support */
#define CONFIG_DA8XX_GPIO
#define CONFIG_IPAM390_GPIO_BOOTMODE	((16 * 7) + 14)

#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_IPAM390_GPIO_LED_RED	((16 * 7) + 11)
#define CONFIG_IPAM390_GPIO_LED_GREEN	((16 * 7) + 12)

#endif /* __CONFIG_H */
Commit	Line	Data
03efcb05 HS	1	/*
	2	* (C) Heiko Schocher, DENX Software Engineering, [email protected].
	3	* Based on:
	4	* U-Boot:include/configs/da850evm.h
	5	*
	6	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	7	*
	8	* Based on davinci_dvevm.h. Original Copyrights follow:
	9	*
	10	* Copyright (C) 2007 Sergey Kubushyn <[email protected]>
	11	*
	12	* SPDX-License-Identifier: GPL-2.0+
	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
	18	/*
	19	* Board
	20	*/
	21	#define CONFIG_DRIVER_TI_EMAC
	22	#define CONFIG_BARIX_IPAM390
	23
	24	/*
	25	* SoC Configuration
	26	*/
	27	#define CONFIG_MACH_DAVINCI_DA850_EVM
03efcb05 HS	28	#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
	29	#define CONFIG_SOC_DA850 /* TI DA850 SoC */
	30	#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
	31	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
	32	#define CONFIG_SYS_OSCIN_FREQ 24000000
	33	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	34	#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
03efcb05 HS	35	#define CONFIG_SYS_DA850_PLL_INIT
	36	#define CONFIG_SYS_DA850_DDR_INIT
	37	#define CONFIG_SYS_TEXT_BASE 0xc1080000
	38
	39	/*
	40	* Memory Info
	41	*/
	42	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 110241024) /* malloc() len */
	43	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
	44	#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
	45	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
	46
	47	/* memtest start addr */
	48	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
	49
	50	/* memtest will be run on 16MB */
	51	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
	52
	53	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	54
	55	#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
	56	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
	57	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
	58	DAVINCI_SYSCFG_SUSPSRC_UART0 \| \
	59	DAVINCI_SYSCFG_SUSPSRC_EMAC)
	60
	61	/*
	62	* PLL configuration
	63	*/
	64	#define CONFIG_SYS_DV_CLKMODE 0
	65	#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
	66	#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
	67	#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
	68	#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
	69	#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
	70	#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
	71	#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
	72	#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
	73
	74	#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
	75	#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
	76	#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
	77	#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
	78
	79	#define CONFIG_SYS_DA850_PLL0_PLLM 24
	80	#define CONFIG_SYS_DA850_PLL1_PLLM 24
	81
	82	/*
	83	* DDR2 memory configuration
	84	*/
	85	#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
	86	DV_DDR_PHY_EXT_STRBEN \| \
	87	(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	88	#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
	89
	90	#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
	91	#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
	92
03efcb05 HS	93	#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
	94	(13 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	95	(2 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	96	(2 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	97	(2 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	98	(5 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	99	(8 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	100	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	101	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
	102
	103	#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
	104	(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
	105	(2 << DV_DDR_SDTMR2_XP_SHIFT) \| \
	106	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
	107	(14 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
	108	(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
	109	(1 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
	110	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
	111
	112	#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
	113	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) \| \
	114	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \| \
	115	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	116	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	117	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	118	(2 << DV_DDR_SDCR_CL_SHIFT) \| \
	119	(3 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	120	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	121
660a2e65	122	#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) \| \
03efcb05	123	DAVINCI_ABCR_WSTROBE(2) \| \
660a2e65	124	DAVINCI_ABCR_WHOLD(0) \| \
03efcb05	125	DAVINCI_ABCR_RSETUP(1) \| \
660a2e65 HS	126	DAVINCI_ABCR_RSTROBE(2) \| \
	127	DAVINCI_ABCR_RHOLD(1) \| \
	128	DAVINCI_ABCR_TA(0) \| \
03efcb05 HS	129	DAVINCI_ABCR_ASIZE_8BIT)
03efcb05 HS	130
03efcb05 HS	131	/*
	132	* Serial Driver info
	133	*/
03efcb05 HS	134	#define CONFIG_SYS_NS16550_SERIAL
	135	#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
	136	#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
	137	#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
	138	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
	139	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
	140
	141	/*
	142	* Flash & Environment
	143	*/
	144	#define CONFIG_NAND_DAVINCI
	145	#define CONFIG_SYS_NO_FLASH
	146	#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
	147	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
	148	#define CONFIG_ENV_SIZE (128 << 10)
	149	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	150	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	151	#define CONFIG_SYS_NAND_PAGE_2K
	152	#define CONFIG_SYS_NAND_CS 3
	153	#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
	154	#define CONFIG_SYS_NAND_MASK_CLE 0x10
	155	#define CONFIG_SYS_NAND_MASK_ALE 0x8
	156	#undef CONFIG_SYS_NAND_HW_ECC
	157	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	158	#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
660a2e65	159	#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
03efcb05 HS	160	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	161	#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
	162	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
	163	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	164	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
	165	#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
	166	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	167	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
	168	CONFIG_SYS_NAND_U_BOOT_SIZE - \
	169	CONFIG_SYS_MALLOC_LEN - \
	170	GENERATED_GBL_DATA_SIZE)
	171	#define CONFIG_SYS_NAND_ECCPOS { \
660a2e65 HS	172	6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
	173	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
	174	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
	175	54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
03efcb05 HS	176	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	177	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	178	#define CONFIG_SYS_NAND_ECCSIZE 512
	179	#define CONFIG_SYS_NAND_ECCBYTES 10
	180	#define CONFIG_SYS_NAND_OOBSIZE 64
03efcb05 HS	181	#define CONFIG_SPL_NAND_BASE
	182	#define CONFIG_SPL_NAND_DRIVERS
	183	#define CONFIG_SPL_NAND_ECC
	184	#define CONFIG_SPL_NAND_SIMPLE
	185	#define CONFIG_SPL_NAND_LOAD
	186
	187	/*
	188	* Network & Ethernet Configuration
	189	*/
	190	#ifdef CONFIG_DRIVER_TI_EMAC
	191	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	192	#define CONFIG_BOOTP_DEFAULT
	193	#define CONFIG_BOOTP_DNS
	194	#define CONFIG_BOOTP_DNS2
	195	#define CONFIG_BOOTP_SEND_HOSTNAME
	196	#define CONFIG_NET_RETRY_COUNT 10
	197	#endif
	198
	199	/*
	200	* U-Boot general configuration
	201	*/
	202	#define CONFIG_MISC_INIT_R
	203	#define CONFIG_BOARD_EARLY_INIT_F
	204	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
03efcb05 HS	205	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	206	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	207	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	208	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
	209	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
03efcb05	210	#define CONFIG_AUTO_COMPLETE
03efcb05 HS	211	#define CONFIG_CMDLINE_EDITING
	212	#define CONFIG_SYS_LONGHELP
	213	#define CONFIG_CRC32_VERIFY
	214	#define CONFIG_MX_CYCLIC
	215
	216	/*
	217	* Linux Information
	218	*/
	219	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
	220	#define CONFIG_HWCONFIG /* enable hwconfig */
	221	#define CONFIG_CMDLINE_TAG
	222	#define CONFIG_REVISION_TAG
	223	#define CONFIG_SETUP_MEMORY_TAGS
03efcb05	224	#define CONFIG_EXTRA_ENV_SETTINGS \
660a2e65 HS	225	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
	226	"root=/dev/mtdblock5 rw noinitrd " \
	227	"rootfstype=jffs2 noinitrd\0" \
03efcb05	228	"hwconfig=dsp:wake=yes\0" \
660a2e65 HS	229	"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
660a2e65 HS	230	"bootfile=uImage\0" \
03efcb05	231	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
660a2e65 HS	232	"mtddevname=uboot-env\0" \
660a2e65 HS	233	"mtddevnum=0\0" \
03efcb05 HS	234	"mtdids=" MTDIDS_DEFAULT "\0" \
03efcb05 HS	235	"mtdparts=" MTDPARTS_DEFAULT "\0" \
660a2e65 HS	236	"u-boot=/tftpboot/ipam390/u-boot.ais\0" \
	237	"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
	238	"nand write c0000000 20000 ${filesize}\0" \
03efcb05	239	"setbootparms=nand read c0100000 200000 400000;" \
660a2e65	240	"run defbootargs addmtd;" \
03efcb05 HS	241	"spl export atags c0100000;" \
	242	"nand erase.part bootparms;" \
	243	"nand write c0000100 180000 20000\0" \
	244	"\0"
	245
	246	/*
	247	* U-Boot commands
	248	*/
03efcb05	249	#define CONFIG_CMD_ENV
03efcb05	250	#define CONFIG_CMD_DIAG
03efcb05	251	#define CONFIG_CMD_SAVES
03efcb05 HS	252
	253	#ifdef CONFIG_CMD_BDI
	254	#define CONFIG_CLOCKS
	255	#endif
	256
	257	#ifndef CONFIG_DRIVER_TI_EMAC
03efcb05 HS	258	#endif
	259
	260	#define CONFIG_CMD_NAND
	261	#define CONFIG_CMD_NAND_TRIMFFS
	262
	263	#define CONFIG_CMD_MTDPARTS
	264	#define CONFIG_MTD_DEVICE
	265	#define CONFIG_MTD_PARTITIONS
	266	#define CONFIG_LZO
	267	#define CONFIG_RBTREE
03efcb05 HS	268	#define CONFIG_CMD_UBIFS
	269
	270	#define MTDIDS_NAME_STR "davinci_nand.0"
	271	#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
	272	#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
	273	"128k(u-boot-env)," \
	274	"1408k(u-boot)," \
	275	"128k(bootparms)," \
	276	"384k(factory-info)," \
	277	"4M(kernel)," \
	278	"-(rootfs)"
	279
	280	/* defines for SPL */
03efcb05 HS	281	#define CONFIG_SPL_FRAMEWORK
	282	#define CONFIG_SPL_BOARD_INIT
	283	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
	284	CONFIG_SYS_MALLOC_LEN)
	285	#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
03efcb05 HS	286	#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
	287	#define CONFIG_SPL_STACK 0x8001ff00
	288	#define CONFIG_SPL_TEXT_BASE 0x80000000
	289	#define CONFIG_SPL_MAX_SIZE 0x20000
	290	#define CONFIG_SPL_MAX_FOOTPRINT 32768
	291
	292	/* additions for new relocation code, must added to all boards */
	293	#define CONFIG_SYS_SDRAM_BASE 0xc0000000
	294
	295	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
	296	GENERATED_GBL_DATA_SIZE)
	297
	298	/* add FALCON boot mode */
	299	#define CONFIG_CMD_SPL
03efcb05 HS	300	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
	301	#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
	302	#define CONFIG_CMD_SPL_NAND_OFS 0x00180000
	303	#define CONFIG_CMD_SPL_WRITE_SIZE 0x400
	304
	305	/* GPIO support */
03efcb05 HS	306	#define CONFIG_DA8XX_GPIO
	307	#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
	308
	309	#define CONFIG_SHOW_BOOT_PROGRESS
	310	#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
	311	#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
	312
	313	#endif /* __CONFIG_H */