projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c609719b WD |
1 | /* |
| 2 | * (C) Copyright 2002 | |
| 3 | * Rich Ireland, Enterasys Networks, [email protected]. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | * | |
| 23 | */ | |
| 24 | ||
| 25 | #include <fpga.h> | |
| 26 | ||
| 27 | #ifndef _XILINX_H_ | |
| 28 | #define _XILINX_H_ | |
| 29 | ||
| 30 | /* Xilinx Model definitions | |
| 31 | *********************************************************************/ | |
| 6d0f6bcf JCPV |
32 | #define CONFIG_SYS_SPARTAN2 CONFIG_SYS_FPGA_DEV( 0x1 ) |
| 33 | #define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 ) | |
| 34 | #define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 ) | |
| 35 | #define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 ) | |
| 36 | #define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2) | |
| 37 | #define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E) | |
| 38 | #define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2) | |
| 39 | #define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3) | |
| c609719b WD |
40 | /* XXX - Add new models here */ |
| 41 | ||
| 42 | ||
| 43 | /* Xilinx Interface definitions | |
| 44 | *********************************************************************/ | |
| 6d0f6bcf JCPV |
45 | #define CONFIG_SYS_XILINX_IF_SS CONFIG_SYS_FPGA_IF( 0x1 ) /* slave serial */ |
| 46 | #define CONFIG_SYS_XILINX_IF_MS CONFIG_SYS_FPGA_IF( 0x2 ) /* master serial */ | |
| 47 | #define CONFIG_SYS_XILINX_IF_SP CONFIG_SYS_FPGA_IF( 0x4 ) /* slave parallel */ | |
| 48 | #define CONFIG_SYS_XILINX_IF_JTAG CONFIG_SYS_FPGA_IF( 0x8 ) /* jtag */ | |
| 49 | #define CONFIG_SYS_XILINX_IF_MSM CONFIG_SYS_FPGA_IF( 0x10 ) /* master selectmap */ | |
| 50 | #define CONFIG_SYS_XILINX_IF_SSM CONFIG_SYS_FPGA_IF( 0x20 ) /* slave selectmap */ | |
| c609719b WD |
51 | |
| 52 | /* Xilinx types | |
| 53 | *********************************************************************/ | |
| 53677ef1 WD |
54 | typedef enum { /* typedef Xilinx_iface */ |
| 55 | min_xilinx_iface_type, /* low range check value */ | |
| 56 | slave_serial, /* serial data and external clock */ | |
| 57 | master_serial, /* serial data w/ internal clock (not used) */ | |
| 58 | slave_parallel, /* parallel data w/ external latch */ | |
| 59 | jtag_mode, /* jtag/tap serial (not used ) */ | |
| 60 | master_selectmap, /* master SelectMap (virtex2) */ | |
| 61 | slave_selectmap, /* slave SelectMap (virtex2) */ | |
| 62 | max_xilinx_iface_type /* insert all new types before this */ | |
| 63 | } Xilinx_iface; /* end, typedef Xilinx_iface */ | |
| c609719b | 64 | |
| 53677ef1 WD |
65 | typedef enum { /* typedef Xilinx_Family */ |
| 66 | min_xilinx_type, /* low range check value */ | |
| 67 | Xilinx_Spartan2, /* Spartan-II Family */ | |
| 68 | Xilinx_VirtexE, /* Virtex-E Family */ | |
| 69 | Xilinx_Virtex2, /* Virtex2 Family */ | |
| 70 | Xilinx_Spartan3, /* Spartan-III Family */ | |
| 71 | max_xilinx_type /* insert all new types before this */ | |
| 72 | } Xilinx_Family; /* end, typedef Xilinx_Family */ | |
| c609719b | 73 | |
| 53677ef1 WD |
74 | typedef struct { /* typedef Xilinx_desc */ |
| 75 | Xilinx_Family family; /* part type */ | |
| 76 | Xilinx_iface iface; /* interface type */ | |
| 77 | size_t size; /* bytes of data part can accept */ | |
| 78 | void *iface_fns; /* interface function table */ | |
| 79 | int cookie; /* implementation specific cookie */ | |
| 80 | } Xilinx_desc; /* end, typedef Xilinx_desc */ | |
| c609719b WD |
81 | |
| 82 | /* Generic Xilinx Functions | |
| 83 | *********************************************************************/ | |
| e6a857da WD |
84 | extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); |
| 85 | extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); | |
| 86 | extern int xilinx_info(Xilinx_desc *desc); | |
| c609719b WD |
87 | |
| 88 | /* Board specific implementation specific function types | |
| 89 | *********************************************************************/ | |
| 90 | typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie ); | |
| 91 | typedef int (*Xilinx_init_fn)( int cookie ); | |
| 92 | typedef int (*Xilinx_err_fn)( int cookie ); | |
| 93 | typedef int (*Xilinx_done_fn)( int cookie ); | |
| 94 | typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie ); | |
| 95 | typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie ); | |
| 96 | typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie ); | |
| 97 | typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie ); | |
| 98 | typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie ); | |
| 99 | typedef int (*Xilinx_busy_fn)( int cookie ); | |
| 100 | typedef int (*Xilinx_abort_fn)( int cookie ); | |
| 101 | typedef int (*Xilinx_pre_fn)( int cookie ); | |
| 102 | typedef int (*Xilinx_post_fn)( int cookie ); | |
| 89083346 | 103 | typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); |
| c609719b WD |
104 | |
| 105 | #endif /* _XILINX_H_ */ |