[J-u-boot.git] / drivers / spi / rk_spi.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * SPI driver for rockchip
 *
 * (C) Copyright 2015 Google, Inc
 *
 * (C) Copyright 2008-2013 Rockchip Electronics
 * Peter, Software Engineering, <[email protected]>.
 */

#ifndef __RK_SPI_H
#define __RK_SPI_H

struct rockchip_spi {
	u32 ctrlr0;
	u32 ctrlr1;
	u32 enr;
	u32 ser;
	u32 baudr;
	u32 txftlr;
	u32 rxftlr;
	u32 txflr;
	u32 rxflr;
	u32 sr;
	u32 ipr;
	u32 imr;
	u32 isr;
	u32 risr;
	u32 icr;
	u32 dmacr;
	u32 dmatdlr;
	u32 dmardlr;		/* 0x44 */
	u32 reserved[0xef];
	u32 txdr[0x100];	/* 0x400 */
	u32 rxdr[0x100];	/* 0x800 */
};

/* CTRLR0 */
enum {
	DFS_SHIFT	= 0,	/* Data Frame Size */
	DFS_MASK	= 3,
	DFS_4BIT	= 0,
	DFS_8BIT,
	DFS_16BIT,
	DFS_RESV,

	CFS_SHIFT	= 2,	/* Control Frame Size */
	CFS_MASK	= 0xf,

	SCPH_SHIFT	= 6,	/* Serial Clock Phase */
	SCPH_MASK	= 1,
	SCPH_TOGMID	= 0,	/* SCLK toggles in middle of first data bit */
	SCPH_TOGSTA,		/* SCLK toggles at start of first data bit */

	SCOL_SHIFT	= 7,	/* Serial Clock Polarity */
	SCOL_MASK	= 1,
	SCOL_LOW	= 0,	/* Inactive state of serial clock is low */
	SCOL_HIGH,		/* Inactive state of serial clock is high */

	CSM_SHIFT	= 8,	/* Chip Select Mode */
	CSM_MASK	= 0x3,
	CSM_KEEP	= 0,	/* ss_n stays low after each frame  */
	CSM_HALF,		/* ss_n high for half sclk_out cycles */
	CSM_ONE,		/* ss_n high for one sclk_out cycle */
	CSM_RESV,

	SSN_DELAY_SHIFT	= 10,	/* SSN to Sclk_out delay */
	SSN_DELAY_MASK	= 1,
	SSN_DELAY_HALF	= 0,	/* 1/2 sclk_out cycle */
	SSN_DELAY_ONE	= 1,	/* 1 sclk_out cycle */

	SEM_SHIFT	= 11,	/* Serial Endian Mode */
	SEM_MASK	= 1,
	SEM_LITTLE	= 0,	/* little endian */
	SEM_BIG,		/* big endian */

	FBM_SHIFT	= 12,	/* First Bit Mode */
	FBM_MASK	= 1,
	FBM_MSB		= 0,	/* first bit is MSB */
	FBM_LSB,		/* first bit in LSB */

	HALF_WORD_TX_SHIFT = 13,	/* Byte and Halfword Transform */
	HALF_WORD_MASK	= 1,
	HALF_WORD_ON	= 0,	/* apb 16bit write/read, spi 8bit write/read */
	HALF_WORD_OFF,		/* apb 8bit write/read, spi 8bit write/read */

	RXDSD_SHIFT	= 14,	/* Rxd Sample Delay, in cycles */
	RXDSD_MASK	= 3,

	FRF_SHIFT	= 16,	/* Frame Format */
	FRF_MASK	= 3,
	FRF_SPI		= 0,	/* Motorola SPI */
	FRF_SSP,			/* Texas Instruments SSP*/
	FRF_MICROWIRE,		/* National Semiconductors Microwire */
	FRF_RESV,

	TMOD_SHIFT	= 18,	/* Transfer Mode */
	TMOD_MASK	= 3,
	TMOD_TR		= 0,	/* xmit & recv */
	TMOD_TO,		/* xmit only */
	TMOD_RO,		/* recv only */
	TMOD_RESV,

	OMOD_SHIFT	= 20,	/* Operation Mode */
	OMOD_MASK	= 1,
	OMOD_MASTER	= 0,	/* Master Mode */
	OMOD_SLAVE,		/* Slave Mode */
};

/* SR */
enum {
	SR_MASK		= 0x7f,
	SR_BUSY		= 1 << 0,
	SR_TF_FULL	= 1 << 1,
	SR_TF_EMPT	= 1 << 2,
	SR_RF_EMPT	= 1 << 3,
	SR_RF_FULL	= 1 << 4,
};

#define ROCKCHIP_SPI_TIMEOUT_MS		1000

/*
 * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
 * hardware limitation...  the Linux kernel source has the following
 * comment:
 *   "sclk_out: spi master internal logic in rk3x can support 50Mhz"
 */
#define ROCKCHIP_SPI_MAX_RATE		50000000

#endif /* __RK_SPI_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
1b2fd5bf SG	2	/*
	3	* SPI driver for rockchip
	4	*
	5	* (C) Copyright 2015 Google, Inc
	6	*
	7	* (C) Copyright 2008-2013 Rockchip Electronics
	8	* Peter, Software Engineering, <[email protected]>.
1b2fd5bf SG	9	*/
	10
	11	#ifndef __RK_SPI_H
	12	#define __RK_SPI_H
	13
	14	struct rockchip_spi {
	15	u32 ctrlr0;
	16	u32 ctrlr1;
	17	u32 enr;
	18	u32 ser;
	19	u32 baudr;
	20	u32 txftlr;
	21	u32 rxftlr;
	22	u32 txflr;
	23	u32 rxflr;
	24	u32 sr;
	25	u32 ipr;
	26	u32 imr;
	27	u32 isr;
	28	u32 risr;
	29	u32 icr;
	30	u32 dmacr;
	31	u32 dmatdlr;
	32	u32 dmardlr; /* 0x44 */
	33	u32 reserved[0xef];
	34	u32 txdr[0x100]; /* 0x400 */
	35	u32 rxdr[0x100]; /* 0x800 */
	36	};
	37
	38	/* CTRLR0 */
	39	enum {
	40	DFS_SHIFT = 0, /* Data Frame Size */
	41	DFS_MASK = 3,
	42	DFS_4BIT = 0,
	43	DFS_8BIT,
	44	DFS_16BIT,
	45	DFS_RESV,
	46
	47	CFS_SHIFT = 2, /* Control Frame Size */
	48	CFS_MASK = 0xf,
	49
	50	SCPH_SHIFT = 6, /* Serial Clock Phase */
	51	SCPH_MASK = 1,
	52	SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */
	53	SCPH_TOGSTA, /* SCLK toggles at start of first data bit */
	54
	55	SCOL_SHIFT = 7, /* Serial Clock Polarity */
	56	SCOL_MASK = 1,
	57	SCOL_LOW = 0, /* Inactive state of serial clock is low */
	58	SCOL_HIGH, /* Inactive state of serial clock is high */
	59
	60	CSM_SHIFT = 8, /* Chip Select Mode */
	61	CSM_MASK = 0x3,
	62	CSM_KEEP = 0, /* ss_n stays low after each frame */
	63	CSM_HALF, /* ss_n high for half sclk_out cycles */
	64	CSM_ONE, /* ss_n high for one sclk_out cycle */
	65	CSM_RESV,
	66
	67	SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */
	68	SSN_DELAY_MASK = 1,
	69	SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */
	70	SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */
	71
	72	SEM_SHIFT = 11, /* Serial Endian Mode */
73	SEM_MASK = 1,
74	SEM_LITTLE = 0, /* little endian */
75	SEM_BIG, /* big endian */
76
77	FBM_SHIFT = 12, /* First Bit Mode */
78	FBM_MASK = 1,
79	FBM_MSB = 0, /* first bit is MSB */
80	FBM_LSB, /* first bit in LSB */
81
82	HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */
83	HALF_WORD_MASK = 1,
84	HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
85	HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
86
87	RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */
88	RXDSD_MASK = 3,
89
90	FRF_SHIFT = 16, /* Frame Format */
91	FRF_MASK = 3,
92	FRF_SPI = 0, /* Motorola SPI */
93	FRF_SSP, /* Texas Instruments SSP*/
94	FRF_MICROWIRE, /* National Semiconductors Microwire */
95	FRF_RESV,
96
97	TMOD_SHIFT = 18, /* Transfer Mode */
98	TMOD_MASK = 3,
99	TMOD_TR = 0, /* xmit & recv */
100	TMOD_TO, /* xmit only */
101	TMOD_RO, /* recv only */
102	TMOD_RESV,
103
104	OMOD_SHIFT = 20, /* Operation Mode */
105	OMOD_MASK = 1,
106	OMOD_MASTER = 0, /* Master Mode */
107	OMOD_SLAVE, /* Slave Mode */
108	};
109
110	/* SR */
111	enum {
112	SR_MASK = 0x7f,
113	SR_BUSY = 1 << 0,
114	SR_TF_FULL = 1 << 1,
115	SR_TF_EMPT = 1 << 2,
116	SR_RF_EMPT = 1 << 3,
117	SR_RF_FULL = 1 << 4,
118	};
119
120	#define ROCKCHIP_SPI_TIMEOUT_MS 1000
bd376714 PT	121
	122	/*
	123	* We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
	124	* hardware limitation... the Linux kernel source has the following
	125	* comment:
	126	* "sclk_out: spi master internal logic in rk3x can support 50Mhz"
	127	*/
	128	#define ROCKCHIP_SPI_MAX_RATE 50000000
1b2fd5bf SG	129
1b2fd5bf SG	130	#endif /* __RK_SPI_H */