[J-u-boot.git] / drivers / spi / mxc_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/spi.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
#endif

__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return -1;
}

#define OUT	MXC_GPIO_DIRECTION_OUT

#define reg_read readl
#define reg_write(a, v) writel(v, a)

#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
#define CONFIG_SYS_SPI_MXC_WAIT		(CONFIG_SYS_HZ/100)	/* 10 ms */
#endif

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
#if defined(MXC_ECSPI)
	u32		cfg_reg;
#endif
	int		gpio;
	int		ss_pol;
	unsigned int	max_hz;
	unsigned int	mode;
	struct gpio_desc ss;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
	if (CONFIG_IS_ENABLED(DM_SPI)) {
		dm_gpio_set_value(&mxcs->ss, 1);
	} else {
		if (mxcs->gpio > 0)
			gpio_set_value(mxcs->gpio, mxcs->ss_pol);
	}
}

static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
	if (CONFIG_IS_ENABLED(DM_SPI)) {
		dm_gpio_set_value(&mxcs->ss, 0);
	} else {
		if (mxcs->gpio > 0)
			gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
	}
}

u32 get_cspi_div(u32 div)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (div <= (4 << i))
			return i;
	}
	return i;
}

#ifdef MXC_CSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	unsigned int ctrl_reg;
	u32 clk_src;
	u32 div;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	clk_src = mxc_get_clock(MXC_CSPI_CLK);

	div = DIV_ROUND_UP(clk_src, max_hz);
	div = get_cspi_div(div);

	debug("clk %d Hz, div %d, real clk %d Hz\n",
		max_hz, div, clk_src / (4 << div));

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
		MXC_CSPICTRL_DATARATE(div) |
		MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
		MXC_CSPICTRL_SSCTL |
#endif
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (mode & SPI_CPOL)
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;
	mxcs->ctrl_reg = ctrl_reg;

	return 0;
}
#endif

#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	s32 reg_ctrl, reg_config;
	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
	u32 pre_div = 0, post_div = 0;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	/*
	 * Reset SPI and set all CSs to master mode, if toggling
	 * between slave and master mode we might see a glitch
	 * on the clock line
	 */
	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	reg_write(&regs->ctrl, reg_ctrl);
	reg_ctrl |=  MXC_CSPICTRL_EN;
	reg_write(&regs->ctrl, reg_ctrl);

	if (clk_src > max_hz) {
		pre_div = (clk_src - 1) / max_hz;
		/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
		post_div = fls(pre_div);
		if (post_div > 4) {
			post_div -= 4;
			if (post_div >= 16) {
				printf("Error: no divider for the freq: %d\n",
					max_hz);
				return -1;
			}
			pre_div >>= post_div;
		} else {
			post_div = 0;
		}
	}

	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
		MXC_CSPICTRL_SELCHAN(cs);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
		MXC_CSPICTRL_PREDIV(pre_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
		MXC_CSPICTRL_POSTDIV(post_div);

	if (mode & SPI_CS_HIGH)
		ss_pol = 1;

	if (mode & SPI_CPOL) {
		sclkpol = 1;
		sclkctl = 1;
	}

	if (mode & SPI_CPHA)
		sclkpha = 1;

	reg_config = reg_read(&regs->cfg);

	/*
	 * Configuration register setup
	 * The MX51 supports different setup for each SS
	 */
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
		(ss_pol << (cs + MXC_CSPICON_SSPOL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
		(sclkpol << (cs + MXC_CSPICON_POL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
		(sclkctl << (cs + MXC_CSPICON_CTL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
		(sclkpha << (cs + MXC_CSPICON_PHA));

	debug("reg_ctrl = 0x%x\n", reg_ctrl);
	reg_write(&regs->ctrl, reg_ctrl);
	debug("reg_config = 0x%x\n", reg_config);
	reg_write(&regs->cfg, reg_config);

	/* save config register and control register */
	mxcs->ctrl_reg = reg_ctrl;
	mxcs->cfg_reg = reg_config;

	/* clear interrupt reg */
	reg_write(&regs->intr, 0);
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	return 0;
}
#endif

int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
	const u8 *dout, u8 *din, unsigned long flags)
{
	int nbytes = DIV_ROUND_UP(bitlen, 8);
	u32 data, cnt, i;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	u32 ts;
	int status;

	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
		__func__, bitlen, (u32)dout, (u32)din);

	mxcs->ctrl_reg = (mxcs->ctrl_reg &
		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef MXC_ECSPI
	reg_write(&regs->cfg, mxcs->cfg_reg);
#endif

	/* Clear interrupt register */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	/*
	 * The SPI controller works only with words,
	 * check if less than a word is sent.
	 * Access to the FIFO is only 32 bit
	 */
	if (bitlen % 32) {
		data = 0;
		cnt = (bitlen % 32) / 8;
		if (dout) {
			for (i = 0; i < cnt; i++) {
				data = (data << 8) | (*dout++ & 0xFF);
			}
		}
		debug("Sending SPI 0x%x\n", data);

		reg_write(&regs->txdata, data);
		nbytes -= cnt;
	}

	data = 0;

	while (nbytes > 0) {
		data = 0;
		if (dout) {
			/* Buffer is not 32-bit aligned */
			if ((unsigned long)dout & 0x03) {
				data = 0;
				for (i = 0; i < 4; i++)
					data = (data << 8) | (*dout++ & 0xFF);
			} else {
				data = *(u32 *)dout;
				data = cpu_to_be32(data);
				dout += 4;
			}
		}
		debug("Sending SPI 0x%x\n", data);
		reg_write(&regs->txdata, data);
		nbytes -= 4;
	}

	/* FIFO is written, now starts the transfer setting the XCH bit */
	reg_write(&regs->ctrl, mxcs->ctrl_reg |
		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

	ts = get_timer(0);
	status = reg_read(&regs->stat);
	/* Wait until the TC (Transfer completed) bit is set */
	while ((status & MXC_CSPICTRL_TC) == 0) {
		if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
			printf("spi_xchg_single: Timeout!\n");
			return -1;
		}
		status = reg_read(&regs->stat);
	}

	/* Transfer completed, clear any pending request */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	nbytes = DIV_ROUND_UP(bitlen, 8);

	cnt = nbytes % 32;

	if (bitlen % 32) {
		data = reg_read(&regs->rxdata);
		cnt = (bitlen % 32) / 8;
		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
		debug("SPI Rx unaligned: 0x%x\n", data);
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	while (nbytes > 0) {
		u32 tmp;
		tmp = reg_read(&regs->rxdata);
		data = cpu_to_be32(tmp);
		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
		cnt = min_t(u32, nbytes, sizeof(data));
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	return 0;

}

static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
				 unsigned int bitlen, const void *dout,
				 void *din, unsigned long flags)
{
	int n_bytes = DIV_ROUND_UP(bitlen, 8);
	int n_bits;
	int ret;
	u32 blk_size;
	u8 *p_outbuf = (u8 *)dout;
	u8 *p_inbuf = (u8 *)din;

	if (!mxcs)
		return -EINVAL;

	if (flags & SPI_XFER_BEGIN)
		mxc_spi_cs_activate(mxcs);

	while (n_bytes > 0) {
		if (n_bytes < MAX_SPI_BYTES)
			blk_size = n_bytes;
		else
			blk_size = MAX_SPI_BYTES;

		n_bits = blk_size * 8;

		ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);

		if (ret)
			return ret;
		if (dout)
			p_outbuf += blk_size;
		if (din)
			p_inbuf += blk_size;
		n_bytes -= blk_size;
	}

	if (flags & SPI_XFER_END) {
		mxc_spi_cs_deactivate(mxcs);
	}

	return 0;
}

static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
{
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	int ret;

	reg_write(&regs->rxdata, 1);
	udelay(1);
	ret = spi_cfg_mxc(mxcs, cs);
	if (ret) {
		printf("mxc_spi: cannot setup SPI controller\n");
		return ret;
	}
	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	reg_write(&regs->intr, 0);

	return 0;
}

#ifndef CONFIG_DM_SPI
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

void spi_init(void)
{
}

/*
 * Some SPI devices require active chip-select over multiple
 * transactions, we achieve this using a GPIO. Still, the SPI
 * controller has to be configured to use one of its own chipselects.
 * To use this feature you have to implement board_spi_cs_gpio() to assign
 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
 * You must use some unused on this SPI controller cs between 0 and 3.
 */
static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
			 unsigned int bus, unsigned int cs)
{
	int ret;

	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	if (mxcs->gpio == -1)
		return 0;

	gpio_request(mxcs->gpio, "spi-cs");
	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	if (ret) {
		printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
		return -EINVAL;
	}

	return 0;
}

static unsigned long spi_bases[] = {
	MXC_SPI_BASE_ADDRESSES
};

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	if (max_hz == 0) {
		printf("Error: desired clock is 0\n");
		return NULL;
	}

	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
	if (!mxcs) {
		puts("mxc_spi: SPI Slave not allocated !\n");
		return NULL;
	}

	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	ret = setup_cs_gpio(mxcs, bus, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	mxcs->base = spi_bases[bus];
	mxcs->max_hz = max_hz;
	mxcs->mode = mode;

	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
#else

static int mxc_spi_probe(struct udevice *bus)
{
	struct mxc_spi_slave *plat = bus->platdata;
	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
	int node = dev_of_offset(bus);
	const void *blob = gd->fdt_blob;
	int ret;

	if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
				 GPIOD_IS_OUT)) {
		dev_err(bus, "No cs-gpios property\n");
		return -EINVAL;
	}

	plat->base = devfdt_get_addr(bus);
	if (plat->base == FDT_ADDR_T_NONE)
		return -ENODEV;

	ret = dm_gpio_set_value(&plat->ss, 0);
	if (ret) {
		dev_err(bus, "Setting cs error\n");
		return ret;
	}

	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
				      20000000);

	return 0;
}

static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);


	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

static int mxc_spi_claim_bus(struct udevice *dev)
{
	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);

	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}

static int mxc_spi_release_bus(struct udevice *dev)
{
	return 0;
}

static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
	/* Nothing to do */
	return 0;
}

static int mxc_spi_set_mode(struct udevice *bus, uint mode)
{
	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);

	mxcs->mode = mode;
	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	return 0;
}

static const struct dm_spi_ops mxc_spi_ops = {
	.claim_bus	= mxc_spi_claim_bus,
	.release_bus	= mxc_spi_release_bus,
	.xfer		= mxc_spi_xfer,
	.set_speed	= mxc_spi_set_speed,
	.set_mode	= mxc_spi_set_mode,
};

static const struct udevice_id mxc_spi_ids[] = {
	{ .compatible = "fsl,imx51-ecspi" },
	{ }
};

U_BOOT_DRIVER(mxc_spi) = {
	.name	= "mxc_spi",
	.id	= UCLASS_SPI,
	.of_match = mxc_spi_ids,
	.ops	= &mxc_spi_ops,
	.platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
	.probe	= mxc_spi_probe,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
38254f45 GL	2	/*
38254f45 GL	3	* Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
38254f45 GL	4	*/
	5
	6	#include <common.h>
994266bd	7	#include <dm.h>
d255bb0e	8	#include <malloc.h>
38254f45	9	#include <spi.h>
1221ce45	10	#include <linux/errno.h>
38254f45	11	#include <asm/io.h>
d8e0ca85	12	#include <asm/gpio.h>
86271115 SB	13	#include <asm/arch/imx-regs.h>
86271115 SB	14	#include <asm/arch/clock.h>
552a848e	15	#include <asm/mach-imx/spi.h>
38254f45	16
994266bd PF	17	DECLARE_GLOBAL_DATA_PTR;
994266bd PF	18
38254f45 GL	19	#ifdef CONFIG_MX27
	20	/* i.MX27 has a completely wrong register layout and register definitions in the
	21	* datasheet, the correct one is in the Freescale's Linux driver */
	22
61a58a16	23	#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
38254f45	24	"See linux mxc_spi driver from Freescale for details."
08c61a58	25	#endif
c9d59c7f	26
155fa9af NK	27	__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
	28	{
	29	return -1;
	30	}
	31
c4ea1424 SB	32	#define OUT MXC_GPIO_DIRECTION_OUT
c4ea1424 SB	33
ac87c17d SB	34	#define reg_read readl
	35	#define reg_write(a, v) writel(v, a)
	36
f659b573 HS	37	#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
	38	#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
	39	#endif
	40
d255bb0e HS	41	struct mxc_spi_slave {
	42	struct spi_slave slave;
	43	unsigned long base;
	44	u32 ctrl_reg;
08c61a58	45	#if defined(MXC_ECSPI)
d205ddcf SB	46	u32 cfg_reg;
d205ddcf SB	47	#endif
fc7a93c8	48	int gpio;
c4ea1424	49	int ss_pol;
027a9a00 MN	50	unsigned int max_hz;
027a9a00 MN	51	unsigned int mode;
994266bd	52	struct gpio_desc ss;
38254f45	53	};
d255bb0e HS	54
	55	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	56	{
	57	return container_of(slave, struct mxc_spi_slave, slave);
	58	}
38254f45	59
994266bd	60	static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
d205ddcf	61	{
994266bd	62	if (CONFIG_IS_ENABLED(DM_SPI)) {
34ad7491	63	dm_gpio_set_value(&mxcs->ss, 1);
994266bd PF	64	} else {
	65	if (mxcs->gpio > 0)
	66	gpio_set_value(mxcs->gpio, mxcs->ss_pol);
	67	}
d205ddcf SB	68	}
d205ddcf SB	69
994266bd	70	static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
d205ddcf	71	{
994266bd	72	if (CONFIG_IS_ENABLED(DM_SPI)) {
34ad7491	73	dm_gpio_set_value(&mxcs->ss, 0);
994266bd PF	74	} else {
	75	if (mxcs->gpio > 0)
	76	gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
	77	}
d205ddcf SB	78	}
d205ddcf SB	79
afaa9f65 AG	80	u32 get_cspi_div(u32 div)
	81	{
	82	int i;
	83
	84	for (i = 0; i < 8; i++) {
	85	if (div <= (4 << i))
	86	return i;
	87	}
	88	return i;
	89	}
	90
08c61a58	91	#ifdef MXC_CSPI
027a9a00	92	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
c9d59c7f SB	93	{
c9d59c7f SB	94	unsigned int ctrl_reg;
afaa9f65 AG	95	u32 clk_src;
afaa9f65 AG	96	u32 div;
027a9a00 MN	97	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	98	unsigned int mode = mxcs->mode;
afaa9f65 AG	99
	100	clk_src = mxc_get_clock(MXC_CSPI_CLK);
	101
cd200403	102	div = DIV_ROUND_UP(clk_src, max_hz);
afaa9f65 AG	103	div = get_cspi_div(div);
	104
	105	debug("clk %d Hz, div %d, real clk %d Hz\n",
	106	max_hz, div, clk_src / (4 << div));
c9d59c7f SB	107
	108	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
	109	MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) \|
afaa9f65	110	MXC_CSPICTRL_DATARATE(div) \|
c9d59c7f SB	111	MXC_CSPICTRL_EN \|
	112	#ifdef CONFIG_MX35
	113	MXC_CSPICTRL_SSCTL \|
	114	#endif
	115	MXC_CSPICTRL_MODE;
	116
	117	if (mode & SPI_CPHA)
	118	ctrl_reg \|= MXC_CSPICTRL_PHA;
	119	if (mode & SPI_CPOL)
	120	ctrl_reg \|= MXC_CSPICTRL_POL;
	121	if (mode & SPI_CS_HIGH)
	122	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	123	mxcs->ctrl_reg = ctrl_reg;
	124
	125	return 0;
	126	}
	127	#endif
	128
08c61a58	129	#ifdef MXC_ECSPI
027a9a00	130	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
d205ddcf SB	131	{
d205ddcf SB	132	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
9a30903b	133	s32 reg_ctrl, reg_config;
5d584cce MN	134	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
5d584cce MN	135	u32 pre_div = 0, post_div = 0;
ac87c17d	136	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
027a9a00 MN	137	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	138	unsigned int mode = mxcs->mode;
d205ddcf	139
0f1411bc FE	140	/*
	141	* Reset SPI and set all CSs to master mode, if toggling
	142	* between slave and master mode we might see a glitch
	143	* on the clock line
	144	*/
	145	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	146	reg_write(&regs->ctrl, reg_ctrl);
	147	reg_ctrl \|= MXC_CSPICTRL_EN;
	148	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	149
d205ddcf	150	if (clk_src > max_hz) {
9a30903b DB	151	pre_div = (clk_src - 1) / max_hz;
	152	/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
	153	post_div = fls(pre_div);
	154	if (post_div > 4) {
	155	post_div -= 4;
	156	if (post_div >= 16) {
d205ddcf SB	157	printf("Error: no divider for the freq: %d\n",
	158	max_hz);
	159	return -1;
	160	}
9a30903b DB	161	pre_div >>= post_div;
	162	} else {
	163	post_div = 0;
d205ddcf SB	164	}
	165	}
	166
	167	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	168	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) \|
	169	MXC_CSPICTRL_SELCHAN(cs);
	170	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) \|
	171	MXC_CSPICTRL_PREDIV(pre_div);
	172	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) \|
	173	MXC_CSPICTRL_POSTDIV(post_div);
	174
d205ddcf SB	175	if (mode & SPI_CS_HIGH)
	176	ss_pol = 1;
	177
5d584cce	178	if (mode & SPI_CPOL) {
d205ddcf	179	sclkpol = 1;
5d584cce MN	180	sclkctl = 1;
5d584cce MN	181	}
d205ddcf SB	182
	183	if (mode & SPI_CPHA)
	184	sclkpha = 1;
	185
ac87c17d	186	reg_config = reg_read(&regs->cfg);
d205ddcf SB	187
	188	/*
	189	* Configuration register setup
c9d59c7f	190	* The MX51 supports different setup for each SS
d205ddcf SB	191	*/
	192	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) \|
	193	(ss_pol << (cs + MXC_CSPICON_SSPOL));
	194	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
	195	(sclkpol << (cs + MXC_CSPICON_POL));
5d584cce MN	196	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) \|
5d584cce MN	197	(sclkctl << (cs + MXC_CSPICON_CTL));
d205ddcf SB	198	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
	199	(sclkpha << (cs + MXC_CSPICON_PHA));
	200
	201	debug("reg_ctrl = 0x%x\n", reg_ctrl);
ac87c17d	202	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	203	debug("reg_config = 0x%x\n", reg_config);
ac87c17d	204	reg_write(&regs->cfg, reg_config);
d205ddcf SB	205
	206	/* save config register and control register */
	207	mxcs->ctrl_reg = reg_ctrl;
	208	mxcs->cfg_reg = reg_config;
	209
	210	/* clear interrupt reg */
ac87c17d SB	211	reg_write(&regs->intr, 0);
ac87c17d SB	212	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf SB	213
	214	return 0;
	215	}
	216	#endif
	217
994266bd	218	int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
2f721d17	219	const u8 dout, u8 din, unsigned long flags)
38254f45	220	{
9675fed4	221	int nbytes = DIV_ROUND_UP(bitlen, 8);
2f721d17	222	u32 data, cnt, i;
ac87c17d	223	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
f659b573 HS	224	u32 ts;
f659b573 HS	225	int status;
38254f45	226
2f721d17 SB	227	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
2f721d17 SB	228	__func__, bitlen, (u32)dout, (u32)din);
d205ddcf SB	229
	230	mxcs->ctrl_reg = (mxcs->ctrl_reg &
	231	~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) \|
f9b6a157	232	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	233
ac87c17d	234	reg_write(&regs->ctrl, mxcs->ctrl_reg \| MXC_CSPICTRL_EN);
08c61a58	235	#ifdef MXC_ECSPI
ac87c17d	236	reg_write(&regs->cfg, mxcs->cfg_reg);
d205ddcf	237	#endif
38254f45	238
d205ddcf	239	/* Clear interrupt register */
ac87c17d	240	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
fc7a93c8	241
2f721d17 SB	242	/*
	243	* The SPI controller works only with words,
	244	* check if less than a word is sent.
	245	* Access to the FIFO is only 32 bit
	246	*/
	247	if (bitlen % 32) {
	248	data = 0;
	249	cnt = (bitlen % 32) / 8;
	250	if (dout) {
	251	for (i = 0; i < cnt; i++) {
	252	data = (data << 8) \| (*dout++ & 0xFF);
	253	}
	254	}
	255	debug("Sending SPI 0x%x\n", data);
	256
ac87c17d	257	reg_write(&regs->txdata, data);
2f721d17 SB	258	nbytes -= cnt;
	259	}
	260
	261	data = 0;
	262
	263	while (nbytes > 0) {
	264	data = 0;
	265	if (dout) {
	266	/* Buffer is not 32-bit aligned */
	267	if ((unsigned long)dout & 0x03) {
	268	data = 0;
dff01094	269	for (i = 0; i < 4; i++)
2f721d17	270	data = (data << 8) \| (*dout++ & 0xFF);
2f721d17 SB	271	} else {
	272	data = (u32 )dout;
	273	data = cpu_to_be32(data);
6d5ce1bd	274	dout += 4;
2f721d17	275	}
2f721d17 SB	276	}
2f721d17 SB	277	debug("Sending SPI 0x%x\n", data);
ac87c17d	278	reg_write(&regs->txdata, data);
2f721d17 SB	279	nbytes -= 4;
2f721d17 SB	280	}
38254f45	281
d205ddcf	282	/* FIFO is written, now starts the transfer setting the XCH bit */
ac87c17d	283	reg_write(&regs->ctrl, mxcs->ctrl_reg \|
d205ddcf	284	MXC_CSPICTRL_EN \| MXC_CSPICTRL_XCH);
38254f45	285
f659b573 HS	286	ts = get_timer(0);
f659b573 HS	287	status = reg_read(&regs->stat);
d205ddcf	288	/* Wait until the TC (Transfer completed) bit is set */
f659b573 HS	289	while ((status & MXC_CSPICTRL_TC) == 0) {
	290	if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
	291	printf("spi_xchg_single: Timeout!\n");
	292	return -1;
	293	}
	294	status = reg_read(&regs->stat);
	295	}
38254f45	296
d205ddcf	297	/* Transfer completed, clear any pending request */
ac87c17d	298	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf	299
9675fed4	300	nbytes = DIV_ROUND_UP(bitlen, 8);
d205ddcf	301
2f721d17	302	cnt = nbytes % 32;
d205ddcf	303
2f721d17	304	if (bitlen % 32) {
ac87c17d	305	data = reg_read(&regs->rxdata);
2f721d17	306	cnt = (bitlen % 32) / 8;
dff01094	307	data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
2f721d17 SB	308	debug("SPI Rx unaligned: 0x%x\n", data);
2f721d17 SB	309	if (din) {
dff01094 AG	310	memcpy(din, &data, cnt);
dff01094 AG	311	din += cnt;
2f721d17 SB	312	}
	313	nbytes -= cnt;
	314	}
	315
	316	while (nbytes > 0) {
	317	u32 tmp;
ac87c17d	318	tmp = reg_read(&regs->rxdata);
2f721d17 SB	319	data = cpu_to_be32(tmp);
2f721d17 SB	320	debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
b4141195	321	cnt = min_t(u32, nbytes, sizeof(data));
2f721d17 SB	322	if (din) {
	323	memcpy(din, &data, cnt);
	324	din += cnt;
	325	}
	326	nbytes -= cnt;
	327	}
	328
	329	return 0;
fc7a93c8	330
38254f45 GL	331	}
38254f45 GL	332
994266bd PF	333	static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
	334	unsigned int bitlen, const void *dout,
	335	void *din, unsigned long flags)
38254f45	336	{
9675fed4	337	int n_bytes = DIV_ROUND_UP(bitlen, 8);
2f721d17 SB	338	int n_bits;
	339	int ret;
	340	u32 blk_size;
	341	u8 p_outbuf = (u8 )dout;
	342	u8 p_inbuf = (u8 )din;
38254f45	343
994266bd PF	344	if (!mxcs)
994266bd PF	345	return -EINVAL;
38254f45	346
2f721d17	347	if (flags & SPI_XFER_BEGIN)
994266bd	348	mxc_spi_cs_activate(mxcs);
2f721d17 SB	349
2f721d17 SB	350	while (n_bytes > 0) {
2f721d17 SB	351	if (n_bytes < MAX_SPI_BYTES)
	352	blk_size = n_bytes;
	353	else
	354	blk_size = MAX_SPI_BYTES;
	355
	356	n_bits = blk_size * 8;
	357
994266bd	358	ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
2f721d17 SB	359
	360	if (ret)
	361	return ret;
	362	if (dout)
	363	p_outbuf += blk_size;
	364	if (din)
	365	p_inbuf += blk_size;
	366	n_bytes -= blk_size;
eff536be ML	367	}
eff536be ML	368
2f721d17	369	if (flags & SPI_XFER_END) {
994266bd	370	mxc_spi_cs_deactivate(mxcs);
f9b6a157	371	}
38254f45 GL	372
	373	return 0;
	374	}
	375
994266bd PF	376	static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
	377	{
	378	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
	379	int ret;
	380
	381	reg_write(&regs->rxdata, 1);
	382	udelay(1);
	383	ret = spi_cfg_mxc(mxcs, cs);
	384	if (ret) {
	385	printf("mxc_spi: cannot setup SPI controller\n");
	386	return ret;
	387	}
	388	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	389	reg_write(&regs->intr, 0);
	390
	391	return 0;
	392	}
	393
	394	#ifndef CONFIG_DM_SPI
	395	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	396	void *din, unsigned long flags)
	397	{
	398	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	399
	400	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	401	}
	402
38254f45 GL	403	void spi_init(void)
	404	{
	405	}
	406
155fa9af NK	407	/*
	408	* Some SPI devices require active chip-select over multiple
	409	* transactions, we achieve this using a GPIO. Still, the SPI
	410	* controller has to be configured to use one of its own chipselects.
	411	* To use this feature you have to implement board_spi_cs_gpio() to assign
	412	* a gpio value for each cs (-1 if cs doesn't need to use gpio).
	413	* You must use some unused on this SPI controller cs between 0 and 3.
	414	*/
	415	static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
	416	unsigned int bus, unsigned int cs)
fc7a93c8 GL	417	{
	418	int ret;
	419
155fa9af NK	420	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	421	if (mxcs->gpio == -1)
	422	return 0;
	423
994266bd	424	gpio_request(mxcs->gpio, "spi-cs");
155fa9af NK	425	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	426	if (ret) {
	427	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	428	return -EINVAL;
fc7a93c8 GL	429	}
fc7a93c8 GL	430
155fa9af	431	return 0;
fc7a93c8 GL	432	}
fc7a93c8 GL	433
994266bd PF	434	static unsigned long spi_bases[] = {
	435	MXC_SPI_BASE_ADDRESSES
	436	};
	437
d255bb0e HS	438	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	439	unsigned int max_hz, unsigned int mode)
38254f45	440	{
d255bb0e	441	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	442	int ret;
	443
	444	if (bus >= ARRAY_SIZE(spi_bases))
	445	return NULL;
	446
027a9a00 MN	447	if (max_hz == 0) {
	448	printf("Error: desired clock is 0\n");
	449	return NULL;
	450	}
	451
d3504fee	452	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
2f721d17 SB	453	if (!mxcs) {
2f721d17 SB	454	puts("mxc_spi: SPI Slave not allocated !\n");
fc7a93c8	455	return NULL;
2f721d17	456	}
38254f45	457
de5bf02c FE	458	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
de5bf02c FE	459
155fa9af	460	ret = setup_cs_gpio(mxcs, bus, cs);
fc7a93c8 GL	461	if (ret < 0) {
fc7a93c8 GL	462	free(mxcs);
d255bb0e	463	return NULL;
fc7a93c8 GL	464	}
fc7a93c8 GL	465
d205ddcf	466	mxcs->base = spi_bases[bus];
027a9a00 MN	467	mxcs->max_hz = max_hz;
027a9a00 MN	468	mxcs->mode = mode;
d205ddcf	469
d255bb0e HS	470	return &mxcs->slave;
	471	}
	472
	473	void spi_free_slave(struct spi_slave *slave)
	474	{
f9b6a157 GL	475	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	476
	477	free(mxcs);
d255bb0e HS	478	}
	479
	480	int spi_claim_bus(struct spi_slave *slave)
	481	{
	482	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	483
994266bd PF	484	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
	485	}
	486
	487	void spi_release_bus(struct spi_slave *slave)
	488	{
	489	/* TODO: Shut the controller down */
	490	}
	491	#else
	492
	493	static int mxc_spi_probe(struct udevice *bus)
	494	{
	495	struct mxc_spi_slave *plat = bus->platdata;
	496	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
	497	int node = dev_of_offset(bus);
	498	const void *blob = gd->fdt_blob;
	499	int ret;
	500
	501	if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
	502	GPIOD_IS_OUT)) {
	503	dev_err(bus, "No cs-gpios property\n");
	504	return -EINVAL;
	505	}
	506
618e8e20	507	plat->base = devfdt_get_addr(bus);
994266bd PF	508	if (plat->base == FDT_ADDR_T_NONE)
	509	return -ENODEV;
	510
34ad7491	511	ret = dm_gpio_set_value(&plat->ss, 0);
027a9a00	512	if (ret) {
994266bd	513	dev_err(bus, "Setting cs error\n");
027a9a00 MN	514	return ret;
027a9a00 MN	515	}
994266bd PF	516
	517	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
	518	20000000);
38254f45 GL	519
	520	return 0;
	521	}
d255bb0e	522
994266bd PF	523	static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
994266bd PF	524	const void dout, void din, unsigned long flags)
d255bb0e	525	{
994266bd PF	526	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
	527
	528
	529	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	530	}
	531
	532	static int mxc_spi_claim_bus(struct udevice *dev)
	533	{
	534	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
	535	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	536
	537	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
d255bb0e	538	}
994266bd PF	539
	540	static int mxc_spi_release_bus(struct udevice *dev)
	541	{
	542	return 0;
	543	}
	544
	545	static int mxc_spi_set_speed(struct udevice *bus, uint speed)
	546	{
	547	/* Nothing to do */
	548	return 0;
	549	}
	550
	551	static int mxc_spi_set_mode(struct udevice *bus, uint mode)
	552	{
	553	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
	554
	555	mxcs->mode = mode;
	556	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
	557
	558	return 0;
	559	}
	560
	561	static const struct dm_spi_ops mxc_spi_ops = {
	562	.claim_bus = mxc_spi_claim_bus,
	563	.release_bus = mxc_spi_release_bus,
	564	.xfer = mxc_spi_xfer,
	565	.set_speed = mxc_spi_set_speed,
	566	.set_mode = mxc_spi_set_mode,
	567	};
	568
	569	static const struct udevice_id mxc_spi_ids[] = {
	570	{ .compatible = "fsl,imx51-ecspi" },
	571	{ }
	572	};
	573
	574	U_BOOT_DRIVER(mxc_spi) = {
	575	.name = "mxc_spi",
	576	.id = UCLASS_SPI,
	577	.of_match = mxc_spi_ids,
	578	.ops = &mxc_spi_ops,
	579	.platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
	580	.probe = mxc_spi_probe,
	581	};
	582	#endif