projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2d257d92 VR |
1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_K3=y | |
| 8f3e2d14 | 3 | CONFIG_TI_SECURE_DEVICE=y |
| 2d257d92 VR |
4 | CONFIG_SYS_MALLOC_F_LEN=0x8000 |
| 5 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | |
| 6 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
| 7 | CONFIG_NR_DRAM_BANKS=2 | |
| 8 | CONFIG_SOC_K3_AM625=y | |
| 9 | CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 | |
| 10 | CONFIG_TARGET_AM625_A53_EVM=y | |
| fcb5117d | 11 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 5c64598b | 12 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 |
| c960c0fd | 13 | CONFIG_SF_DEFAULT_SPEED=25000000 |
| 21d39eb5 | 14 | CONFIG_SPL_DM_SPI=y |
| 2d257d92 VR |
15 | CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk" |
| 16 | CONFIG_SPL_TEXT_BASE=0x80080000 | |
| c960c0fd | 17 | CONFIG_OF_LIBFDT_OVERLAY=y |
| fcb5117d | 18 | CONFIG_DM_RESET=y |
| 2d257d92 VR |
19 | CONFIG_SPL_MMC=y |
| 20 | CONFIG_SPL_SERIAL=y | |
| 21 | CONFIG_SPL_STACK_R_ADDR=0x82000000 | |
| 5c64598b NJ |
22 | CONFIG_SPL_SIZE_LIMIT=0x40000 |
| 23 | CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 | |
| 2d257d92 VR |
24 | CONFIG_SPL_FS_FAT=y |
| 25 | CONFIG_SPL_LIBDISK_SUPPORT=y | |
| 21d39eb5 | 26 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| 04150400 | 27 | CONFIG_SPL_SPI=y |
| 2d257d92 VR |
28 | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
| 29 | CONFIG_SPL_LOAD_FIT=y | |
| 30 | CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 | |
| c358af81 | 31 | CONFIG_DISTRO_DEFAULTS=y |
| 14439cd7 | 32 | CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" |
| 2d257d92 | 33 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 5c64598b | 34 | CONFIG_SPL_BSS_START_ADDR=0x80c80000 |
| 2d257d92 | 35 | CONFIG_SPL_BSS_MAX_SIZE=0x80000 |
| 5c64598b | 36 | CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y |
| 2d257d92 VR |
37 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| 38 | CONFIG_SPL_STACK_R=y | |
| 39 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y | |
| 40 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 | |
| 41 | CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" | |
| 42 | CONFIG_SPL_DM_MAILBOX=y | |
| 04150400 | 43 | CONFIG_SPL_DM_SPI_FLASH=y |
| 2d257d92 | 44 | CONFIG_SPL_POWER_DOMAIN=y |
| 04150400 DG |
45 | # CONFIG_SPL_SPI_FLASH_TINY is not set |
| 46 | CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y | |
| 04150400 DG |
47 | CONFIG_SPL_SPI_LOAD=y |
| 48 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 | |
| 2d257d92 | 49 | CONFIG_SPL_YMODEM_SUPPORT=y |
| c45568cc | 50 | CONFIG_SYS_BOOTM_LEN=0x800000 |
| 2d257d92 VR |
51 | CONFIG_CMD_MMC=y |
| 52 | CONFIG_OF_CONTROL=y | |
| 53 | CONFIG_SPL_OF_CONTROL=y | |
| 54 | CONFIG_MULTI_DTB_FIT=y | |
| 55 | CONFIG_SPL_MULTI_DTB_FIT=y | |
| 56 | CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y | |
| 57 | CONFIG_NET_RANDOM_ETHADDR=y | |
| 2d257d92 VR |
58 | CONFIG_SPL_DM=y |
| 59 | CONFIG_SPL_DM_SEQ_ALIAS=y | |
| 60 | CONFIG_REGMAP=y | |
| 61 | CONFIG_SPL_REGMAP=y | |
| 62 | CONFIG_SPL_OF_TRANSLATE=y | |
| 63 | CONFIG_CLK=y | |
| 64 | CONFIG_SPL_CLK=y | |
| 65 | CONFIG_CLK_TI_SCI=y | |
| 92a15f69 SS |
66 | CONFIG_DMA_CHANNELS=y |
| 67 | CONFIG_TI_K3_NAVSS_UDMA=y | |
| 2d257d92 VR |
68 | CONFIG_TI_SCI_PROTOCOL=y |
| 69 | CONFIG_DM_MAILBOX=y | |
| 70 | CONFIG_K3_SEC_PROXY=y | |
| 71 | CONFIG_MMC_SDHCI=y | |
| 72 | CONFIG_MMC_SDHCI_ADMA=y | |
| 73 | CONFIG_SPL_MMC_SDHCI_ADMA=y | |
| 74 | CONFIG_MMC_SDHCI_AM654=y | |
| 04150400 | 75 | CONFIG_DM_SPI_FLASH=y |
| 04150400 DG |
76 | CONFIG_SPI_FLASH_SFDP_SUPPORT=y |
| 77 | CONFIG_SPI_FLASH_SOFT_RESET=y | |
| 78 | CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y | |
| 79 | CONFIG_SPI_FLASH_SPANSION=y | |
| a8ddc37e | 80 | CONFIG_SPI_FLASH_S28HX_T=y |
| 92a15f69 SS |
81 | CONFIG_PHY_TI_DP83867=y |
| 82 | CONFIG_PHY_FIXED=y | |
| 83 | CONFIG_TI_AM65_CPSW_NUSS=y | |
| 84 | CONFIG_PHY=y | |
| 2d257d92 VR |
85 | CONFIG_PINCTRL=y |
| 86 | CONFIG_SPL_PINCTRL=y | |
| 87 | CONFIG_PINCTRL_SINGLE=y | |
| 88 | CONFIG_POWER_DOMAIN=y | |
| 89 | CONFIG_TI_SCI_POWER_DOMAIN=y | |
| 90 | CONFIG_K3_SYSTEM_CONTROLLER=y | |
| 91 | CONFIG_REMOTEPROC_TI_K3_ARM64=y | |
| 2d257d92 VR |
92 | CONFIG_RESET_TI_SCI=y |
| 93 | CONFIG_DM_SERIAL=y | |
| 94 | CONFIG_SOC_DEVICE=y | |
| 95 | CONFIG_SOC_DEVICE_TI_K3=y | |
| 96 | CONFIG_SOC_TI=y | |
| 04150400 DG |
97 | CONFIG_SPI=y |
| 98 | CONFIG_DM_SPI=y | |
| 99 | CONFIG_CADENCE_QSPI=y | |
| 2d257d92 VR |
100 | CONFIG_SYSRESET=y |
| 101 | CONFIG_SPL_SYSRESET=y | |
| 102 | CONFIG_SYSRESET_TI_SCI=y | |
| 103 | CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 | |
| 1f768238 | 104 | CONFIG_BLOBLIST_ADDR=0x80D00000 |