[J-u-boot.git] / drivers / spi / mpc8xx_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
 *	<[email protected]>,
 *	<[email protected]>
 * Copyright (c) 2001 Gerd Mennchen <[email protected]>
 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <[email protected]>.
 */

/*
 * MPC8xx CPM SPI interface.
 *
 * Parts of this code are probably not portable and/or specific to
 * the board which I used for the tests. Please send fixes/complaints
 * to [email protected]
 *
 */

#include <common.h>
#include <dm.h>
#include <mpc8xx.h>
#include <spi.h>
#include <linux/delay.h>

#include <asm/cpm_8xx.h>
#include <asm/io.h>

#define CPM_SPI_BASE_RX	CPM_SPI_BASE
#define CPM_SPI_BASE_TX	(CPM_SPI_BASE + sizeof(cbd_t))

#define MAX_BUFFER	0x104

static int mpc8xx_spi_probe(struct udevice *dev)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t __iomem *cp = &immr->im_cpm;
	spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
	cbd_t __iomem *tbdf, *rbdf;

	/* Disable relocation */
	out_be16(&spi->spi_rpbase, 0);

/* 1 */
	/* ------------------------------------------------
	 * Initialize Port B SPI pins -> page 34-8 MPC860UM
	 * (we are only in Master Mode !)
	 * ------------------------------------------------ */

	/* --------------------------------------------
	 * GPIO or per. Function
	 * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
	 * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
	 * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
	 * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
	 * -------------------------------------------- */
	clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E);	/* set  bits */

	/* ----------------------------------------------
	 * In/Out or per. Function 0/1
	 * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
	 * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
	 * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
	 * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
	 * ---------------------------------------------- */
	setbits_be32(&cp->cp_pbdir, 0x0000000F);

	/* ----------------------------------------------
	 * open drain or active output
	 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
	 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
	 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
	 * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
	 * ---------------------------------------------- */

	clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);

	/* Initialize the parameter ram.
	 * We need to make sure many things are initialized to zero
	 */
	out_be32(&spi->spi_rstate, 0);
	out_be32(&spi->spi_rdp, 0);
	out_be16(&spi->spi_rbptr, 0);
	out_be16(&spi->spi_rbc, 0);
	out_be32(&spi->spi_rxtmp, 0);
	out_be32(&spi->spi_tstate, 0);
	out_be32(&spi->spi_tdp, 0);
	out_be16(&spi->spi_tbptr, 0);
	out_be16(&spi->spi_tbc, 0);
	out_be32(&spi->spi_txtmp, 0);

/* 3 */
	/* Set up the SPI parameters in the parameter ram */
	out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
	out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);

	/***********IMPORTANT******************/

	/*
	 * Setting transmit and receive buffer descriptor pointers
	 * initially to rbase and tbase. Only the microcode patches
	 * documentation talks about initializing this pointer. This
	 * is missing from the sample I2C driver. If you dont
	 * initialize these pointers, the kernel hangs.
	 */
	out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
	out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);

/* 4 */
	/* Init SPI Tx + Rx Parameters */
	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
		;

	out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
			       CPM_CR_FLG);
	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
		;

/* 5 */
	/* Set SDMA configuration register */
	out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);

/* 6 */
	/* Set to big endian. */
	out_8(&spi->spi_tfcr, SMC_EB);
	out_8(&spi->spi_rfcr, SMC_EB);

/* 7 */
	/* Set maximum receive size. */
	out_be16(&spi->spi_mrblr, MAX_BUFFER);

/* 8 + 9 */
	/* tx and rx buffer descriptors */
	tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
	rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];

	clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
	clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);

/* 10 + 11 */
	out_8(&cp->cp_spim, 0);			/* Mask  all SPI events */
	out_8(&cp->cp_spie, SPI_EMASK);		/* Clear all SPI events	*/

	return 0;
}

static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
			    const void *dout, void *din, unsigned long flags)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t __iomem *cp = &immr->im_cpm;
	cbd_t __iomem *tbdf, *rbdf;
	int tm;
	size_t count = (bitlen + 7) / 8;

	if (count > MAX_BUFFER)
		return -EINVAL;

	tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
	rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];

	/* Set CS for device */
	clrbits_be32(&cp->cp_pbdat, 0x0001);

	/* Setting tx bd status and data length */
	out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
	out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
	out_be16(&tbdf->cbd_datlen, count);

	/* Setting rx bd status and data length */
	out_be32(&rbdf->cbd_bufaddr, (ulong)din);
	out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
	out_be16(&rbdf->cbd_datlen, 0);	 /* rx length has no significance */

	clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
			SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
	out_8(&cp->cp_spim, 0);		/* Mask  all SPI events */
	out_8(&cp->cp_spie, SPI_EMASK);	/* Clear all SPI events	*/

	/* start spi transfer */
	setbits_8(&cp->cp_spcom, SPI_STR);		/* Start transmit */

	/* --------------------------------
	 * Wait for SPI transmit to get out
	 * or time out (1 second = 1000 ms)
	 * -------------------------------- */
	for (tm = 0; tm < 1000; ++tm) {
		if (in_8(&cp->cp_spie) & SPI_TXB)	/* Tx Buffer Empty */
			break;
		if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
			break;
		udelay(1000);
	}
	if (tm >= 1000)
		printf("*** spi_xfer: Time out while xferring to/from SPI!\n");

	/* Clear CS for device */
	setbits_be32(&cp->cp_pbdat, 0x0001);

	return count;
}

static const struct dm_spi_ops mpc8xx_spi_ops = {
	.xfer		= mpc8xx_spi_xfer,
};

static const struct udevice_id mpc8xx_spi_ids[] = {
	{ .compatible = "fsl,mpc8xx-spi" },
	{ }
};

U_BOOT_DRIVER(mpc8xx_spi) = {
	.name	= "mpc8xx_spi",
	.id	= UCLASS_SPI,
	.of_match = mpc8xx_spi_ids,
	.ops	= &mpc8xx_spi_ops,
	.probe	= mpc8xx_spi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
907208c4 CL	2	/*
	3	* Copyright (c) 2001 Navin Boppuri / Prashant Patel
	4	* <[email protected]>,
	5	* <[email protected]>
	6	* Copyright (c) 2001 Gerd Mennchen <[email protected]>
	7	* Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <[email protected]>.
907208c4 CL	8	*/
	9
	10	/*
	11	* MPC8xx CPM SPI interface.
	12	*
	13	* Parts of this code are probably not portable and/or specific to
	14	* the board which I used for the tests. Please send fixes/complaints
	15	* to [email protected]
	16	*
	17	*/
	18
	19	#include <common.h>
fb0204e4	20	#include <dm.h>
907208c4	21	#include <mpc8xx.h>
fb0204e4	22	#include <spi.h>
c05ed00a	23	#include <linux/delay.h>
fb0204e4	24
18f8d4c6	25	#include <asm/cpm_8xx.h>
fb0204e4	26	#include <asm/io.h>
907208c4	27
ba3da734 CL	28	#define CPM_SPI_BASE_RX CPM_SPI_BASE
	29	#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
	30
907208c4 CL	31	#define MAX_BUFFER 0x104
907208c4 CL	32
fb0204e4	33	static int mpc8xx_spi_probe(struct udevice *dev)
907208c4	34	{
ba3da734 CL	35	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
	36	cpm8xx_t __iomem *cp = &immr->im_cpm;
	37	spi_t __iomem spi = (spi_t __iomem )&cp->cp_dparam[PROFF_SPI];
	38	cbd_t __iomem tbdf, rbdf;
907208c4	39
907208c4	40	/* Disable relocation */
ba3da734	41	out_be16(&spi->spi_rpbase, 0);
907208c4 CL	42
	43	/* 1 */
	44	/* ------------------------------------------------
	45	* Initialize Port B SPI pins -> page 34-8 MPC860UM
	46	* (we are only in Master Mode !)
	47	* ------------------------------------------------ */
	48
	49	/* --------------------------------------------
	50	* GPIO or per. Function
	51	* PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
	52	* PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
	53	* PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
	54	* PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
	55	* -------------------------------------------- */
ba3da734	56	clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
907208c4 CL	57
	58	/* ----------------------------------------------
	59	* In/Out or per. Function 0/1
	60	* PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
	61	* PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
	62	* PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
	63	* PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
	64	* ---------------------------------------------- */
ba3da734	65	setbits_be32(&cp->cp_pbdir, 0x0000000F);
907208c4 CL	66
	67	/* ----------------------------------------------
	68	* open drain or active output
	69	* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
	70	* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
	71	* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
70fd0710	72	* PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
907208c4 CL	73	* ---------------------------------------------- */
907208c4 CL	74
ba3da734	75	clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
907208c4 CL	76
	77	/* Initialize the parameter ram.
	78	* We need to make sure many things are initialized to zero
	79	*/
ba3da734 CL	80	out_be32(&spi->spi_rstate, 0);
	81	out_be32(&spi->spi_rdp, 0);
	82	out_be16(&spi->spi_rbptr, 0);
	83	out_be16(&spi->spi_rbc, 0);
	84	out_be32(&spi->spi_rxtmp, 0);
	85	out_be32(&spi->spi_tstate, 0);
	86	out_be32(&spi->spi_tdp, 0);
	87	out_be16(&spi->spi_tbptr, 0);
	88	out_be16(&spi->spi_tbc, 0);
	89	out_be32(&spi->spi_txtmp, 0);
907208c4 CL	90
	91	/* 3 */
	92	/* Set up the SPI parameters in the parameter ram */
ba3da734 CL	93	out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
ba3da734 CL	94	out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
907208c4 CL	95
	96	/*********IMPORTANT****************/
	97
	98	/*
	99	* Setting transmit and receive buffer descriptor pointers
	100	* initially to rbase and tbase. Only the microcode patches
	101	* documentation talks about initializing this pointer. This
	102	* is missing from the sample I2C driver. If you dont
	103	* initialize these pointers, the kernel hangs.
	104	*/
ba3da734 CL	105	out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
ba3da734 CL	106	out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
907208c4 CL	107
	108	/* 4 */
	109	/* Init SPI Tx + Rx Parameters */
ba3da734	110	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
907208c4	111	;
ba3da734 CL	112
	113	out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) \|
	114	CPM_CR_FLG);
	115	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
907208c4 CL	116	;
	117
	118	/* 5 */
	119	/* Set SDMA configuration register */
ba3da734	120	out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
907208c4 CL	121
	122	/* 6 */
	123	/* Set to big endian. */
ba3da734 CL	124	out_8(&spi->spi_tfcr, SMC_EB);
ba3da734 CL	125	out_8(&spi->spi_rfcr, SMC_EB);
907208c4 CL	126
	127	/* 7 */
	128	/* Set maximum receive size. */
ba3da734	129	out_be16(&spi->spi_mrblr, MAX_BUFFER);
907208c4 CL	130
	131	/* 8 + 9 */
	132	/* tx and rx buffer descriptors */
ba3da734 CL	133	tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
ba3da734 CL	134	rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
907208c4	135
ba3da734 CL	136	clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
ba3da734 CL	137	clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
907208c4	138
907208c4	139	/* 10 + 11 */
ba3da734 CL	140	out_8(&cp->cp_spim, 0); /* Mask all SPI events */
ba3da734 CL	141	out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
907208c4	142
fb0204e4	143	return 0;
907208c4 CL	144	}
907208c4 CL	145
fb0204e4 CL	146	static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
fb0204e4 CL	147	const void dout, void din, unsigned long flags)
907208c4	148	{
ba3da734 CL	149	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
ba3da734 CL	150	cpm8xx_t __iomem *cp = &immr->im_cpm;
ba3da734	151	cbd_t __iomem tbdf, rbdf;
907208c4	152	int tm;
fb0204e4	153	size_t count = (bitlen + 7) / 8;
907208c4	154
fb0204e4 CL	155	if (count > MAX_BUFFER)
fb0204e4 CL	156	return -EINVAL;
907208c4	157
ba3da734 CL	158	tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
ba3da734 CL	159	rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
907208c4 CL	160
907208c4 CL	161	/* Set CS for device */
ba3da734	162	clrbits_be32(&cp->cp_pbdat, 0x0001);
907208c4 CL	163
907208c4 CL	164	/* Setting tx bd status and data length */
fb0204e4	165	out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
ba3da734 CL	166	out_be16(&tbdf->cbd_sc, BD_SC_READY \| BD_SC_LAST \| BD_SC_WRAP);
ba3da734 CL	167	out_be16(&tbdf->cbd_datlen, count);
907208c4 CL	168
907208c4 CL	169	/* Setting rx bd status and data length */
fb0204e4	170	out_be32(&rbdf->cbd_bufaddr, (ulong)din);
ba3da734 CL	171	out_be16(&rbdf->cbd_sc, BD_SC_EMPTY \| BD_SC_WRAP);
	172	out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
	173
	174	clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV \| SPMODE_MSTR \|
	175	SPMODE_EN \| SPMODE_LEN(8) \| SPMODE_PM(0x8));
	176	out_8(&cp->cp_spim, 0); /* Mask all SPI events */
	177	out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
907208c4 CL	178
907208c4 CL	179	/* start spi transfer */
ba3da734	180	setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
907208c4 CL	181
	182	/* --------------------------------
	183	* Wait for SPI transmit to get out
	184	* or time out (1 second = 1000 ms)
	185	* -------------------------------- */
70fd0710	186	for (tm = 0; tm < 1000; ++tm) {
ba3da734	187	if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
907208c4	188	break;
ba3da734	189	if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
907208c4	190	break;
70fd0710	191	udelay(1000);
907208c4	192	}
70fd0710 CL	193	if (tm >= 1000)
70fd0710 CL	194	printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
907208c4 CL	195
907208c4 CL	196	/* Clear CS for device */
ba3da734	197	setbits_be32(&cp->cp_pbdat, 0x0001);
907208c4 CL	198
	199	return count;
	200	}
fb0204e4 CL	201
	202	static const struct dm_spi_ops mpc8xx_spi_ops = {
	203	.xfer = mpc8xx_spi_xfer,
	204	};
	205
	206	static const struct udevice_id mpc8xx_spi_ids[] = {
	207	{ .compatible = "fsl,mpc8xx-spi" },
	208	{ }
	209	};
	210
	211	U_BOOT_DRIVER(mpc8xx_spi) = {
	212	.name = "mpc8xx_spi",
	213	.id = UCLASS_SPI,
	214	.of_match = mpc8xx_spi_ids,
	215	.ops = &mpc8xx_spi_ops,
	216	.probe = mpc8xx_spi_probe,
	217	};