[J-u-boot.git] / board / advantech / dms-ba16 / dms-ba16.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2016 Timesys Corporation
 * Copyright 2016 Advantech Corporation
 * Copyright 2012 Freescale Semiconductor, Inc.
 */

#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <input.h>
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR;

#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_HYS)

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)

#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)

#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)

#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
	PAD_CTL_ODE | PAD_CTL_SRE_FAST)

#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const uart3_pads[] = {
	MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const uart4_pads[] = {
	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const enet_pads[] = {
	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	/* AR8033 PHY Reset */
	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

	/* Reset AR8033 PHY */
	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
	mdelay(10);
	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
	mdelay(1);
}

static iomux_v3_cfg_t const usdhc2_pads[] = {
	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc4_pads[] = {
	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const ecspi1_pads[] = {
	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
		.gp = IMX_GPIO_NR(5, 27)
	},
	.sda = {
		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
		.gp = IMX_GPIO_NR(5, 26)
	}
};

static struct i2c_pads_info i2c_pad_info2 = {
	.scl = {
		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
		.gp = IMX_GPIO_NR(4, 12)
	},
	.sda = {
		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
		.gp = IMX_GPIO_NR(4, 13)
	}
};

static struct i2c_pads_info i2c_pad_info3 = {
	.scl = {
		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 3)
	},
	.sda = {
		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 6)
	}
};

#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
}

static void setup_spi(void)
{
	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
#endif

static iomux_v3_cfg_t const pcie_pads[] = {
	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_pcie(void)
{
	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
}

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}

#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
	{USDHC2_BASE_ADDR},
	{USDHC3_BASE_ADDR},
	{USDHC4_BASE_ADDR},
};

#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 11)

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		ret = 1; /* eMMC is always present */
		break;
	case USDHC4_BASE_ADDR:
		ret = !gpio_get_value(USDHC4_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;
	int i;

	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
			gpio_direction_input(USDHC2_CD_GPIO);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			break;
		case 2:
			imx_iomux_v3_setup_multiple_pads(
				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
			gpio_direction_input(USDHC4_CD_GPIO);
			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
			break;
		default:
			printf("Warning: you configured more USDHC controllers\n"
			       "(%d) then supported by the board (%d)\n",
			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret)
			return ret;
	}

	return 0;
}
#endif

static int mx6_rgmii_rework(struct phy_device *phydev)
{
	/* set device address 0x7 */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	/* offset 0x8016: CLK_25M Clock Select */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	/* enable register write, no post increment, address 0x7 */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	/* set to 125 MHz from local PLL source */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
	/* set debug port address: SerDes Test and System Mode Control */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
	/* enable rgmii tx clock delay */
	/* set the reserved bits to avoid board specific voltage peak issue*/
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
	/* Power for LVDS Display */
	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
	/* Backlight enable for LVDS display */
	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
	/* backlight PWM brightness control */
	MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void do_enable_hdmi(struct display_info_t const *dev)
{
	imx_enable_hdmi_phy();
}

int board_cfb_skip(void)
{
	gpio_direction_output(LVDS_POWER_GP, 1);

	return 0;
}

static int detect_baseboard(struct display_info_t const *dev)
{
	return 0 == dev->addr;
}

struct display_info_t const displays[] = {{
	.bus	= -1,
	.addr	= 0,
	.pixfmt	= IPU_PIX_FMT_RGB24,
	.detect	= detect_baseboard,
	.enable	= NULL,
	.mode	= {
		.name           = "SHARP-LQ156M1LG21",
		.refresh        = 60,
		.xres           = 1920,
		.yres           = 1080,
		.pixclock       = 7851,
		.left_margin    = 100,
		.right_margin   = 40,
		.upper_margin   = 30,
		.lower_margin   = 3,
		.hsync_len      = 10,
		.vsync_len      = 2,
		.sync           = FB_SYNC_EXT,
		.vmode          = FB_VMODE_NONINTERLACED
} }, {
	.bus	= -1,
	.addr	= 3,
	.pixfmt	= IPU_PIX_FMT_RGB24,
	.detect	= detect_hdmi,
	.enable	= do_enable_hdmi,
	.mode	= {
		.name           = "HDMI",
		.refresh        = 60,
		.xres           = 1024,
		.yres           = 768,
		.pixclock       = 15385,
		.left_margin    = 220,
		.right_margin   = 40,
		.upper_margin   = 21,
		.lower_margin   = 7,
		.hsync_len      = 60,
		.vsync_len      = 10,
		.sync           = FB_SYNC_EXT,
		.vmode          = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);

static void setup_display(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);

	imx_setup_hdmi();

	/* Set LDB_DI0 as clock source for IPU_DI0 */
	clrsetbits_le32(&mxc_ccm->chsccdr,
			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
			(CHSCCDR_CLK_SEL_LDB_DI0 <<
			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));

	/* Turn on IPU LDB DI0 clocks */
	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);

	enable_ipu_clock();

	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
	       &iomux->gpr[2]);

	clrsetbits_le32(&iomux->gpr[3],
			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
			IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
			IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
		       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));

	/* backlights off until needed */
	imx_iomux_v3_setup_multiple_pads(backlight_pads,
					 ARRAY_SIZE(backlight_pads));

	gpio_direction_input(LVDS_POWER_GP);
	gpio_direction_input(LVDS_BACKLIGHT_GP);
}
#endif /* CONFIG_VIDEO_IPUV3 */

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

int board_eth_init(bd_t *bis)
{
	setup_iomux_enet();
	setup_pcie();

	return cpu_eth_init(bis);
}

static iomux_v3_cfg_t const misc_pads[] = {
	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
};
#define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
#define WIFI_EN	IMX_GPIO_NR(6, 14)

int setup_ba16_sata(void)
{
	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int ret;

	ret = enable_sata_clock();
	if (ret)
		return ret;

	clrsetbits_le32(&iomuxc_regs->gpr[13],
			IOMUXC_GPR13_SATA_MASK,
			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
			|IOMUXC_GPR13_SATA_SPEED_3G
			|(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
			|IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
			|IOMUXC_GPR13_SATA_PHY_1_SLOW);

	return 0;
}

int board_early_init_f(void)
{
	imx_iomux_v3_setup_multiple_pads(misc_pads,
					 ARRAY_SIZE(misc_pads));

	setup_iomux_uart();

#if defined(CONFIG_VIDEO_IPUV3)
	/* Set LDB clock to PLL2 PFD0 */
	select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
#endif
	return 0;
}

int board_init(void)
{
	gpio_direction_output(SUS_S3_OUT, 1);
	gpio_direction_output(WIFI_EN, 1);
#if defined(CONFIG_VIDEO_IPUV3)
	setup_display();
#endif
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_MXC_SPI
	setup_spi();
#endif
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

void pmic_init(void)
{

#define DA9063_ADDR 0x58
#define BCORE2_CONF 0x9D
#define BCORE1_CONF 0x9E
#define BPRO_CONF 0x9F
#define BIO_CONF 0xA0
#define BMEM_CONF 0xA1
#define BPERI_CONF 0xA2
#define MODE_BIT_H 7
#define MODE_BIT_L 6

        uchar val;
        i2c_set_bus_num(2);

        i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
        val |= (1 << MODE_BIT_H);
        val &= ~(1 << MODE_BIT_L);
        i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);

        i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
        val |= (1 << MODE_BIT_H);
        val &= ~(1 << MODE_BIT_L);
        i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);

        i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
        val |= (1 << MODE_BIT_H);
        val &= ~(1 << MODE_BIT_L);
        i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);

        i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
        val |= (1 << MODE_BIT_H);
        val &= ~(1 << MODE_BIT_L);
        i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);

        i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
        val |= (1 << MODE_BIT_H);
        val &= ~(1 << MODE_BIT_L);
        i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);

        i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
        val |= (1 << MODE_BIT_H);
        val &= ~(1 << MODE_BIT_L);
        i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);

}

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

#if defined(CONFIG_VIDEO_IPUV3)
	/*
	 * We need at least 200ms between power on and backlight on
	 * as per specifications from CHI MEI
	 */
	mdelay(250);

	/* enable backlight PWM 1 */
	pwm_init(0, 0, 0);

	/* duty cycle 5000000ns, period: 5000000ns */
	pwm_config(0, 5000000, 5000000);

	/* Backlight Power */
	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);

	pwm_enable(0);
#endif

#ifdef CONFIG_SATA
	setup_ba16_sata();
#endif

        /* board specific pmic init */
        pmic_init();

	return 0;
}

int checkboard(void)
{
	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
ff383220 AB	2	/*
	3	* Copyright 2016 Timesys Corporation
	4	* Copyright 2016 Advantech Corporation
	5	* Copyright 2012 Freescale Semiconductor, Inc.
ff383220 AB	6	*/
ff383220 AB	7
5255932f	8	#include <init.h>
90526e9f	9	#include <net.h>
ff383220 AB	10	#include <asm/arch/clock.h>
	11	#include <asm/arch/imx-regs.h>
	12	#include <asm/arch/iomux.h>
	13	#include <asm/arch/mx6-pins.h>
c05ed00a	14	#include <linux/delay.h>
1221ce45	15	#include <linux/errno.h>
ff383220	16	#include <asm/gpio.h>
552a848e SB	17	#include <asm/mach-imx/mxc_i2c.h>
	18	#include <asm/mach-imx/iomux-v3.h>
	19	#include <asm/mach-imx/boot_mode.h>
	20	#include <asm/mach-imx/video.h>
ff383220	21	#include <mmc.h>
e37ac717	22	#include <fsl_esdhc_imx.h>
ff383220 AB	23	#include <miiphy.h>
	24	#include <netdev.h>
	25	#include <asm/arch/mxc_hdmi.h>
	26	#include <asm/arch/crm_regs.h>
	27	#include <asm/io.h>
	28	#include <asm/arch/sys_proto.h>
	29	#include <i2c.h>
7594c51a	30	#include <input.h>
ff383220 AB	31	#include <pwm.h>
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	35	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	36	PAD_CTL_HYS)
	37
	38	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	39	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	40	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	41
	42	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	43	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	44	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	45
	46	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	47	PAD_CTL_SPEED_HIGH \| PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST)
	48
	49	#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED \| \
	50	PAD_CTL_DSE_120ohm \| PAD_CTL_SRE_FAST)
	51
	52	#define ENET_RX_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	53	PAD_CTL_SPEED_HIGH \| PAD_CTL_SRE_FAST)
	54
	55	#define SPI_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
	56	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	57
	58	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	59	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	60	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	61
	62	#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
	63
	64	int dram_init(void)
	65	{
	66	gd->ram_size = imx_ddr_size();
	67
	68	return 0;
	69	}
	70
	71	static iomux_v3_cfg_t const uart3_pads[] = {
	72	MX6_PAD_EIM_D31__UART3_RTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL),
	73	MX6_PAD_EIM_D23__UART3_CTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL),
	74	MX6_PAD_EIM_D24__UART3_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	75	MX6_PAD_EIM_D25__UART3_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	76	};
	77
	78	static iomux_v3_cfg_t const uart4_pads[] = {
	79	MX6_PAD_KEY_COL0__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	80	MX6_PAD_KEY_ROW0__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	81	};
	82
	83	static iomux_v3_cfg_t const enet_pads[] = {
	84	MX6_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	85	MX6_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	86	MX6_PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	87	MX6_PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	88	MX6_PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	89	MX6_PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	90	MX6_PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	91	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	92	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
	93	MX6_PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	94	MX6_PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
95	MX6_PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
96	MX6_PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
97	MX6_PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
98	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
99	/* AR8033 PHY Reset */
100	MX6_PAD_ENET_TX_EN__GPIO1_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL),
101	};
102
103	static void setup_iomux_enet(void)
104	{
105	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
106
107	/* Reset AR8033 PHY */
108	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
0254006b	109	mdelay(10);
ff383220	110	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
0254006b	111	mdelay(1);
ff383220 AB	112	}
	113
	114	static iomux_v3_cfg_t const usdhc2_pads[] = {
	115	MX6_PAD_SD2_CLK__SD2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	116	MX6_PAD_SD2_CMD__SD2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	117	MX6_PAD_SD2_DAT0__SD2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	118	MX6_PAD_SD2_DAT1__SD2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	119	MX6_PAD_SD2_DAT2__SD2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	120	MX6_PAD_SD2_DAT3__SD2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	121	MX6_PAD_GPIO_4__GPIO1_IO04 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	122	};
	123
	124	static iomux_v3_cfg_t const usdhc3_pads[] = {
	125	MX6_PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	126	MX6_PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	127	MX6_PAD_SD3_RST__SD3_RESET \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	128	MX6_PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	129	MX6_PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	130	MX6_PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	131	MX6_PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	132	MX6_PAD_SD3_DAT4__SD3_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	133	MX6_PAD_SD3_DAT5__SD3_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	134	MX6_PAD_SD3_DAT6__SD3_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	135	MX6_PAD_SD3_DAT7__SD3_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	136	};
	137
	138	static iomux_v3_cfg_t const usdhc4_pads[] = {
	139	MX6_PAD_SD4_CLK__SD4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	140	MX6_PAD_SD4_CMD__SD4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	141	MX6_PAD_SD4_DAT0__SD4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	142	MX6_PAD_SD4_DAT1__SD4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	143	MX6_PAD_SD4_DAT2__SD4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	144	MX6_PAD_SD4_DAT3__SD4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	145	MX6_PAD_SD4_DAT4__SD4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	146	MX6_PAD_SD4_DAT5__SD4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	147	MX6_PAD_SD4_DAT6__SD4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	148	MX6_PAD_SD4_DAT7__SD4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	149	MX6_PAD_NANDF_CS0__GPIO6_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	150	MX6_PAD_NANDF_CS1__GPIO6_IO14 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	151	};
	152
	153	static iomux_v3_cfg_t const ecspi1_pads[] = {
	154	MX6_PAD_EIM_D16__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	155	MX6_PAD_EIM_D17__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	156	MX6_PAD_EIM_D18__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	157	MX6_PAD_EIM_EB2__GPIO2_IO30 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	158	};
	159
	160	static struct i2c_pads_info i2c_pad_info1 = {
	161	.scl = {
	162	.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL \| I2C_PAD,
	163	.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 \| I2C_PAD,
	164	.gp = IMX_GPIO_NR(5, 27)
	165	},
	166	.sda = {
	167	.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA \| I2C_PAD,
	168	.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 \| I2C_PAD,
	169	.gp = IMX_GPIO_NR(5, 26)
	170	}
	171	};
	172
	173	static struct i2c_pads_info i2c_pad_info2 = {
	174	.scl = {
	175	.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL \| I2C_PAD,
176	.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 \| I2C_PAD,
177	.gp = IMX_GPIO_NR(4, 12)
178	},
179	.sda = {
180	.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA \| I2C_PAD,
181	.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 \| I2C_PAD,
182	.gp = IMX_GPIO_NR(4, 13)
183	}
184	};
185
186	static struct i2c_pads_info i2c_pad_info3 = {
187	.scl = {
188	.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL \| I2C_PAD,
189	.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 \| I2C_PAD,
190	.gp = IMX_GPIO_NR(1, 3)
191	},
192	.sda = {
193	.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA \| I2C_PAD,
194	.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 \| I2C_PAD,
195	.gp = IMX_GPIO_NR(1, 6)
196	}
197	};
198
199	#ifdef CONFIG_MXC_SPI
200	int board_spi_cs_gpio(unsigned bus, unsigned cs)
201	{
202	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
203	}
204
205	static void setup_spi(void)
206	{
207	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
208	}
209	#endif
210
211	static iomux_v3_cfg_t const pcie_pads[] = {
212	MX6_PAD_GPIO_5__GPIO1_IO05 \| MUX_PAD_CTRL(NO_PAD_CTRL),
213	MX6_PAD_GPIO_17__GPIO7_IO12 \| MUX_PAD_CTRL(NO_PAD_CTRL),
214	};
215
216	static void setup_pcie(void)
217	{
218	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
219	}
220
221	static void setup_iomux_uart(void)
222	{
223	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
224	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
225	}
226
e37ac717	227	#ifdef CONFIG_FSL_ESDHC_IMX
ff383220 AB	228	struct fsl_esdhc_cfg usdhc_cfg[3] = {
	229	{USDHC2_BASE_ADDR},
	230	{USDHC3_BASE_ADDR},
	231	{USDHC4_BASE_ADDR},
	232	};
	233
	234	#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
	235	#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
	236
	237	int board_mmc_getcd(struct mmc *mmc)
	238	{
	239	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	240	int ret = 0;
	241
	242	switch (cfg->esdhc_base) {
	243	case USDHC2_BASE_ADDR:
	244	ret = !gpio_get_value(USDHC2_CD_GPIO);
	245	break;
	246	case USDHC3_BASE_ADDR:
	247	ret = 1; /* eMMC is always present */
	248	break;
	249	case USDHC4_BASE_ADDR:
	250	ret = !gpio_get_value(USDHC4_CD_GPIO);
	251	break;
	252	}
	253
	254	return ret;
	255	}
	256
	257	int board_mmc_init(bd_t *bis)
	258	{
	259	int ret;
	260	int i;
	261
	262	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	263	switch (i) {
	264	case 0:
	265	imx_iomux_v3_setup_multiple_pads(
	266	usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
	267	gpio_direction_input(USDHC2_CD_GPIO);
	268	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	269	break;
	270	case 1:
	271	imx_iomux_v3_setup_multiple_pads(
	272	usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	273	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	274	break;
	275	case 2:
	276	imx_iomux_v3_setup_multiple_pads(
	277	usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
	278	gpio_direction_input(USDHC4_CD_GPIO);
	279	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	280	break;
	281	default:
	282	printf("Warning: you configured more USDHC controllers\n"
	283	"(%d) then supported by the board (%d)\n",
	284	i + 1, CONFIG_SYS_FSL_USDHC_NUM);
	285	return -EINVAL;
	286	}
	287
	288	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	289	if (ret)
	290	return ret;
	291	}
292
293	return 0;
294	}
295	#endif
296
297	static int mx6_rgmii_rework(struct phy_device *phydev)
298	{
299	/* set device address 0x7 */
300	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
301	/* offset 0x8016: CLK_25M Clock Select */
302	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
303	/* enable register write, no post increment, address 0x7 */
304	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
305	/* set to 125 MHz from local PLL source */
306	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
307	/* set debug port address: SerDes Test and System Mode Control */
308	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
309	/* enable rgmii tx clock delay */
fab70acf YCL	310	/* set the reserved bits to avoid board specific voltage peak issue*/
fab70acf YCL	311	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
ff383220 AB	312
	313	return 0;
	314	}
	315
	316	int board_phy_config(struct phy_device *phydev)
	317	{
	318	mx6_rgmii_rework(phydev);
	319
	320	if (phydev->drv->config)
	321	phydev->drv->config(phydev);
	322
	323	return 0;
	324	}
	325
	326	#if defined(CONFIG_VIDEO_IPUV3)
	327	static iomux_v3_cfg_t const backlight_pads[] = {
	328	/* Power for LVDS Display */
	329	MX6_PAD_EIM_D22__GPIO3_IO22 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	330	#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
	331	/* Backlight enable for LVDS display */
	332	MX6_PAD_GPIO_0__GPIO1_IO00 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	333	#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
	334	/* backlight PWM brightness control */
	335	MX6_PAD_SD1_DAT3__PWM1_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL),
	336	};
	337
	338	static void do_enable_hdmi(struct display_info_t const *dev)
	339	{
	340	imx_enable_hdmi_phy();
	341	}
	342
	343	int board_cfb_skip(void)
	344	{
	345	gpio_direction_output(LVDS_POWER_GP, 1);
	346
	347	return 0;
	348	}
	349
	350	static int detect_baseboard(struct display_info_t const *dev)
	351	{
	352	return 0 == dev->addr;
	353	}
	354
	355	struct display_info_t const displays[] = {{
	356	.bus = -1,
	357	.addr = 0,
	358	.pixfmt = IPU_PIX_FMT_RGB24,
	359	.detect = detect_baseboard,
	360	.enable = NULL,
	361	.mode = {
	362	.name = "SHARP-LQ156M1LG21",
	363	.refresh = 60,
	364	.xres = 1920,
	365	.yres = 1080,
	366	.pixclock = 7851,
	367	.left_margin = 100,
	368	.right_margin = 40,
	369	.upper_margin = 30,
	370	.lower_margin = 3,
	371	.hsync_len = 10,
	372	.vsync_len = 2,
	373	.sync = FB_SYNC_EXT,
	374	.vmode = FB_VMODE_NONINTERLACED
	375	} }, {
376	.bus = -1,
377	.addr = 3,
378	.pixfmt = IPU_PIX_FMT_RGB24,
379	.detect = detect_hdmi,
380	.enable = do_enable_hdmi,
381	.mode = {
382	.name = "HDMI",
383	.refresh = 60,
384	.xres = 1024,
385	.yres = 768,
386	.pixclock = 15385,
387	.left_margin = 220,
388	.right_margin = 40,
389	.upper_margin = 21,
390	.lower_margin = 7,
391	.hsync_len = 60,
392	.vsync_len = 10,
393	.sync = FB_SYNC_EXT,
394	.vmode = FB_VMODE_NONINTERLACED
395	} } };
396	size_t display_count = ARRAY_SIZE(displays);
397
398	static void setup_display(void)
399	{
400	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
401	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
402
403	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
404
405	imx_setup_hdmi();
406
407	/* Set LDB_DI0 as clock source for IPU_DI0 */
408	clrsetbits_le32(&mxc_ccm->chsccdr,
409	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
410	(CHSCCDR_CLK_SEL_LDB_DI0 <<
411	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
412
413	/* Turn on IPU LDB DI0 clocks */
414	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
415
416	enable_ipu_clock();
417
418	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES \|
419	IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH \|
420	IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW \|
421	IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG \|
422	IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT \|
423	IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG \|
424	IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT \|
425	IOMUXC_GPR2_SPLIT_MODE_EN_MASK \|
426	IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 \|
427	IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
428	&iomux->gpr[2]);
429
430	clrsetbits_le32(&iomux->gpr[3],
431	IOMUXC_GPR3_LVDS0_MUX_CTL_MASK \|
432	IOMUXC_GPR3_LVDS1_MUX_CTL_MASK \|
433	IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
434	(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
435	IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
436
437	/* backlights off until needed */
438	imx_iomux_v3_setup_multiple_pads(backlight_pads,
439	ARRAY_SIZE(backlight_pads));
440
441	gpio_direction_input(LVDS_POWER_GP);
442	gpio_direction_input(LVDS_BACKLIGHT_GP);
443	}
444	#endif /* CONFIG_VIDEO_IPUV3 */
445
446	/*
447	* Do not overwrite the console
448	* Use always serial for U-Boot console
449	*/
450	int overwrite_console(void)
451	{
452	return 1;
453	}
454
455	int board_eth_init(bd_t *bis)
456	{
457	setup_iomux_enet();
458	setup_pcie();
459
460	return cpu_eth_init(bis);
461	}
462
463	static iomux_v3_cfg_t const misc_pads[] = {
464	MX6_PAD_KEY_ROW2__GPIO4_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
465	MX6_PAD_EIM_A25__GPIO5_IO02 \| MUX_PAD_CTRL(NC_PAD_CTRL),
466	MX6_PAD_EIM_CS0__GPIO2_IO23 \| MUX_PAD_CTRL(NC_PAD_CTRL),
467	MX6_PAD_EIM_CS1__GPIO2_IO24 \| MUX_PAD_CTRL(NC_PAD_CTRL),
468	MX6_PAD_EIM_OE__GPIO2_IO25 \| MUX_PAD_CTRL(NC_PAD_CTRL),
469	MX6_PAD_EIM_BCLK__GPIO6_IO31 \| MUX_PAD_CTRL(NC_PAD_CTRL),
470	MX6_PAD_GPIO_1__GPIO1_IO01 \| MUX_PAD_CTRL(NC_PAD_CTRL),
471	};
472	#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
473	#define WIFI_EN IMX_GPIO_NR(6, 14)
474
475	int setup_ba16_sata(void)
476	{
477	struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
478	int ret;
479
480	ret = enable_sata_clock();
481	if (ret)
482	return ret;
483
484	clrsetbits_le32(&iomuxc_regs->gpr[13],
485	IOMUXC_GPR13_SATA_MASK,
486	IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
487	\|IOMUXC_GPR13_SATA_PHY_7_SATA2M
488	\|IOMUXC_GPR13_SATA_SPEED_3G
489	\|(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
490	\|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
491	\|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
492	\|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
493	\|IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
494	\|IOMUXC_GPR13_SATA_PHY_1_SLOW);
495
496	return 0;
497	}
498
499	int board_early_init_f(void)
500	{
501	imx_iomux_v3_setup_multiple_pads(misc_pads,
502	ARRAY_SIZE(misc_pads));
503
504	setup_iomux_uart();
505
506	#if defined(CONFIG_VIDEO_IPUV3)
507	/* Set LDB clock to PLL2 PFD0 */
508	select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
509	#endif
510	return 0;
511	}
512
513	int board_init(void)
514	{
515	gpio_direction_output(SUS_S3_OUT, 1);
516	gpio_direction_output(WIFI_EN, 1);
517	#if defined(CONFIG_VIDEO_IPUV3)
518	setup_display();
519	#endif
520	/* address of boot parameters */
521	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
522
523	#ifdef CONFIG_MXC_SPI
524	setup_spi();
525	#endif
526	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
527	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
528	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
529
530	return 0;
531	}
532
533	#ifdef CONFIG_CMD_BMODE
534	static const struct boot_mode board_boot_modes[] = {
535	/* 4 bit bus width */
536	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
537	{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
538	{NULL, 0},
539	};
540	#endif
541
fc9ade56 YCL	542	void pmic_init(void)
	543	{
	544
	545	#define DA9063_ADDR 0x58
	546	#define BCORE2_CONF 0x9D
	547	#define BCORE1_CONF 0x9E
	548	#define BPRO_CONF 0x9F
	549	#define BIO_CONF 0xA0
	550	#define BMEM_CONF 0xA1
	551	#define BPERI_CONF 0xA2
	552	#define MODE_BIT_H 7
	553	#define MODE_BIT_L 6
	554
	555	uchar val;
	556	i2c_set_bus_num(2);
	557
	558	i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
	559	val \|= (1 << MODE_BIT_H);
	560	val &= ~(1 << MODE_BIT_L);
	561	i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
	562
	563	i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
	564	val \|= (1 << MODE_BIT_H);
	565	val &= ~(1 << MODE_BIT_L);
	566	i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
	567
	568	i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
	569	val \|= (1 << MODE_BIT_H);
	570	val &= ~(1 << MODE_BIT_L);
	571	i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
	572
	573	i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
	574	val \|= (1 << MODE_BIT_H);
	575	val &= ~(1 << MODE_BIT_L);
	576	i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
	577
	578	i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
	579	val \|= (1 << MODE_BIT_H);
	580	val &= ~(1 << MODE_BIT_L);
	581	i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
	582
	583	i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
	584	val \|= (1 << MODE_BIT_H);
	585	val &= ~(1 << MODE_BIT_L);
	586	i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
	587
	588	}
	589
ff383220 AB	590	int board_late_init(void)
	591	{
	592	#ifdef CONFIG_CMD_BMODE
	593	add_board_boot_modes(board_boot_modes);
	594	#endif
f6f7e73d YCL	595
f6f7e73d YCL	596	#if defined(CONFIG_VIDEO_IPUV3)
ff383220 AB	597	/*
	598	* We need at least 200ms between power on and backlight on
	599	* as per specifications from CHI MEI
	600	*/
	601	mdelay(250);
	602
	603	/* enable backlight PWM 1 */
	604	pwm_init(0, 0, 0);
	605
	606	/* duty cycle 5000000ns, period: 5000000ns */
	607	pwm_config(0, 5000000, 5000000);
	608
	609	/* Backlight Power */
	610	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
	611
	612	pwm_enable(0);
f6f7e73d	613	#endif
ff383220	614
10e40d54	615	#ifdef CONFIG_SATA
ff383220 AB	616	setup_ba16_sata();
	617	#endif
	618
fc9ade56 YCL	619	/* board specific pmic init */
	620	pmic_init();
	621
ff383220 AB	622	return 0;
	623	}
	624
	625	int checkboard(void)
	626	{
	627	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
	628	return 0;
	629	}