]>
Commit | Line | Data |
---|---|---|
a8cb4fb5 SG |
1 | /* |
2 | * Copyright (c) 2013 Google, Inc | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <clk.h> | |
9 | #include <dm.h> | |
10 | #include <dwmmc.h> | |
11 | #include <errno.h> | |
e1efec4e | 12 | #include <pwrseq.h> |
a8cb4fb5 | 13 | #include <syscon.h> |
e1efec4e | 14 | #include <asm/gpio.h> |
a8cb4fb5 SG |
15 | #include <asm/arch/clock.h> |
16 | #include <asm/arch/periph.h> | |
17 | #include <linux/err.h> | |
18 | ||
19 | DECLARE_GLOBAL_DATA_PTR; | |
20 | ||
f6e41d17 SG |
21 | struct rockchip_mmc_plat { |
22 | struct mmc_config cfg; | |
23 | struct mmc mmc; | |
24 | }; | |
25 | ||
a8cb4fb5 | 26 | struct rockchip_dwmmc_priv { |
135aa950 | 27 | struct clk clk; |
a8cb4fb5 SG |
28 | struct dwmci_host host; |
29 | }; | |
30 | ||
31 | static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) | |
32 | { | |
33 | struct udevice *dev = host->priv; | |
34 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); | |
35 | int ret; | |
36 | ||
135aa950 | 37 | ret = clk_set_rate(&priv->clk, freq); |
a8cb4fb5 SG |
38 | if (ret < 0) { |
39 | debug("%s: err=%d\n", __func__, ret); | |
40 | return ret; | |
41 | } | |
42 | ||
43 | return freq; | |
44 | } | |
45 | ||
46 | static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) | |
47 | { | |
48 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); | |
49 | struct dwmci_host *host = &priv->host; | |
50 | ||
51 | host->name = dev->name; | |
52 | host->ioaddr = (void *)dev_get_addr(dev); | |
53 | host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, | |
54 | "bus-width", 4); | |
55 | host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; | |
56 | host->priv = dev; | |
57 | ||
ace2198b | 58 | /* use non-removeable as sdcard and emmc as judgement */ |
59 | if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable")) | |
6579385b | 60 | host->dev_index = 0; |
61 | else | |
ace2198b | 62 | host->dev_index = 1; |
a8cb4fb5 SG |
63 | |
64 | return 0; | |
65 | } | |
66 | ||
67 | static int rockchip_dwmmc_probe(struct udevice *dev) | |
68 | { | |
f6e41d17 | 69 | struct rockchip_mmc_plat *plat = dev_get_platdata(dev); |
a8cb4fb5 SG |
70 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
71 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); | |
72 | struct dwmci_host *host = &priv->host; | |
e1efec4e | 73 | struct udevice *pwr_dev __maybe_unused; |
a8cb4fb5 SG |
74 | u32 minmax[2]; |
75 | int ret; | |
28637248 | 76 | int fifo_depth; |
a8cb4fb5 | 77 | |
898d6439 SG |
78 | ret = clk_get_by_index(dev, 0, &priv->clk); |
79 | if (ret < 0) | |
a8cb4fb5 SG |
80 | return ret; |
81 | ||
28637248 | 82 | if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, |
83 | "clock-freq-min-max", minmax, 2)) | |
84 | return -EINVAL; | |
85 | ||
86 | fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, | |
87 | "fifo-depth", 0); | |
88 | if (fifo_depth < 0) | |
89 | return -EINVAL; | |
90 | ||
91 | host->fifoth_val = MSIZE(0x2) | | |
92 | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); | |
93 | ||
94 | if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode")) | |
95 | host->fifo_mode = true; | |
96 | ||
e1efec4e SG |
97 | #ifdef CONFIG_PWRSEQ |
98 | /* Enable power if needed */ | |
99 | ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", | |
100 | &pwr_dev); | |
101 | if (!ret) { | |
102 | ret = pwrseq_set_power(pwr_dev, true); | |
103 | if (ret) | |
104 | return ret; | |
105 | } | |
106 | #endif | |
f6e41d17 SG |
107 | dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps, |
108 | minmax[1], minmax[0]); | |
109 | host->mmc = &plat->mmc; | |
f6e41d17 | 110 | host->mmc->priv = &priv->host; |
cffe5d86 | 111 | host->mmc->dev = dev; |
a8cb4fb5 SG |
112 | upriv->mmc = host->mmc; |
113 | ||
42b37d8d | 114 | return dwmci_probe(dev); |
a8cb4fb5 SG |
115 | } |
116 | ||
f6e41d17 SG |
117 | static int rockchip_dwmmc_bind(struct udevice *dev) |
118 | { | |
f6e41d17 SG |
119 | struct rockchip_mmc_plat *plat = dev_get_platdata(dev); |
120 | int ret; | |
121 | ||
122 | ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); | |
123 | if (ret) | |
124 | return ret; | |
f6e41d17 SG |
125 | |
126 | return 0; | |
127 | } | |
128 | ||
a8cb4fb5 SG |
129 | static const struct udevice_id rockchip_dwmmc_ids[] = { |
130 | { .compatible = "rockchip,rk3288-dw-mshc" }, | |
131 | { } | |
132 | }; | |
133 | ||
134 | U_BOOT_DRIVER(rockchip_dwmmc_drv) = { | |
135 | .name = "rockchip_dwmmc", | |
136 | .id = UCLASS_MMC, | |
137 | .of_match = rockchip_dwmmc_ids, | |
138 | .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, | |
42b37d8d | 139 | .ops = &dm_dwmci_ops, |
f6e41d17 | 140 | .bind = rockchip_dwmmc_bind, |
a8cb4fb5 SG |
141 | .probe = rockchip_dwmmc_probe, |
142 | .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), | |
f6e41d17 | 143 | .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), |
a8cb4fb5 | 144 | }; |
e1efec4e SG |
145 | |
146 | #ifdef CONFIG_PWRSEQ | |
147 | static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) | |
148 | { | |
149 | struct gpio_desc reset; | |
150 | int ret; | |
151 | ||
152 | ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); | |
153 | if (ret) | |
154 | return ret; | |
155 | dm_gpio_set_value(&reset, 1); | |
156 | udelay(1); | |
157 | dm_gpio_set_value(&reset, 0); | |
158 | udelay(200); | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { | |
164 | .set_power = rockchip_dwmmc_pwrseq_set_power, | |
165 | }; | |
166 | ||
167 | static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { | |
168 | { .compatible = "mmc-pwrseq-emmc" }, | |
169 | { } | |
170 | }; | |
171 | ||
172 | U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { | |
173 | .name = "mmc_pwrseq_emmc", | |
174 | .id = UCLASS_PWRSEQ, | |
175 | .of_match = rockchip_dwmmc_pwrseq_ids, | |
176 | .ops = &rockchip_dwmmc_pwrseq_ops, | |
177 | }; | |
178 | #endif |