[J-u-boot.git] / include / asm-ppc / immap_512x.h

/*
 * (C) Copyright 2007 DENX Software Engineering
 *
 * MPC512x Internal Memory Map
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Based on the MPC83xx header.
 */

#ifndef __IMMAP_512x__
#define __IMMAP_512x__

#include <asm/types.h>

typedef struct law512x {
	u32 bar;	/* Base Addr Register */
	u32 ar;		/* Attributes Register */
} law512x_t;

/*
 * System configuration registers
 */
typedef struct sysconf512x {
	u32 immrbar;		/* Internal memory map base address register */
	u8 res0[0x1c];
	u32 lpbaw;		/* LP Boot Access Window */
	u32 lpcs0aw;		/* LP CS0 Access Window */
	u32 lpcs1aw;		/* LP CS1 Access Window */
	u32 lpcs2aw;		/* LP CS2 Access Window */
	u32 lpcs3aw;		/* LP CS3 Access Window */
	u32 lpcs4aw;		/* LP CS4 Access Window */
	u32 lpcs5aw;		/* LP CS5 Access Window */
	u32 lpcs6aw;		/* LP CS6 Access Window */
	u32 lpcs7aw;		/* LP CS7 Access Window */
	u8 res1[0x1c];
	law512x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
	u8 res2[0x28];
	law512x_t ddrlaw;	/* DDR Local Access Window */
	u8 res3[0x18];
	u32 mbxbar;		/* MBX Base Address */
	u32 srambar;		/* SRAM Base Address */
	u32 nfcbar;		/* NFC Base Address */
	u8 res4[0x34];
	u32 spridr;		/* System Part and Revision ID Register */
	u32 spcr;		/* System Priority Configuration Register */
	u8 res5[0xf8];
} sysconf512x_t;

/*
 * Watch Dog Timer (WDT) Registers
 */
typedef struct wdt512x {
	u8 res0[4];
	u32 swcrr;		/* System watchdog control register */
	u32 swcnr;		/* System watchdog count register */
	u8 res1[2];
	u16 swsrr;		/* System watchdog service register */
	u8 res2[0xF0];
} wdt512x_t;

/*
 * RTC Module Registers
 */
typedef struct rtclk512x {
	u8 fixme[0x100];
} rtclk512x_t;

/*
 * General Purpose Timer
 */
typedef struct gpt512x {
	u8 fixme[0x100];
} gpt512x_t;

/*
 * Integrated Programmable Interrupt Controller
 */
typedef struct ipic512x {
	u8 fixme[0x100];
} ipic512x_t;

/*
 * System Arbiter Registers
 */
typedef struct arbiter512x {
	u32 acr;		/* Arbiter Configuration Register */
	u32 atr;		/* Arbiter Timers Register */
	u32 ater;		/* Arbiter Transfer Error Register */
	u32 aer;		/* Arbiter Event Register */
	u32 aidr;		/* Arbiter Interrupt Definition Register */
	u32 amr;		/* Arbiter Mask Register */
	u32 aeatr;		/* Arbiter Event Attributes Register */
	u32 aeadr;		/* Arbiter Event Address Register */
	u32 aerr;		/* Arbiter Event Response Register */
	u8 res1[0xDC];
} arbiter512x_t;

/*
 * Reset Module
 */
typedef struct reset512x {
	u32 rcwl;		/* Reset Configuration Word Low Register */
	u32 rcwh;		/* Reset Configuration Word High Register */
	u8 res0[8];
	u32 rsr;		/* Reset Status Register */
	u32 rmr;		/* Reset Mode Register */
	u32 rpr;		/* Reset protection Register */
	u32 rcr;		/* Reset Control Register */
	u32 rcer;		/* Reset Control Enable Register */
	u8 res1[0xDC];
} reset512x_t;

/*
 * Clock Module
 */
typedef struct clk512x {
	u32 spmr;		/* System PLL Mode Register */
	u32 sccr[2];		/* System Clock Control Registers */
	u32 scfr[2];		/* System Clock Frequency Registers */
	u8 res0[4];
	u32 bcr;		/* Bread Crumb Register */
	u32 pscccr[12];		/* PSC0-11 Clock Control Registers */
	u32 spccr;		/* SPDIF Clock Control Registers */
	u32 cccr;		/* CFM Clock Control Registers */
	u32 dccr;		/* DIU Clock Control Registers */
	u8 res1[0xa8];
} clk512x_t;

/*
 * Power Management Control Module
 */
typedef struct pmc512x {
	u8 fixme[0x100];
} pmc512x_t;

/*
 * General purpose I/O module
 */
typedef struct gpio512x {
	u8 fixme[0x100];
} gpio512x_t;

/*
 * DDR Memory Controller Memory Map
 */
typedef struct ddr512x {
	u32 ddr_sys_config;	/* System Configuration Register */
	u32 ddr_time_config0;	/* Timing Configuration Register */
	u32 ddr_time_config1;	/* Timing Configuration Register */
	u32 ddr_time_config2;	/* Timing Configuration Register */
	u32 ddr_command;	/* Command Register */
	u32 ddr_compact_command;	/* Compact Command Register */
	u32 self_refresh_cmd_0;	/* Enter/Exit Self Refresh Registers */
	u32 self_refresh_cmd_1;	/* Enter/Exit Self Refresh Registers */
	u32 self_refresh_cmd_2;	/* Enter/Exit Self Refresh Registers */
	u32 self_refresh_cmd_3;	/* Enter/Exit Self Refresh Registers */
	u32 self_refresh_cmd_4;	/* Enter/Exit Self Refresh Registers */
	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
	u32 DQS_config_offset_count;	/* DQS Config Offset Count */
	u32 DQS_config_offset_time;	/* DQS Config Offset Time */
	u32 DQS_delay_status;	/* DQS Delay Status */
	u32 res0[0xF];
	u32 prioman_config1;	/* Priority Manager Configuration */
	u32 prioman_config2;	/* Priority Manager Configuration */
	u32 hiprio_config;	/* High Priority Configuration */
	u32 lut_table0_main_upper;	/* LUT0 Main Upper */
	u32 lut_table1_main_upper;	/* LUT1 Main Upper */
	u32 lut_table2_main_upper;	/* LUT2 Main Upper */
	u32 lut_table3_main_upper;	/* LUT3 Main Upper */
	u32 lut_table4_main_upper;	/* LUT4 Main Upper */
	u32 lut_table0_main_lower;	/* LUT0 Main Lower */
	u32 lut_table1_main_lower;	/* LUT1 Main Lower */
	u32 lut_table2_main_lower;	/* LUT2 Main Lower */
	u32 lut_table3_main_lower;	/* LUT3 Main Lower */
	u32 lut_table4_main_lower;	/* LUT4 Main Lower */
	u32 lut_table0_alternate_upper;	/* LUT0 Alternate Upper */
	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
	u32 performance_monitor_config;
	u32 event_time_counter;
	u32 event_time_preset;
	u32 performance_monitor1_address_low;
	u32 performance_monitor2_address_low;
	u32 performance_monitor1_address_hi;
	u32 performance_monitor2_address_hi;
	u32 res1[2];
	u32 performance_monitor1_read_counter;
	u32 performance_monitor2_read_counter;
	u32 performance_monitor1_write_counter;
	u32 performance_monitor2_write_counter;
	u32 granted_ack_counter0;
	u32 granted_ack_counter1;
	u32 granted_ack_counter2;
	u32 granted_ack_counter3;
	u32 granted_ack_counter4;
	u32 cumulative_wait_counter0;
	u32 cumulative_wait_counter1;
	u32 cumulative_wait_counter2;
	u32 cumulative_wait_counter3;
	u32 cumulative_wait_counter4;
	u32 summed_priority_counter0;
	u32 summed_priority_counter1;
	u32 summed_priority_counter2;
	u32 summed_priority_counter3;
	u32 summed_priority_counter4;
	u32 res2[0x3AD];
} ddr512x_t;


/*
 * DMA/Messaging Unit
 */
typedef struct dma512x {
	u8 fixme[0x1800];
} dma512x_t;

/*
 * PCI Software Configuration Registers
 */
typedef struct pciconf512x {
	u32 config_address;
	u32 config_data;
	u32 int_ack;
	u8 res[116];
} pciconf512x_t;

/*
 * PCI Outbound Translation Register
 */
typedef struct pci_outbound_window {
	u32 potar;
	u8 res0[4];
	u32 pobar;
	u8 res1[4];
	u32 pocmr;
	u8 res2[4];
} pot512x_t;

/*
 * Sequencer
 */
typedef struct ios512x {
	pot512x_t pot[6];
	u8 res0[0x60];
	u32 pmcr;
	u8 res1[4];
	u32 dtcr;
	u8 res2[4];
} ios512x_t;

/*
 * PCI Controller
 */
typedef struct pcictrl512x {
	u32 esr;
	u32 ecdr;
	u32 eer;
	u32 eatcr;
	u32 eacr;
	u32 eeacr;
	u32 edlcr;
	u32 edhcr;
	u32 gcr;
	u32 ecr;
	u32 gsr;
	u8 res0[12];
	u32 pitar2;
	u8 res1[4];
	u32 pibar2;
	u32 piebar2;
	u32 piwar2;
	u8 res2[4];
	u32 pitar1;
	u8 res3[4];
	u32 pibar1;
	u32 piebar1;
	u32 piwar1;
	u8 res4[4];
	u32 pitar0;
	u8 res5[4];
	u32 pibar0;
	u8 res6[4];
	u32 piwar0;
	u8 res7[132];
} pcictrl512x_t;


/*
 * MSCAN
 */
typedef struct mscan512x {
	u8 fixme[0x100];
} mscan512x_t;

/*
 * BDLC
 */
typedef struct bdlc512x {
	u8 fixme[0x100];
} bdlc512x_t;

/*
 * SDHC
 */
typedef struct sdhc512x {
	u8 fixme[0x100];
} sdhc512x_t;

/*
 * SPDIF
 */
typedef struct spdif512x {
	u8 fixme[0x100];
} spdif512x_t;

/*
 * I2C
 */
typedef struct i2c512x_dev {
	volatile u32 madr;		/* I2Cn + 0x00 */
	volatile u32 mfdr;		/* I2Cn + 0x04 */
	volatile u32 mcr;		/* I2Cn + 0x08 */
	volatile u32 msr;		/* I2Cn + 0x0C */
	volatile u32 mdr;		/* I2Cn + 0x10 */
	u8 res0[0x0C];
} i2c512x_dev_t;

typedef struct i2c512x {
	i2c512x_dev_t dev[3];
	volatile u32 icr;
	volatile u32 mifr;
	u8 res0[0x98];
} i2c512x_t;

/*
 * AXE
 */
typedef struct axe512x {
	u8 fixme[0x100];
} axe512x_t;

/*
 * DIU
 */
typedef struct diu512x {
	u8 fixme[0x100];
} diu512x_t;

/*
 * CFM
 */
typedef struct cfm512x {
	u8 fixme[0x100];
} cfm512x_t;

/*
 * FEC
 */
typedef struct fec512x {
	u8 fixme[0x800];
} fec512x_t;

/*
 * ULPI
 */
typedef struct ulpi512x {
	u8 fixme[0x600];
} ulpi512x_t;

/*
 * UTMI
 */
typedef struct utmi512x {
	u8 fixme[0x3000];
} utmi512x_t;

/*
 * PCI DMA
 */
typedef struct pcidma512x {
	u8 fixme[0x300];
} pcidma512x_t;

/*
 * IO Control
 */
typedef struct ioctrl512x {
	u32 regs[0x400];
} ioctrl512x_t;

/*
 * IIM
 */
typedef struct iim512x {
	u8 fixme[0x1000];
} iim512x_t;

/*
 * LPC
 */
typedef struct lpc512x {
	u32	cs_cfg[8];	/* Chip Select N Configuration Registers
				   No dedicated entry for CS Boot as == CS0 */
	u32	cs_cr;		/* Chip Select Control Register */
	u32	cs_sr;		/* Chip Select Status Register */
	u32	cs_bcr;		/* Chip Select Burst Control Register */
	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
	u8	res0[0xcc];
	u32	sclpc_psr;	/* SCLPC Packet Size Register */
	u32	sclpc_sar;	/* SCLPC Start Address Register */
	u32	sclpc_cr;	/* SCLPC Control Register */
	u32	sclpc_er;	/* SCLPC Enable Register */
	u32	sclpc_nar;	/* SCLPC NextAddress Register */
	u32	sclpc_sr;	/* SCLPC Status Register */
	u32	sclpc_bdr;	/* SCLPC Bytes Done Register */
	u32	emb_scr;	/* EMB Share Counter Register */
	u32	emb_pcr;	/* EMB Pause Control Register */
	u8	res1[0x1c];
	u32	lpc_fdwr;	/* LPC RX/TX FIFO Data Word Register */
	u32	lpc_fsr;	/* LPC RX/TX FIFO Status Register */
	u32	lpc_cr;		/* LPC RX/TX FIFO Control Register */
	u32	lpc_ar;		/* LPC RX/TX FIFO Alarm Register */
	u8	res2[0xb0];
} lpc512x_t;

/*
 * PATA
 */
typedef struct pata512x {
	u8 fixme[0x100];
} pata512x_t;

/*
 * PSC
 */
typedef struct psc512x {
	volatile u8	mode;		/* PSC + 0x00 */
	volatile u8	res0[3];
	union {				/* PSC + 0x04 */
		volatile u16	status;
		volatile u16	clock_select;
	} sr_csr;
#define psc_status	sr_csr.status
#define psc_clock_select sr_csr.clock_select
	volatile u16	res1;
	volatile u8	command;	/* PSC + 0x08 */
	volatile u8	res2[3];
	union {				/* PSC + 0x0c */
		volatile u8	buffer_8;
		volatile u16	buffer_16;
		volatile u32	buffer_32;
	} buffer;
#define psc_buffer_8	buffer.buffer_8
#define psc_buffer_16	buffer.buffer_16
#define psc_buffer_32	buffer.buffer_32
	union {				/* PSC + 0x10 */
		volatile u8	ipcr;
		volatile u8	acr;
	} ipcr_acr;
#define psc_ipcr	ipcr_acr.ipcr
#define psc_acr		ipcr_acr.acr
	volatile u8	res3[3];
	union {				/* PSC + 0x14 */
		volatile u16	isr;
		volatile u16	imr;
	} isr_imr;
#define psc_isr		isr_imr.isr
#define psc_imr		isr_imr.imr
	volatile u16	res4;
	volatile u8	ctur;		/* PSC + 0x18 */
	volatile u8	res5[3];
	volatile u8	ctlr;		/* PSC + 0x1c */
	volatile u8	res6[3];
	volatile u32	ccr;		/* PSC + 0x20 */
	volatile u8	res7[12];
	volatile u8	ivr;		/* PSC + 0x30 */
	volatile u8	res8[3];
	volatile u8	ip;		/* PSC + 0x34 */
	volatile u8	res9[3];
	volatile u8	op1;		/* PSC + 0x38 */
	volatile u8	res10[3];
	volatile u8	op0;		/* PSC + 0x3c */
	volatile u8	res11[3];
	volatile u32	sicr;		/* PSC + 0x40 */
	volatile u8	res12[60];
	volatile u32	tfcmd;		/* PSC + 0x80 */
	volatile u32	tfalarm;	/* PSC + 0x84 */
	volatile u32	tfstat;		/* PSC + 0x88 */
	volatile u32	tfintstat;	/* PSC + 0x8C */
	volatile u32	tfintmask;	/* PSC + 0x90 */
	volatile u32	tfcount;	/* PSC + 0x94 */
	volatile u16	tfwptr;		/* PSC + 0x98 */
	volatile u16	tfrptr;		/* PSC + 0x9A */
	volatile u32	tfsize;		/* PSC + 0x9C */
	volatile u8	res13[28];
	union {				/* PSC + 0xBC */
		volatile u8	buffer_8;
		volatile u16	buffer_16;
		volatile u32	buffer_32;
	} tfdata_buffer;
#define tfdata_8	tfdata_buffer.buffer_8
#define tfdata_16	tfdata_buffer.buffer_16
#define tfdata_32	tfdata_buffer.buffer_32

	volatile u32	rfcmd;		/* PSC + 0xC0 */
	volatile u32	rfalarm;	/* PSC + 0xC4 */
	volatile u32	rfstat;		/* PSC + 0xC8 */
	volatile u32	rfintstat;	/* PSC + 0xCC */
	volatile u32	rfintmask;	/* PSC + 0xD0 */
	volatile u32	rfcount;	/* PSC + 0xD4 */
	volatile u16	rfwptr;		/* PSC + 0xD8 */
	volatile u16	rfrptr;		/* PSC + 0xDA */
	volatile u32	rfsize;		/* PSC + 0xDC */
	volatile u8	res18[28];
	union {				/* PSC + 0xFC */
		volatile u8	buffer_8;
		volatile u16	buffer_16;
		volatile u32	buffer_32;
	} rfdata_buffer;
#define rfdata_8	rfdata_buffer.buffer_8
#define rfdata_16	rfdata_buffer.buffer_16
#define rfdata_32	rfdata_buffer.buffer_32
} psc512x_t;

/*
 * FIFOC
 */
typedef struct fifoc512x {
	u32 fifoc_cmd;
	u32 fifoc_int;
	u32 fifoc_dma;
	u32 fifoc_axe;
	u32 fifoc_debug;
	u8 fixme[0xEC];
} fifoc512x_t;

/*
 * SATA
 */
typedef struct sata512x {
	u8 fixme[0x2000];
} sata512x_t;

typedef struct immap {
	sysconf512x_t		sysconf;	/* System configuration */
	u8			res0[0x700];
	wdt512x_t		wdt;		/* Watch Dog Timer (WDT) */
	rtclk512x_t		rtc;		/* Real Time Clock Module */
	gpt512x_t		gpt;		/* General Purpose Timer */
	ipic512x_t		ipic;		/* Integrated Programmable Interrupt Controller */
	arbiter512x_t		arbiter;	/* CSB Arbiter */
	reset512x_t		reset;		/* Reset Module */
	clk512x_t		clk;		/* Clock Module */
	pmc512x_t		pmc;		/* Power Management Control Module */
	gpio512x_t		gpio;		/* General purpose I/O module */
	u8			res1[0x100];
	mscan512x_t		mscan;		/* MSCAN */
	bdlc512x_t		bdlc;		/* BDLC */
	sdhc512x_t		sdhc;		/* SDHC */
	spdif512x_t		spdif;		/* SPDIF */
	i2c512x_t		i2c;		/* I2C Controllers */
	u8			res2[0x800];
	axe512x_t		axe;		/* AXE */
	diu512x_t		diu;		/* Display Interface Unit */
	cfm512x_t		cfm;		/* Clock Frequency Measurement */
	u8			res3[0x500];
	fec512x_t		fec;		/* Fast Ethernet Controller */
	ulpi512x_t		ulpi;		/* USB ULPI */
	u8			res4[0xa00];
	utmi512x_t		utmi;		/* USB UTMI */
	u8			res5[0x1000];
	pcidma512x_t		pci_dma;	/* PCI DMA */
	pciconf512x_t		pci_conf;	/* PCI Configuration */
	u8			res6[0x80];
	ios512x_t		ios;		/* PCI Sequencer */
	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
	u8			res7[0xa00];
	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
	ioctrl512x_t		io_ctrl;	/* IO Control */
	iim512x_t		iim;		/* IC Identification module */
	u8			res8[0x4000];
	lpc512x_t		lpc;		/* LocalPlus Controller */
	pata512x_t		pata;		/* Parallel ATA */
	u8			res9[0xd00];
	psc512x_t		psc[12];	/* PSCs */
	u8			res10[0x300];
	fifoc512x_t		fifoc;		/* FIFO Controller */
	u8			res11[0x2000];
	dma512x_t		dma;		/* DMA */
	u8			res12[0xa800];
	sata512x_t		sata;		/* Serial ATA */
	u8			res13[0xde000];
} immap_t;
#endif /* __IMMAP_512x__ */
Commit	Line	Data
8993e54b RJ	1	/*
	2	* (C) Copyright 2007 DENX Software Engineering
	3	*
	4	* MPC512x Internal Memory Map
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*
	21	* Based on the MPC83xx header.
	22	*/
	23
	24	#ifndef __IMMAP_512x__
	25	#define __IMMAP_512x__
	26
	27	#include <asm/types.h>
	28
	29	typedef struct law512x {
	30	u32 bar; /* Base Addr Register */
	31	u32 ar; /* Attributes Register */
5f91db7f	32	} law512x_t;
8993e54b RJ	33
	34	/*
	35	* System configuration registers
	36	*/
	37	typedef struct sysconf512x {
	38	u32 immrbar; /* Internal memory map base address register */
	39	u8 res0[0x1c];
	40	u32 lpbaw; /* LP Boot Access Window */
	41	u32 lpcs0aw; /* LP CS0 Access Window */
	42	u32 lpcs1aw; /* LP CS1 Access Window */
	43	u32 lpcs2aw; /* LP CS2 Access Window */
	44	u32 lpcs3aw; /* LP CS3 Access Window */
	45	u32 lpcs4aw; /* LP CS4 Access Window */
	46	u32 lpcs5aw; /* LP CS5 Access Window */
	47	u32 lpcs6aw; /* LP CS6 Access Window */
	48	u32 lpcs7aw; /* LP CS7 Access Window */
	49	u8 res1[0x1c];
5f91db7f	50	law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
8993e54b	51	u8 res2[0x28];
5f91db7f	52	law512x_t ddrlaw; /* DDR Local Access Window */
8993e54b RJ	53	u8 res3[0x18];
	54	u32 mbxbar; /* MBX Base Address */
	55	u32 srambar; /* SRAM Base Address */
	56	u32 nfcbar; /* NFC Base Address */
	57	u8 res4[0x34];
	58	u32 spridr; /* System Part and Revision ID Register */
	59	u32 spcr; /* System Priority Configuration Register */
	60	u8 res5[0xf8];
	61	} sysconf512x_t;
	62
	63	/*
	64	* Watch Dog Timer (WDT) Registers
	65	*/
	66	typedef struct wdt512x {
	67	u8 res0[4];
	68	u32 swcrr; /* System watchdog control register */
	69	u32 swcnr; /* System watchdog count register */
	70	u8 res1[2];
	71	u16 swsrr; /* System watchdog service register */
	72	u8 res2[0xF0];
	73	} wdt512x_t;
	74
	75	/*
	76	* RTC Module Registers
	77	*/
	78	typedef struct rtclk512x {
	79	u8 fixme[0x100];
	80	} rtclk512x_t;
	81
	82	/*
	83	* General Purpose Timer
	84	*/
	85	typedef struct gpt512x {
	86	u8 fixme[0x100];
	87	} gpt512x_t;
	88
	89	/*
	90	* Integrated Programmable Interrupt Controller
	91	*/
	92	typedef struct ipic512x {
	93	u8 fixme[0x100];
	94	} ipic512x_t;
	95
	96	/*
	97	* System Arbiter Registers
	98	*/
	99	typedef struct arbiter512x {
	100	u32 acr; /* Arbiter Configuration Register */
	101	u32 atr; /* Arbiter Timers Register */
	102	u32 ater; /* Arbiter Transfer Error Register */
	103	u32 aer; /* Arbiter Event Register */
	104	u32 aidr; /* Arbiter Interrupt Definition Register */
	105	u32 amr; /* Arbiter Mask Register */
	106	u32 aeatr; /* Arbiter Event Attributes Register */
	107	u32 aeadr; /* Arbiter Event Address Register */
	108	u32 aerr; /* Arbiter Event Response Register */
	109	u8 res1[0xDC];
	110	} arbiter512x_t;
	111
	112	/*
	113	* Reset Module
	114	*/
	115	typedef struct reset512x {
	116	u32 rcwl; /* Reset Configuration Word Low Register */
117	u32 rcwh; /* Reset Configuration Word High Register */
118	u8 res0[8];
119	u32 rsr; /* Reset Status Register */
120	u32 rmr; /* Reset Mode Register */
121	u32 rpr; /* Reset protection Register */
122	u32 rcr; /* Reset Control Register */
123	u32 rcer; /* Reset Control Enable Register */
124	u8 res1[0xDC];
125	} reset512x_t;
126
127	/*
128	* Clock Module
129	*/
130	typedef struct clk512x {
131	u32 spmr; /* System PLL Mode Register */
132	u32 sccr[2]; /* System Clock Control Registers */
133	u32 scfr[2]; /* System Clock Frequency Registers */
134	u8 res0[4];
135	u32 bcr; /* Bread Crumb Register */
136	u32 pscccr[12]; /* PSC0-11 Clock Control Registers */
137	u32 spccr; /* SPDIF Clock Control Registers */
138	u32 cccr; /* CFM Clock Control Registers */
139	u32 dccr; /* DIU Clock Control Registers */
140	u8 res1[0xa8];
141	} clk512x_t;
142
143	/*
144	* Power Management Control Module
145	*/
146	typedef struct pmc512x {
147	u8 fixme[0x100];
148	} pmc512x_t;
149
150	/*
151	* General purpose I/O module
152	*/
153	typedef struct gpio512x {
154	u8 fixme[0x100];
155	} gpio512x_t;
156
157	/*
158	* DDR Memory Controller Memory Map
159	*/
160	typedef struct ddr512x {
161	u32 ddr_sys_config; /* System Configuration Register */
162	u32 ddr_time_config0; /* Timing Configuration Register */
163	u32 ddr_time_config1; /* Timing Configuration Register */
164	u32 ddr_time_config2; /* Timing Configuration Register */
165	u32 ddr_command; /* Command Register */
166	u32 ddr_compact_command; /* Compact Command Register */
167	u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */
168	u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */
169	u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */
170	u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */
171	u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */
172	u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
173	u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
174	u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
175	u32 DQS_config_offset_count; /* DQS Config Offset Count */
176	u32 DQS_config_offset_time; /* DQS Config Offset Time */
177	u32 DQS_delay_status; /* DQS Delay Status */
178	u32 res0[0xF];
179	u32 prioman_config1; /* Priority Manager Configuration */
180	u32 prioman_config2; /* Priority Manager Configuration */
181	u32 hiprio_config; /* High Priority Configuration */
182	u32 lut_table0_main_upper; /* LUT0 Main Upper */
183	u32 lut_table1_main_upper; /* LUT1 Main Upper */
184	u32 lut_table2_main_upper; /* LUT2 Main Upper */
185	u32 lut_table3_main_upper; /* LUT3 Main Upper */
186	u32 lut_table4_main_upper; /* LUT4 Main Upper */
187	u32 lut_table0_main_lower; /* LUT0 Main Lower */
188	u32 lut_table1_main_lower; /* LUT1 Main Lower */
189	u32 lut_table2_main_lower; /* LUT2 Main Lower */
190	u32 lut_table3_main_lower; /* LUT3 Main Lower */
191	u32 lut_table4_main_lower; /* LUT4 Main Lower */
192	u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */
193	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
194	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
195	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
196	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
197	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
198	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
199	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
200	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
201	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
202	u32 performance_monitor_config;
203	u32 event_time_counter;
204	u32 event_time_preset;
205	u32 performance_monitor1_address_low;
206	u32 performance_monitor2_address_low;
207	u32 performance_monitor1_address_hi;
208	u32 performance_monitor2_address_hi;
209	u32 res1[2];
210	u32 performance_monitor1_read_counter;
211	u32 performance_monitor2_read_counter;
212	u32 performance_monitor1_write_counter;
213	u32 performance_monitor2_write_counter;
214	u32 granted_ack_counter0;
215	u32 granted_ack_counter1;
216	u32 granted_ack_counter2;
217	u32 granted_ack_counter3;
218	u32 granted_ack_counter4;
219	u32 cumulative_wait_counter0;
220	u32 cumulative_wait_counter1;
221	u32 cumulative_wait_counter2;
222	u32 cumulative_wait_counter3;
223	u32 cumulative_wait_counter4;
224	u32 summed_priority_counter0;
225	u32 summed_priority_counter1;
226	u32 summed_priority_counter2;
227	u32 summed_priority_counter3;
228	u32 summed_priority_counter4;
229	u32 res2[0x3AD];
230	} ddr512x_t;
231
232
233	/*
234	* DMA/Messaging Unit
235	*/
236	typedef struct dma512x {
237	u8 fixme[0x1800];
238	} dma512x_t;
239
240	/*
241	* PCI Software Configuration Registers
242	*/
243	typedef struct pciconf512x {
5f91db7f JR	244	u32 config_address;
	245	u32 config_data;
	246	u32 int_ack;
	247	u8 res[116];
8993e54b RJ	248	} pciconf512x_t;
8993e54b RJ	249
5f91db7f JR	250	/*
	251	* PCI Outbound Translation Register
	252	*/
	253	typedef struct pci_outbound_window {
	254	u32 potar;
	255	u8 res0[4];
	256	u32 pobar;
	257	u8 res1[4];
	258	u32 pocmr;
	259	u8 res2[4];
	260	} pot512x_t;
	261
8993e54b RJ	262	/*
	263	* Sequencer
	264	*/
	265	typedef struct ios512x {
5f91db7f JR	266	pot512x_t pot[6];
	267	u8 res0[0x60];
	268	u32 pmcr;
	269	u8 res1[4];
	270	u32 dtcr;
	271	u8 res2[4];
8993e54b RJ	272	} ios512x_t;
	273
	274	/*
	275	* PCI Controller
	276	*/
	277	typedef struct pcictrl512x {
5f91db7f JR	278	u32 esr;
	279	u32 ecdr;
	280	u32 eer;
	281	u32 eatcr;
	282	u32 eacr;
	283	u32 eeacr;
	284	u32 edlcr;
	285	u32 edhcr;
	286	u32 gcr;
	287	u32 ecr;
	288	u32 gsr;
	289	u8 res0[12];
	290	u32 pitar2;
	291	u8 res1[4];
	292	u32 pibar2;
	293	u32 piebar2;
	294	u32 piwar2;
	295	u8 res2[4];
	296	u32 pitar1;
	297	u8 res3[4];
	298	u32 pibar1;
	299	u32 piebar1;
	300	u32 piwar1;
	301	u8 res4[4];
	302	u32 pitar0;
	303	u8 res5[4];
	304	u32 pibar0;
	305	u8 res6[4];
	306	u32 piwar0;
	307	u8 res7[132];
8993e54b RJ	308	} pcictrl512x_t;
	309
	310
	311	/*
	312	* MSCAN
	313	*/
	314	typedef struct mscan512x {
	315	u8 fixme[0x100];
	316	} mscan512x_t;
	317
	318	/*
	319	* BDLC
	320	*/
	321	typedef struct bdlc512x {
	322	u8 fixme[0x100];
	323	} bdlc512x_t;
	324
	325	/*
	326	* SDHC
	327	*/
	328	typedef struct sdhc512x {
	329	u8 fixme[0x100];
	330	} sdhc512x_t;
	331
	332	/*
	333	* SPDIF
	334	*/
	335	typedef struct spdif512x {
	336	u8 fixme[0x100];
	337	} spdif512x_t;
	338
	339	/*
	340	* I2C
	341	*/
	342	typedef struct i2c512x_dev {
	343	volatile u32 madr; /* I2Cn + 0x00 */
	344	volatile u32 mfdr; /* I2Cn + 0x04 */
	345	volatile u32 mcr; /* I2Cn + 0x08 */
	346	volatile u32 msr; /* I2Cn + 0x0C */
	347	volatile u32 mdr; /* I2Cn + 0x10 */
	348	u8 res0[0x0C];
	349	} i2c512x_dev_t;
	350
	351	typedef struct i2c512x {
	352	i2c512x_dev_t dev[3];
	353	volatile u32 icr;
	354	volatile u32 mifr;
	355	u8 res0[0x98];
	356	} i2c512x_t;
	357
	358	/*
	359	* AXE
	360	*/
	361	typedef struct axe512x {
	362	u8 fixme[0x100];
	363	} axe512x_t;
	364
	365	/*
	366	* DIU
	367	*/
	368	typedef struct diu512x {
	369	u8 fixme[0x100];
	370	} diu512x_t;
	371
372	/*
373	* CFM
374	*/
375	typedef struct cfm512x {
376	u8 fixme[0x100];
377	} cfm512x_t;
378
379	/*
380	* FEC
381	*/
382	typedef struct fec512x {
383	u8 fixme[0x800];
384	} fec512x_t;
385
386	/*
387	* ULPI
388	*/
389	typedef struct ulpi512x {
390	u8 fixme[0x600];
391	} ulpi512x_t;
392
393	/*
394	* UTMI
395	*/
396	typedef struct utmi512x {
397	u8 fixme[0x3000];
398	} utmi512x_t;
399
400	/*
401	* PCI DMA
402	*/
403	typedef struct pcidma512x {
404	u8 fixme[0x300];
405	} pcidma512x_t;
406
407	/*
408	* IO Control
409	*/
410	typedef struct ioctrl512x {
411	u32 regs[0x400];
412	} ioctrl512x_t;
413
414	/*
415	* IIM
416	*/
417	typedef struct iim512x {
418	u8 fixme[0x1000];
419	} iim512x_t;
420
421	/*
422	* LPC
423	*/
424	typedef struct lpc512x {
425	u32 cs_cfg[8]; /* Chip Select N Configuration Registers
426	No dedicated entry for CS Boot as == CS0 */
427	u32 cs_cr; /* Chip Select Control Register */
428	u32 cs_sr; /* Chip Select Status Register */
429	u32 cs_bcr; /* Chip Select Burst Control Register */
430	u32 cs_dccr; /* Chip Select Deadcycle Control Register */
431	u32 cs_hccr; /* Chip Select Holdcycle Control Register */
432	u8 res0[0xcc];
433	u32 sclpc_psr; /* SCLPC Packet Size Register */
434	u32 sclpc_sar; /* SCLPC Start Address Register */
435	u32 sclpc_cr; /* SCLPC Control Register */
436	u32 sclpc_er; /* SCLPC Enable Register */
437	u32 sclpc_nar; /* SCLPC NextAddress Register */
438	u32 sclpc_sr; /* SCLPC Status Register */
439	u32 sclpc_bdr; /* SCLPC Bytes Done Register */
440	u32 emb_scr; /* EMB Share Counter Register */
441	u32 emb_pcr; /* EMB Pause Control Register */
442	u8 res1[0x1c];
443	u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */
444	u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */
445	u32 lpc_cr; /* LPC RX/TX FIFO Control Register */
446	u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */
447	u8 res2[0xb0];
448	} lpc512x_t;
449
450	/*
451	* PATA
452	*/
453	typedef struct pata512x {
454	u8 fixme[0x100];
455	} pata512x_t;
456
457	/*
458	* PSC
459	*/
460	typedef struct psc512x {
461	volatile u8 mode; /* PSC + 0x00 */
462	volatile u8 res0[3];
463	union { /* PSC + 0x04 */
464	volatile u16 status;
465	volatile u16 clock_select;
466	} sr_csr;
467	#define psc_status sr_csr.status
468	#define psc_clock_select sr_csr.clock_select
469	volatile u16 res1;
470	volatile u8 command; /* PSC + 0x08 */
471	volatile u8 res2[3];
472	union { /* PSC + 0x0c */
473	volatile u8 buffer_8;
474	volatile u16 buffer_16;
475	volatile u32 buffer_32;
476	} buffer;
477	#define psc_buffer_8 buffer.buffer_8
478	#define psc_buffer_16 buffer.buffer_16
479	#define psc_buffer_32 buffer.buffer_32
480	union { /* PSC + 0x10 */
481	volatile u8 ipcr;
482	volatile u8 acr;
483	} ipcr_acr;
484	#define psc_ipcr ipcr_acr.ipcr
485	#define psc_acr ipcr_acr.acr
486	volatile u8 res3[3];
487	union { /* PSC + 0x14 */
488	volatile u16 isr;
489	volatile u16 imr;
490	} isr_imr;
491	#define psc_isr isr_imr.isr
492	#define psc_imr isr_imr.imr
493	volatile u16 res4;
494	volatile u8 ctur; /* PSC + 0x18 */
495	volatile u8 res5[3];
496	volatile u8 ctlr; /* PSC + 0x1c */
497	volatile u8 res6[3];
498	volatile u32 ccr; /* PSC + 0x20 */
499	volatile u8 res7[12];
500	volatile u8 ivr; /* PSC + 0x30 */
501	volatile u8 res8[3];
502	volatile u8 ip; /* PSC + 0x34 */
503	volatile u8 res9[3];
504	volatile u8 op1; /* PSC + 0x38 */
505	volatile u8 res10[3];
506	volatile u8 op0; /* PSC + 0x3c */
507	volatile u8 res11[3];
508	volatile u32 sicr; /* PSC + 0x40 */
509	volatile u8 res12[60];
510	volatile u32 tfcmd; /* PSC + 0x80 */
511	volatile u32 tfalarm; /* PSC + 0x84 */
512	volatile u32 tfstat; /* PSC + 0x88 */
513	volatile u32 tfintstat; /* PSC + 0x8C */
514	volatile u32 tfintmask; /* PSC + 0x90 */
515	volatile u32 tfcount; /* PSC + 0x94 */
516	volatile u16 tfwptr; /* PSC + 0x98 */
517	volatile u16 tfrptr; /* PSC + 0x9A */
518	volatile u32 tfsize; /* PSC + 0x9C */
519	volatile u8 res13[28];
520	union { /* PSC + 0xBC */
521	volatile u8 buffer_8;
522	volatile u16 buffer_16;
523	volatile u32 buffer_32;
524	} tfdata_buffer;
525	#define tfdata_8 tfdata_buffer.buffer_8
526	#define tfdata_16 tfdata_buffer.buffer_16
527	#define tfdata_32 tfdata_buffer.buffer_32
528
529	volatile u32 rfcmd; /* PSC + 0xC0 */
530	volatile u32 rfalarm; /* PSC + 0xC4 */
531	volatile u32 rfstat; /* PSC + 0xC8 */
532	volatile u32 rfintstat; /* PSC + 0xCC */
533	volatile u32 rfintmask; /* PSC + 0xD0 */
534	volatile u32 rfcount; /* PSC + 0xD4 */
535	volatile u16 rfwptr; /* PSC + 0xD8 */
536	volatile u16 rfrptr; /* PSC + 0xDA */
537	volatile u32 rfsize; /* PSC + 0xDC */
538	volatile u8 res18[28];
539	union { /* PSC + 0xFC */
540	volatile u8 buffer_8;
541	volatile u16 buffer_16;
542	volatile u32 buffer_32;
543	} rfdata_buffer;
544	#define rfdata_8 rfdata_buffer.buffer_8
545	#define rfdata_16 rfdata_buffer.buffer_16
546	#define rfdata_32 rfdata_buffer.buffer_32
547	} psc512x_t;
548
549	/*
550	* FIFOC
551	*/
552	typedef struct fifoc512x {
553	u32 fifoc_cmd;
554	u32 fifoc_int;
555	u32 fifoc_dma;
556	u32 fifoc_axe;
557	u32 fifoc_debug;
558	u8 fixme[0xEC];
559	} fifoc512x_t;
560
561	/*
562	* SATA
563	*/
564	typedef struct sata512x {
565	u8 fixme[0x2000];
566	} sata512x_t;
567
568	typedef struct immap {
569	sysconf512x_t sysconf; /* System configuration */
570	u8 res0[0x700];
571	wdt512x_t wdt; /* Watch Dog Timer (WDT) */
572	rtclk512x_t rtc; /* Real Time Clock Module */
573	gpt512x_t gpt; /* General Purpose Timer */
574	ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */
575	arbiter512x_t arbiter; /* CSB Arbiter */
576	reset512x_t reset; /* Reset Module */
577	clk512x_t clk; /* Clock Module */
578	pmc512x_t pmc; /* Power Management Control Module */
579	gpio512x_t gpio; /* General purpose I/O module */
580	u8 res1[0x100];
581	mscan512x_t mscan; /* MSCAN */
582	bdlc512x_t bdlc; /* BDLC */
583	sdhc512x_t sdhc; /* SDHC */
584	spdif512x_t spdif; /* SPDIF */
585	i2c512x_t i2c; /* I2C Controllers */
586	u8 res2[0x800];
587	axe512x_t axe; /* AXE */
588	diu512x_t diu; /* Display Interface Unit */
589	cfm512x_t cfm; /* Clock Frequency Measurement */
590	u8 res3[0x500];
591	fec512x_t fec; /* Fast Ethernet Controller */
592	ulpi512x_t ulpi; /* USB ULPI */
593	u8 res4[0xa00];
594	utmi512x_t utmi; /* USB UTMI */
595	u8 res5[0x1000];
596	pcidma512x_t pci_dma; /* PCI DMA */
597	pciconf512x_t pci_conf; /* PCI Configuration */
598	u8 res6[0x80];
599	ios512x_t ios; /* PCI Sequencer */
600	pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */
601	u8 res7[0xa00];
602	ddr512x_t mddrc; /* Multi-port DDR Memory Controller */
603	ioctrl512x_t io_ctrl; /* IO Control */
604	iim512x_t iim; /* IC Identification module */
605	u8 res8[0x4000];
606	lpc512x_t lpc; /* LocalPlus Controller */
607	pata512x_t pata; /* Parallel ATA */
608	u8 res9[0xd00];
609	psc512x_t psc[12]; /* PSCs */
610	u8 res10[0x300];
611	fifoc512x_t fifoc; /* FIFO Controller */
612	u8 res11[0x2000];
613	dma512x_t dma; /* DMA */
614	u8 res12[0xa800];
615	sata512x_t sata; /* Serial ATA */
616	u8 res13[0xde000];
617	} immap_t;
618	#endif /* __IMMAP_512x__ */