[J-u-boot.git] / drivers / spi / tegra114_spi.c

/*
 * NVIDIA Tegra SPI controller (T114 and later)
 *
 * Copyright (c) 2010-2013 NVIDIA Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#include <spi.h>
#include <fdtdec.h>
#include "tegra_spi.h"

DECLARE_GLOBAL_DATA_PTR;

/* COMMAND1 */
#define SPI_CMD1_GO			BIT(31)
#define SPI_CMD1_M_S			BIT(30)
#define SPI_CMD1_MODE_MASK		GENMASK(1, 0)
#define SPI_CMD1_MODE_SHIFT		28
#define SPI_CMD1_CS_SEL_MASK		GENMASK(1, 0)
#define SPI_CMD1_CS_SEL_SHIFT		26
#define SPI_CMD1_CS_POL_INACTIVE3	BIT(25)
#define SPI_CMD1_CS_POL_INACTIVE2	BIT(24)
#define SPI_CMD1_CS_POL_INACTIVE1	BIT(23)
#define SPI_CMD1_CS_POL_INACTIVE0	BIT(22)
#define SPI_CMD1_CS_SW_HW		BIT(21)
#define SPI_CMD1_CS_SW_VAL		BIT(20)
#define SPI_CMD1_IDLE_SDA_MASK		GENMASK(1, 0)
#define SPI_CMD1_IDLE_SDA_SHIFT		18
#define SPI_CMD1_BIDIR			BIT(17)
#define SPI_CMD1_LSBI_FE		BIT(16)
#define SPI_CMD1_LSBY_FE		BIT(15)
#define SPI_CMD1_BOTH_EN_BIT		BIT(14)
#define SPI_CMD1_BOTH_EN_BYTE		BIT(13)
#define SPI_CMD1_RX_EN			BIT(12)
#define SPI_CMD1_TX_EN			BIT(11)
#define SPI_CMD1_PACKED			BIT(5)
#define SPI_CMD1_BIT_LEN_MASK		GENMASK(4, 0)
#define SPI_CMD1_BIT_LEN_SHIFT		0

/* COMMAND2 */
#define SPI_CMD2_TX_CLK_TAP_DELAY	BIT(6)
#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	GENMASK(11, 6)
#define SPI_CMD2_RX_CLK_TAP_DELAY	BIT(0)
#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	GENMASK(5, 0)

/* TRANSFER STATUS */
#define SPI_XFER_STS_RDY		BIT(30)

/* FIFO STATUS */
#define SPI_FIFO_STS_CS_INACTIVE	BIT(31)
#define SPI_FIFO_STS_FRAME_END		BIT(30)
#define SPI_FIFO_STS_RX_FIFO_FLUSH	BIT(15)
#define SPI_FIFO_STS_TX_FIFO_FLUSH	BIT(14)
#define SPI_FIFO_STS_ERR		BIT(8)
#define SPI_FIFO_STS_TX_FIFO_OVF	BIT(7)
#define SPI_FIFO_STS_TX_FIFO_UNR	BIT(6)
#define SPI_FIFO_STS_RX_FIFO_OVF	BIT(5)
#define SPI_FIFO_STS_RX_FIFO_UNR	BIT(4)
#define SPI_FIFO_STS_TX_FIFO_FULL	BIT(3)
#define SPI_FIFO_STS_TX_FIFO_EMPTY	BIT(2)
#define SPI_FIFO_STS_RX_FIFO_FULL	BIT(1)
#define SPI_FIFO_STS_RX_FIFO_EMPTY	BIT(0)

#define SPI_TIMEOUT		1000
#define TEGRA_SPI_MAX_FREQ	52000000

struct spi_regs {
	u32 command1;	/* 000:SPI_COMMAND1 register */
	u32 command2;	/* 004:SPI_COMMAND2 register */
	u32 timing1;	/* 008:SPI_CS_TIM1 register */
	u32 timing2;	/* 00c:SPI_CS_TIM2 register */
	u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
	u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
	u32 tx_data;	/* 018:SPI_TX_DATA register */
	u32 rx_data;	/* 01c:SPI_RX_DATA register */
	u32 dma_ctl;	/* 020:SPI_DMA_CTL register */
	u32 dma_blk;	/* 024:SPI_DMA_BLK register */
	u32 rsvd[56];	/* 028-107 reserved */
	u32 tx_fifo;	/* 108:SPI_FIFO1 register */
	u32 rsvd2[31];	/* 10c-187 reserved */
	u32 rx_fifo;	/* 188:SPI_FIFO2 register */
	u32 spare_ctl;	/* 18c:SPI_SPARE_CTRL register */
};

struct tegra114_spi_priv {
	struct spi_regs *regs;
	unsigned int freq;
	unsigned int mode;
	int periph_id;
	int valid;
	int last_transaction_us;
};

static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
{
	struct tegra_spi_platdata *plat = bus->platdata;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	plat->base = devfdt_get_addr(bus);
	plat->periph_id = clock_decode_periph_id(blob, node);

	if (plat->periph_id == PERIPH_ID_NONE) {
		debug("%s: could not decode periph id %d\n", __func__,
		      plat->periph_id);
		return -FDT_ERR_NOTFOUND;
	}

	/* Use 500KHz as a suitable default */
	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
					500000);
	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, plat->base, plat->periph_id, plat->frequency,
	      plat->deactivate_delay_us);

	return 0;
}

static int tegra114_spi_probe(struct udevice *bus)
{
	struct tegra_spi_platdata *plat = dev_get_platdata(bus);
	struct tegra114_spi_priv *priv = dev_get_priv(bus);
	struct spi_regs *regs;
	ulong rate;

	priv->regs = (struct spi_regs *)plat->base;
	regs = priv->regs;

	priv->last_transaction_us = timer_get_us();
	priv->freq = plat->frequency;
	priv->periph_id = plat->periph_id;

	/*
	 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
	 * back to the oscillator if that is too fast.
	 */
	rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
				      priv->freq);
	if (rate > priv->freq + 100000) {
		rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
					      priv->freq);
		if (rate != priv->freq) {
			printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
			       bus->name, priv->freq, rate);
		}
	}
	udelay(plat->deactivate_delay_us);

	/* Clear stale status here */
	setbits_le32(&regs->fifo_status,
		     SPI_FIFO_STS_ERR		|
		     SPI_FIFO_STS_TX_FIFO_OVF	|
		     SPI_FIFO_STS_TX_FIFO_UNR	|
		     SPI_FIFO_STS_RX_FIFO_OVF	|
		     SPI_FIFO_STS_RX_FIFO_UNR	|
		     SPI_FIFO_STS_TX_FIFO_FULL	|
		     SPI_FIFO_STS_TX_FIFO_EMPTY	|
		     SPI_FIFO_STS_RX_FIFO_FULL	|
		     SPI_FIFO_STS_RX_FIFO_EMPTY);
	debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));

	setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
		     (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
	debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));

	return 0;
}

/**
 * Activate the CS by driving it LOW
 *
 * @param slave	Pointer to spi_slave to which controller has to
 *		communicate with
 */
static void spi_cs_activate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
	struct tegra114_spi_priv *priv = dev_get_priv(bus);

	/* If it's too soon to do another transaction, wait */
	if (pdata->deactivate_delay_us &&
	    priv->last_transaction_us) {
		ulong delay_us;		/* The delay completed so far */
		delay_us = timer_get_us() - priv->last_transaction_us;
		if (delay_us < pdata->deactivate_delay_us)
			udelay(pdata->deactivate_delay_us - delay_us);
	}

	clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
}

/**
 * Deactivate the CS by driving it HIGH
 *
 * @param slave	Pointer to spi_slave to which controller has to
 *		communicate with
 */
static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
	struct tegra114_spi_priv *priv = dev_get_priv(bus);

	setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);

	/* Remember time of this transaction so we can honour the bus delay */
	if (pdata->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();

	debug("Deactivate CS, bus '%s'\n", bus->name);
}

static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
			     const void *data_out, void *data_in,
			     unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct tegra114_spi_priv *priv = dev_get_priv(bus);
	struct spi_regs *regs = priv->regs;
	u32 reg, tmpdout, tmpdin = 0;
	const u8 *dout = data_out;
	u8 *din = data_in;
	int num_bytes;
	int ret;

	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
	      __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
	if (bitlen % 8)
		return -1;
	num_bytes = bitlen / 8;

	ret = 0;

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev);

	/* clear all error status bits */
	reg = readl(&regs->fifo_status);
	writel(reg, &regs->fifo_status);

	clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
			SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
			(spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));

	/* set xfer size to 1 block (32 bits) */
	writel(0, &regs->dma_blk);

	/* handle data in 32-bit chunks */
	while (num_bytes > 0) {
		int bytes;
		int tm, i;

		tmpdout = 0;
		bytes = (num_bytes > 4) ?  4 : num_bytes;

		if (dout != NULL) {
			for (i = 0; i < bytes; ++i)
				tmpdout = (tmpdout << 8) | dout[i];
			dout += bytes;
		}

		num_bytes -= bytes;

		/* clear ready bit */
		setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);

		clrsetbits_le32(&regs->command1,
				SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
				(bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
		writel(tmpdout, &regs->tx_fifo);
		setbits_le32(&regs->command1, SPI_CMD1_GO);

		/*
		 * Wait for SPI transmit FIFO to empty, or to time out.
		 * The RX FIFO status will be read and cleared last
		 */
		for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
			u32 fifo_status, xfer_status;

			xfer_status = readl(&regs->xfer_status);
			if (!(xfer_status & SPI_XFER_STS_RDY))
				continue;

			fifo_status = readl(&regs->fifo_status);
			if (fifo_status & SPI_FIFO_STS_ERR) {
				debug("%s: got a fifo error: ", __func__);
				if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
					debug("tx FIFO overflow ");
				if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
					debug("tx FIFO underrun ");
				if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
					debug("rx FIFO overflow ");
				if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
					debug("rx FIFO underrun ");
				if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
					debug("tx FIFO full ");
				if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
					debug("tx FIFO empty ");
				if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
					debug("rx FIFO full ");
				if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
					debug("rx FIFO empty ");
				debug("\n");
				break;
			}

			if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
				tmpdin = readl(&regs->rx_fifo);

				/* swap bytes read in */
				if (din != NULL) {
					for (i = bytes - 1; i >= 0; --i) {
						din[i] = tmpdin & 0xff;
						tmpdin >>= 8;
					}
					din += bytes;
				}

				/* We can exit when we've had both RX and TX */
				break;
			}
		}

		if (tm >= SPI_TIMEOUT)
			ret = tm;

		/* clear ACK RDY, etc. bits */
		writel(readl(&regs->fifo_status), &regs->fifo_status);
	}

	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev);

	debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
	      __func__, tmpdin, readl(&regs->fifo_status));

	if (ret) {
		printf("%s: timeout during SPI transfer, tm %d\n",
		       __func__, ret);
		return -1;
	}

	return ret;
}

static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
{
	struct tegra_spi_platdata *plat = bus->platdata;
	struct tegra114_spi_priv *priv = dev_get_priv(bus);

	if (speed > plat->frequency)
		speed = plat->frequency;
	priv->freq = speed;
	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);

	return 0;
}

static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
{
	struct tegra114_spi_priv *priv = dev_get_priv(bus);

	priv->mode = mode;
	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops tegra114_spi_ops = {
	.xfer		= tegra114_spi_xfer,
	.set_speed	= tegra114_spi_set_speed,
	.set_mode	= tegra114_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id tegra114_spi_ids[] = {
	{ .compatible = "nvidia,tegra114-spi" },
	{ }
};

U_BOOT_DRIVER(tegra114_spi) = {
	.name	= "tegra114_spi",
	.id	= UCLASS_SPI,
	.of_match = tegra114_spi_ids,
	.ops	= &tegra114_spi_ops,
	.ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
	.probe	= tegra114_spi_probe,
};
Commit	Line	Data
77c42e80 AM	1	/*
	2	* NVIDIA Tegra SPI controller (T114 and later)
	3	*
	4	* Copyright (c) 2010-2013 NVIDIA Corporation
	5	*
5b8031cc	6	* SPDX-License-Identifier: GPL-2.0
77c42e80 AM	7	*/
	8
	9	#include <common.h>
fda6fac3	10	#include <dm.h>
77c42e80	11	#include <asm/io.h>
77c42e80 AM	12	#include <asm/arch/clock.h>
77c42e80 AM	13	#include <asm/arch-tegra/clk_rst.h>
77c42e80 AM	14	#include <spi.h>
77c42e80 AM	15	#include <fdtdec.h>
fda6fac3	16	#include "tegra_spi.h"
77c42e80 AM	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
	20	/* COMMAND1 */
f692248f JT	21	#define SPI_CMD1_GO BIT(31)
f692248f JT	22	#define SPI_CMD1_M_S BIT(30)
76538ec6	23	#define SPI_CMD1_MODE_MASK GENMASK(1, 0)
77c42e80	24	#define SPI_CMD1_MODE_SHIFT 28
76538ec6	25	#define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
77c42e80	26	#define SPI_CMD1_CS_SEL_SHIFT 26
f692248f JT	27	#define SPI_CMD1_CS_POL_INACTIVE3 BIT(25)
	28	#define SPI_CMD1_CS_POL_INACTIVE2 BIT(24)
	29	#define SPI_CMD1_CS_POL_INACTIVE1 BIT(23)
	30	#define SPI_CMD1_CS_POL_INACTIVE0 BIT(22)
	31	#define SPI_CMD1_CS_SW_HW BIT(21)
	32	#define SPI_CMD1_CS_SW_VAL BIT(20)
76538ec6	33	#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
77c42e80	34	#define SPI_CMD1_IDLE_SDA_SHIFT 18
f692248f JT	35	#define SPI_CMD1_BIDIR BIT(17)
	36	#define SPI_CMD1_LSBI_FE BIT(16)
	37	#define SPI_CMD1_LSBY_FE BIT(15)
	38	#define SPI_CMD1_BOTH_EN_BIT BIT(14)
	39	#define SPI_CMD1_BOTH_EN_BYTE BIT(13)
	40	#define SPI_CMD1_RX_EN BIT(12)
	41	#define SPI_CMD1_TX_EN BIT(11)
	42	#define SPI_CMD1_PACKED BIT(5)
76538ec6	43	#define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
77c42e80 AM	44	#define SPI_CMD1_BIT_LEN_SHIFT 0
	45
	46	/* COMMAND2 */
f692248f	47	#define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
76538ec6	48	#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
f692248f	49	#define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
76538ec6	50	#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
77c42e80 AM	51
77c42e80 AM	52	/* TRANSFER STATUS */
f692248f	53	#define SPI_XFER_STS_RDY BIT(30)
77c42e80 AM	54
77c42e80 AM	55	/* FIFO STATUS */
f692248f JT	56	#define SPI_FIFO_STS_CS_INACTIVE BIT(31)
	57	#define SPI_FIFO_STS_FRAME_END BIT(30)
	58	#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
	59	#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
	60	#define SPI_FIFO_STS_ERR BIT(8)
	61	#define SPI_FIFO_STS_TX_FIFO_OVF BIT(7)
	62	#define SPI_FIFO_STS_TX_FIFO_UNR BIT(6)
	63	#define SPI_FIFO_STS_RX_FIFO_OVF BIT(5)
	64	#define SPI_FIFO_STS_RX_FIFO_UNR BIT(4)
	65	#define SPI_FIFO_STS_TX_FIFO_FULL BIT(3)
	66	#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
	67	#define SPI_FIFO_STS_RX_FIFO_FULL BIT(1)
	68	#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
77c42e80 AM	69
	70	#define SPI_TIMEOUT 1000
	71	#define TEGRA_SPI_MAX_FREQ 52000000
	72
	73	struct spi_regs {
	74	u32 command1; /* 000:SPI_COMMAND1 register */
	75	u32 command2; /* 004:SPI_COMMAND2 register */
	76	u32 timing1; /* 008:SPI_CS_TIM1 register */
	77	u32 timing2; /* 00c:SPI_CS_TIM2 register */
	78	u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
	79	u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
	80	u32 tx_data; /* 018:SPI_TX_DATA register */
	81	u32 rx_data; /* 01c:SPI_RX_DATA register */
	82	u32 dma_ctl; /* 020:SPI_DMA_CTL register */
	83	u32 dma_blk; /* 024:SPI_DMA_BLK register */
	84	u32 rsvd[56]; /* 028-107 reserved */
	85	u32 tx_fifo; /* 108:SPI_FIFO1 register */
	86	u32 rsvd2[31]; /* 10c-187 reserved */
	87	u32 rx_fifo; /* 188:SPI_FIFO2 register */
	88	u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
	89	};
	90
fda6fac3	91	struct tegra114_spi_priv {
77c42e80 AM	92	struct spi_regs *regs;
	93	unsigned int freq;
	94	unsigned int mode;
	95	int periph_id;
	96	int valid;
fda6fac3	97	int last_transaction_us;
77c42e80 AM	98	};
77c42e80 AM	99
fda6fac3	100	static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
77c42e80	101	{
fda6fac3 SG	102	struct tegra_spi_platdata *plat = bus->platdata;
fda6fac3 SG	103	const void *blob = gd->fdt_blob;
e160f7d4	104	int node = dev_of_offset(bus);
77c42e80	105
a821c4af	106	plat->base = devfdt_get_addr(bus);
fda6fac3	107	plat->periph_id = clock_decode_periph_id(blob, node);
77c42e80	108
fda6fac3 SG	109	if (plat->periph_id == PERIPH_ID_NONE) {
	110	debug("%s: could not decode periph id %d\n", __func__,
	111	plat->periph_id);
	112	return -FDT_ERR_NOTFOUND;
77c42e80 AM	113	}
77c42e80 AM	114
fda6fac3 SG	115	/* Use 500KHz as a suitable default */
	116	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
	117	500000);
	118	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
	119	"spi-deactivate-delay", 0);
	120	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
	121	__func__, plat->base, plat->periph_id, plat->frequency,
	122	plat->deactivate_delay_us);
77c42e80	123
fda6fac3	124	return 0;
77c42e80 AM	125	}
77c42e80 AM	126
fda6fac3	127	static int tegra114_spi_probe(struct udevice *bus)
77c42e80	128	{
fda6fac3 SG	129	struct tegra_spi_platdata *plat = dev_get_platdata(bus);
fda6fac3 SG	130	struct tegra114_spi_priv *priv = dev_get_priv(bus);
635c2515	131	struct spi_regs *regs;
20edd1ac	132	ulong rate;
77c42e80	133
fda6fac3	134	priv->regs = (struct spi_regs *)plat->base;
635c2515	135	regs = priv->regs;
77c42e80	136
fda6fac3 SG	137	priv->last_transaction_us = timer_get_us();
	138	priv->freq = plat->frequency;
	139	priv->periph_id = plat->periph_id;
77c42e80	140
20edd1ac SG	141	/*
	142	* Change SPI clock to correct frequency, PLLP_OUT0 source, falling
	143	* back to the oscillator if that is too fast.
	144	*/
	145	rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
	146	priv->freq);
	147	if (rate > priv->freq + 100000) {
	148	rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
	149	priv->freq);
	150	if (rate != priv->freq) {
	151	printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
	152	bus->name, priv->freq, rate);
	153	}
	154	}
4a7b9ee1	155	udelay(plat->deactivate_delay_us);
77c42e80 AM	156
	157	/* Clear stale status here */
	158	setbits_le32(&regs->fifo_status,
	159	SPI_FIFO_STS_ERR \|
	160	SPI_FIFO_STS_TX_FIFO_OVF \|
	161	SPI_FIFO_STS_TX_FIFO_UNR \|
	162	SPI_FIFO_STS_RX_FIFO_OVF \|
	163	SPI_FIFO_STS_RX_FIFO_UNR \|
	164	SPI_FIFO_STS_TX_FIFO_FULL \|
	165	SPI_FIFO_STS_TX_FIFO_EMPTY \|
	166	SPI_FIFO_STS_RX_FIFO_FULL \|
	167	SPI_FIFO_STS_RX_FIFO_EMPTY);
	168	debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
	169
635c2515 SG	170	setbits_le32(&priv->regs->command1, SPI_CMD1_M_S \| SPI_CMD1_CS_SW_HW \|
635c2515 SG	171	(priv->mode << SPI_CMD1_MODE_SHIFT) \| SPI_CMD1_CS_SW_VAL);
77c42e80 AM	172	debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
	173
	174	return 0;
	175	}
	176
fda6fac3 SG	177	/**
	178	* Activate the CS by driving it LOW
	179	*
	180	* @param slave Pointer to spi_slave to which controller has to
	181	* communicate with
	182	*/
	183	static void spi_cs_activate(struct udevice *dev)
77c42e80	184	{
fda6fac3 SG	185	struct udevice *bus = dev->parent;
	186	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
	187	struct tegra114_spi_priv *priv = dev_get_priv(bus);
	188
	189	/* If it's too soon to do another transaction, wait */
	190	if (pdata->deactivate_delay_us &&
	191	priv->last_transaction_us) {
	192	ulong delay_us; /* The delay completed so far */
	193	delay_us = timer_get_us() - priv->last_transaction_us;
	194	if (delay_us < pdata->deactivate_delay_us)
	195	udelay(pdata->deactivate_delay_us - delay_us);
	196	}
77c42e80	197
fda6fac3	198	clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
77c42e80 AM	199	}
77c42e80 AM	200
fda6fac3 SG	201	/**
	202	* Deactivate the CS by driving it HIGH
	203	*
	204	* @param slave Pointer to spi_slave to which controller has to
	205	* communicate with
	206	*/
	207	static void spi_cs_deactivate(struct udevice *dev)
77c42e80	208	{
fda6fac3 SG	209	struct udevice *bus = dev->parent;
	210	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
	211	struct tegra114_spi_priv *priv = dev_get_priv(bus);
	212
	213	setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
77c42e80	214
fda6fac3 SG	215	/* Remember time of this transaction so we can honour the bus delay */
	216	if (pdata->deactivate_delay_us)
	217	priv->last_transaction_us = timer_get_us();
	218
	219	debug("Deactivate CS, bus '%s'\n", bus->name);
77c42e80 AM	220	}
77c42e80 AM	221
fda6fac3 SG	222	static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
	223	const void data_out, void data_in,
	224	unsigned long flags)
77c42e80	225	{
fda6fac3 SG	226	struct udevice *bus = dev->parent;
	227	struct tegra114_spi_priv *priv = dev_get_priv(bus);
	228	struct spi_regs *regs = priv->regs;
77c42e80 AM	229	u32 reg, tmpdout, tmpdin = 0;
	230	const u8 *dout = data_out;
	231	u8 *din = data_in;
	232	int num_bytes;
	233	int ret;
	234
	235	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
fda6fac3	236	__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
77c42e80 AM	237	if (bitlen % 8)
	238	return -1;
	239	num_bytes = bitlen / 8;
	240
	241	ret = 0;
	242
635c2515 SG	243	if (flags & SPI_XFER_BEGIN)
	244	spi_cs_activate(dev);
	245
77c42e80 AM	246	/* clear all error status bits */
	247	reg = readl(&regs->fifo_status);
	248	writel(reg, &regs->fifo_status);
	249
77c42e80 AM	250	clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
77c42e80 AM	251	SPI_CMD1_RX_EN \| SPI_CMD1_TX_EN \| SPI_CMD1_LSBY_FE \|
fda6fac3	252	(spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
77c42e80 AM	253
	254	/* set xfer size to 1 block (32 bits) */
	255	writel(0, &regs->dma_blk);
	256
77c42e80 AM	257	/* handle data in 32-bit chunks */
	258	while (num_bytes > 0) {
	259	int bytes;
77c42e80 AM	260	int tm, i;
	261
	262	tmpdout = 0;
	263	bytes = (num_bytes > 4) ? 4 : num_bytes;
	264
	265	if (dout != NULL) {
	266	for (i = 0; i < bytes; ++i)
	267	tmpdout = (tmpdout << 8) \| dout[i];
	268	dout += bytes;
	269	}
	270
	271	num_bytes -= bytes;
	272
60acde43 YL	273	/* clear ready bit */
	274	setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
	275
77c42e80 AM	276	clrsetbits_le32(&regs->command1,
	277	SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
	278	(bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
	279	writel(tmpdout, &regs->tx_fifo);
	280	setbits_le32(&regs->command1, SPI_CMD1_GO);
	281
	282	/*
	283	* Wait for SPI transmit FIFO to empty, or to time out.
	284	* The RX FIFO status will be read and cleared last
	285	*/
60acde43	286	for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
77c42e80 AM	287	u32 fifo_status, xfer_status;
77c42e80 AM	288
77c42e80 AM	289	xfer_status = readl(&regs->xfer_status);
	290	if (!(xfer_status & SPI_XFER_STS_RDY))
	291	continue;
	292
60acde43	293	fifo_status = readl(&regs->fifo_status);
77c42e80 AM	294	if (fifo_status & SPI_FIFO_STS_ERR) {
	295	debug("%s: got a fifo error: ", __func__);
	296	if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
	297	debug("tx FIFO overflow ");
	298	if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
	299	debug("tx FIFO underrun ");
	300	if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
	301	debug("rx FIFO overflow ");
	302	if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
	303	debug("rx FIFO underrun ");
	304	if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
	305	debug("tx FIFO full ");
	306	if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
	307	debug("tx FIFO empty ");
	308	if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
	309	debug("rx FIFO full ");
	310	if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
	311	debug("rx FIFO empty ");
	312	debug("\n");
	313	break;
	314	}
	315
	316	if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
	317	tmpdin = readl(&regs->rx_fifo);
77c42e80 AM	318
	319	/* swap bytes read in */
	320	if (din != NULL) {
	321	for (i = bytes - 1; i >= 0; --i) {
	322	din[i] = tmpdin & 0xff;
	323	tmpdin >>= 8;
	324	}
	325	din += bytes;
	326	}
60acde43 YL	327
	328	/* We can exit when we've had both RX and TX */
	329	break;
77c42e80 AM	330	}
	331	}
	332
	333	if (tm >= SPI_TIMEOUT)
	334	ret = tm;
	335
	336	/* clear ACK RDY, etc. bits */
	337	writel(readl(&regs->fifo_status), &regs->fifo_status);
	338	}
	339
	340	if (flags & SPI_XFER_END)
fda6fac3	341	spi_cs_deactivate(dev);
77c42e80 AM	342
	343	debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
	344	__func__, tmpdin, readl(&regs->fifo_status));
	345
	346	if (ret) {
	347	printf("%s: timeout during SPI transfer, tm %d\n",
	348	__func__, ret);
	349	return -1;
	350	}
	351
fda6fac3 SG	352	return ret;
	353	}
	354
	355	static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
	356	{
	357	struct tegra_spi_platdata *plat = bus->platdata;
	358	struct tegra114_spi_priv *priv = dev_get_priv(bus);
	359
	360	if (speed > plat->frequency)
	361	speed = plat->frequency;
	362	priv->freq = speed;
	363	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
	364
77c42e80 AM	365	return 0;
77c42e80 AM	366	}
fda6fac3 SG	367
	368	static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
	369	{
	370	struct tegra114_spi_priv *priv = dev_get_priv(bus);
	371
	372	priv->mode = mode;
	373	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
	374
	375	return 0;
	376	}
	377
	378	static const struct dm_spi_ops tegra114_spi_ops = {
fda6fac3 SG	379	.xfer = tegra114_spi_xfer,
	380	.set_speed = tegra114_spi_set_speed,
	381	.set_mode = tegra114_spi_set_mode,
	382	/*
	383	* cs_info is not needed, since we require all chip selects to be
	384	* in the device tree explicitly
	385	*/
	386	};
	387
	388	static const struct udevice_id tegra114_spi_ids[] = {
	389	{ .compatible = "nvidia,tegra114-spi" },
	390	{ }
	391	};
	392
	393	U_BOOT_DRIVER(tegra114_spi) = {
	394	.name = "tegra114_spi",
	395	.id = UCLASS_SPI,
	396	.of_match = tegra114_spi_ids,
	397	.ops = &tegra114_spi_ops,
	398	.ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
	399	.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
	400	.priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
fda6fac3 SG	401	.probe = tegra114_spi_probe,
fda6fac3 SG	402	};