]> Git Repo - J-u-boot.git/blame - cmd/i2c.c
cmd: Add a memory-search command
[J-u-boot.git] / cmd / i2c.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
81a8824f 2/*
3f4978c7
HS
3 * (C) Copyright 2009
4 * Sergey Kubushyn, himself, [email protected]
5 *
6 * Changes for unified multibus/multiadapter I2C support.
7 *
81a8824f
WD
8 * (C) Copyright 2001
9 * Gerald Van Baren, Custom IDEAS, [email protected].
81a8824f
WD
10 */
11
12/*
13 * I2C Functions similar to the standard memory functions.
14 *
15 * There are several parameters in many of the commands that bear further
16 * explanations:
17 *
81a8824f
WD
18 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
19 * Each I2C chip on the bus has a unique address. On the I2C data bus,
20 * the address is the upper seven bits and the LSB is the "read/write"
21 * bit. Note that the {i2c_chip} address specified on the command
22 * line is not shifted up: e.g. a typical EEPROM memory chip may have
23 * an I2C address of 0x50, but the data put on the bus will be 0xA0
24 * for write and 0xA1 for read. This "non shifted" address notation
25 * matches at least half of the data sheets :-/.
26 *
27 * {addr} is the address (or offset) within the chip. Small memory
28 * chips have 8 bit addresses. Large memory chips have 16 bit
29 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
30 * Many non-memory chips have multiple registers and {addr} is used
31 * as the register index. Some non-memory chips have only one register
32 * and therefore don't need any {addr} parameter.
33 *
34 * The default {addr} parameter is one byte (.1) which works well for
35 * memories and registers with 8 bits of address space.
36 *
37 * You can specify the length of the {addr} field with the optional .0,
38 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
39 * manipulating a single register device which doesn't use an address
40 * field, use "0.0" for the address and the ".0" length field will
41 * suppress the address in the I2C data stream. This also works for
42 * successive reads using the I2C auto-incrementing memory pointer.
43 *
44 * If you are manipulating a large memory with 2-byte addresses, use
45 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
46 *
47 * Then there are the unfortunate memory chips that spill the most
48 * significant 1, 2, or 3 bits of address into the chip address byte.
49 * This effectively makes one chip (logically) look like 2, 4, or
50 * 8 chips. This is handled (awkwardly) by #defining
6d0f6bcf 51 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
81a8824f
WD
52 * {addr} field (since .1 is the default, it doesn't actually have to
53 * be specified). Examples: given a memory chip at I2C chip address
54 * 0x50, the following would happen...
0f89c54b 55 * i2c md 50 0 10 display 16 bytes starting at 0x000
81a8824f 56 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
0f89c54b 57 * i2c md 50 100 10 display 16 bytes starting at 0x100
81a8824f 58 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
0f89c54b 59 * i2c md 50 210 10 display 16 bytes starting at 0x210
81a8824f
WD
60 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
61 * This is awfully ugly. It would be nice if someone would think up
62 * a better way of handling this.
63 *
64 * Adapted from cmd_mem.c which is copyright Wolfgang Denk ([email protected]).
65 */
66
67#include <common.h>
0098e179 68#include <bootretry.h>
18d66533 69#include <cli.h>
81a8824f 70#include <command.h>
24b852a7 71#include <console.h>
63656b76 72#include <dm.h>
735987c5 73#include <edid.h>
63656b76 74#include <errno.h>
81a8824f 75#include <i2c.h>
f7ae49fc 76#include <log.h>
67b23a32 77#include <malloc.h>
81a8824f 78#include <asm/byteorder.h>
2515d843 79#include <linux/compiler.h>
c05ed00a 80#include <linux/delay.h>
3db71108 81#include <u-boot/crc.h>
81a8824f 82
81a8824f
WD
83/* Display values from last command.
84 * Memory modify remembered values are different from display memory.
85 */
5468461d 86static uint i2c_dp_last_chip;
81a8824f
WD
87static uint i2c_dp_last_addr;
88static uint i2c_dp_last_alen;
89static uint i2c_dp_last_length = 0x10;
90
5468461d 91static uint i2c_mm_last_chip;
81a8824f
WD
92static uint i2c_mm_last_addr;
93static uint i2c_mm_last_alen;
94
bb99ad6d
BW
95/* If only one I2C bus is present, the list of devices to ignore when
96 * the probe command is issued is represented by a 1D array of addresses.
97 * When multiple buses are present, the list is an array of bus-address
98 * pairs. The following macros take care of this */
99
6d0f6bcf 100#if defined(CONFIG_SYS_I2C_NOPROBES)
9a2accb4 101#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
bb99ad6d
BW
102static struct
103{
104 uchar bus;
105 uchar addr;
6d0f6bcf 106} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
107#define GET_BUS_NUM i2c_get_bus_num()
108#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
109#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
110#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
111#else /* single bus */
6d0f6bcf 112static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
113#define GET_BUS_NUM 0
114#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
115#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
116#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
3f4978c7 117#endif /* defined(CONFIG_SYS_I2C) */
67b23a32
HS
118#endif
119
a266fe95
FM
120#define DISP_LINE_LEN 16
121
63656b76
SG
122/*
123 * Default for driver model is to use the chip's existing address length.
124 * For legacy code, this is not stored, so we need to use a suitable
125 * default.
126 */
127#ifdef CONFIG_DM_I2C
128#define DEFAULT_ADDR_LEN (-1)
129#else
130#define DEFAULT_ADDR_LEN 1
131#endif
132
133#ifdef CONFIG_DM_I2C
134static struct udevice *i2c_cur_bus;
135
f9a4c2da 136static int cmd_i2c_set_bus_num(unsigned int busnum)
63656b76
SG
137{
138 struct udevice *bus;
139 int ret;
140
141 ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
142 if (ret) {
143 debug("%s: No bus %d\n", __func__, busnum);
144 return ret;
145 }
146 i2c_cur_bus = bus;
147
148 return 0;
149}
150
151static int i2c_get_cur_bus(struct udevice **busp)
152{
e46f8a33
LM
153#ifdef CONFIG_I2C_SET_DEFAULT_BUS_NUM
154 if (!i2c_cur_bus) {
155 if (cmd_i2c_set_bus_num(CONFIG_I2C_DEFAULT_BUS_NUMBER)) {
156 printf("Default I2C bus %d not found\n",
157 CONFIG_I2C_DEFAULT_BUS_NUMBER);
158 return -ENODEV;
159 }
160 }
161#endif
162
63656b76
SG
163 if (!i2c_cur_bus) {
164 puts("No I2C bus selected\n");
165 return -ENODEV;
166 }
167 *busp = i2c_cur_bus;
168
169 return 0;
170}
171
172static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
173{
174 struct udevice *bus;
175 int ret;
176
177 ret = i2c_get_cur_bus(&bus);
178 if (ret)
179 return ret;
180
25ab4b03 181 return i2c_get_chip(bus, chip_addr, 1, devp);
63656b76
SG
182}
183
184#endif
185
06afa388
MV
186/**
187 * i2c_init_board() - Board-specific I2C bus init
188 *
189 * This function is the default no-op implementation of I2C bus
62a3b7dd 190 * initialization. This function can be overridden by board-specific
06afa388
MV
191 * implementation if needed.
192 */
2515d843
MV
193__weak
194void i2c_init_board(void)
c649dda5 195{
c649dda5 196}
c649dda5 197
655b34a7 198/* TODO: Implement architecture-specific get/set functions */
06afa388
MV
199
200/**
201 * i2c_get_bus_speed() - Return I2C bus speed
202 *
203 * This function is the default implementation of function for retrieveing
204 * the current I2C bus speed in Hz.
205 *
206 * A driver implementing runtime switching of I2C bus speed must override
207 * this function to report the speed correctly. Simple or legacy drivers
208 * can use this fallback.
209 *
210 * Returns I2C bus speed in Hz.
211 */
63656b76 212#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
3f4978c7
HS
213/*
214 * TODO: Implement architecture-specific get/set functions
215 * Should go away, if we switched completely to new multibus support
216 */
2515d843
MV
217__weak
218unsigned int i2c_get_bus_speed(void)
655b34a7
PT
219{
220 return CONFIG_SYS_I2C_SPEED;
221}
655b34a7 222
06afa388
MV
223/**
224 * i2c_set_bus_speed() - Configure I2C bus speed
225 * @speed: Newly set speed of the I2C bus in Hz
226 *
227 * This function is the default implementation of function for setting
228 * the I2C bus speed in Hz.
229 *
230 * A driver implementing runtime switching of I2C bus speed must override
231 * this function to report the speed correctly. Simple or legacy drivers
232 * can use this fallback.
233 *
234 * Returns zero on success, negative value on error.
235 */
2515d843
MV
236__weak
237int i2c_set_bus_speed(unsigned int speed)
655b34a7
PT
238{
239 if (speed != CONFIG_SYS_I2C_SPEED)
240 return -1;
241
242 return 0;
243}
3f4978c7 244#endif
655b34a7 245
06afa388
MV
246/**
247 * get_alen() - Small parser helper function to get address length
248 *
249 * Returns the address length.
2c0dc990 250 */
63656b76 251static uint get_alen(char *arg, int default_len)
2c0dc990
FM
252{
253 int j;
254 int alen;
255
63656b76 256 alen = default_len;
2c0dc990
FM
257 for (j = 0; j < 8; j++) {
258 if (arg[j] == '.') {
259 alen = arg[j+1] - '0';
2c0dc990
FM
260 break;
261 } else if (arg[j] == '\0')
262 break;
263 }
264 return alen;
265}
266
c1a6f371
SG
267enum i2c_err_op {
268 I2C_ERR_READ,
269 I2C_ERR_WRITE,
270};
271
272static int i2c_report_err(int ret, enum i2c_err_op op)
273{
274 printf("Error %s the chip: %d\n",
275 op == I2C_ERR_READ ? "reading" : "writing", ret);
276
277 return CMD_RET_FAILURE;
278}
279
06afa388
MV
280/**
281 * do_i2c_read() - Handle the "i2c read" command-line command
282 * @cmdtp: Command data struct pointer
283 * @flag: Command flag
284 * @argc: Command-line argument count
285 * @argv: Array of command-line arguments
286 *
287 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
288 * on error.
289 *
652e5354
FM
290 * Syntax:
291 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
292 */
09140113
SG
293static int do_i2c_read(struct cmd_tbl *cmdtp, int flag, int argc,
294 char *const argv[])
652e5354 295{
5468461d 296 uint chip;
63656b76
SG
297 uint devaddr, length;
298 int alen;
652e5354 299 u_char *memaddr;
63656b76
SG
300 int ret;
301#ifdef CONFIG_DM_I2C
302 struct udevice *dev;
303#endif
652e5354 304
47e26b1b 305 if (argc != 5)
4c12eeb8 306 return CMD_RET_USAGE;
652e5354
FM
307
308 /*
309 * I2C chip address
310 */
311 chip = simple_strtoul(argv[1], NULL, 16);
312
313 /*
314 * I2C data address within the chip. This can be 1 or
315 * 2 bytes long. Some day it might be 3 bytes long :-).
316 */
317 devaddr = simple_strtoul(argv[2], NULL, 16);
63656b76 318 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 319 if (alen > 3)
4c12eeb8 320 return CMD_RET_USAGE;
652e5354
FM
321
322 /*
323 * Length is the number of objects, not number of bytes.
324 */
325 length = simple_strtoul(argv[3], NULL, 16);
326
327 /*
328 * memaddr is the address where to store things in memory
329 */
330 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
331
63656b76
SG
332#ifdef CONFIG_DM_I2C
333 ret = i2c_get_cur_bus_chip(chip, &dev);
334 if (!ret && alen != -1)
335 ret = i2c_set_chip_offset_len(dev, alen);
336 if (!ret)
f9a4c2da 337 ret = dm_i2c_read(dev, devaddr, memaddr, length);
63656b76
SG
338#else
339 ret = i2c_read(chip, devaddr, alen, memaddr, length);
340#endif
341 if (ret)
342 return i2c_report_err(ret, I2C_ERR_READ);
343
652e5354
FM
344 return 0;
345}
346
09140113
SG
347static int do_i2c_write(struct cmd_tbl *cmdtp, int flag, int argc,
348 char *const argv[])
ff5d2dce 349{
5468461d 350 uint chip;
63656b76
SG
351 uint devaddr, length;
352 int alen;
ff5d2dce 353 u_char *memaddr;
63656b76
SG
354 int ret;
355#ifdef CONFIG_DM_I2C
356 struct udevice *dev;
ed16f146 357 struct dm_i2c_chip *i2c_chip;
63656b76 358#endif
ff5d2dce 359
ed16f146 360 if ((argc < 5) || (argc > 6))
ff5d2dce
YS
361 return cmd_usage(cmdtp);
362
363 /*
364 * memaddr is the address where to store things in memory
365 */
366 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
367
368 /*
369 * I2C chip address
370 */
371 chip = simple_strtoul(argv[2], NULL, 16);
372
373 /*
374 * I2C data address within the chip. This can be 1 or
375 * 2 bytes long. Some day it might be 3 bytes long :-).
376 */
377 devaddr = simple_strtoul(argv[3], NULL, 16);
63656b76 378 alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
ff5d2dce
YS
379 if (alen > 3)
380 return cmd_usage(cmdtp);
381
382 /*
ed16f146 383 * Length is the number of bytes.
ff5d2dce
YS
384 */
385 length = simple_strtoul(argv[4], NULL, 16);
386
63656b76
SG
387#ifdef CONFIG_DM_I2C
388 ret = i2c_get_cur_bus_chip(chip, &dev);
389 if (!ret && alen != -1)
390 ret = i2c_set_chip_offset_len(dev, alen);
391 if (ret)
392 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
393 i2c_chip = dev_get_parent_platdata(dev);
394 if (!i2c_chip)
395 return i2c_report_err(ret, I2C_ERR_WRITE);
63656b76
SG
396#endif
397
ed16f146
LP
398 if (argc == 6 && !strcmp(argv[5], "-s")) {
399 /*
400 * Write all bytes in a single I2C transaction. If the target
401 * device is an EEPROM, it is your responsibility to not cross
402 * a page boundary. No write delay upon completion, take this
403 * into account if linking commands.
404 */
63656b76 405#ifdef CONFIG_DM_I2C
ed16f146
LP
406 i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
407 ret = dm_i2c_write(dev, devaddr, memaddr, length);
63656b76 408#else
ed16f146 409 ret = i2c_write(chip, devaddr, alen, memaddr, length);
63656b76
SG
410#endif
411 if (ret)
412 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
413 } else {
414 /*
415 * Repeated addressing - perform <length> separate
416 * write transactions of one byte each
417 */
418 while (length-- > 0) {
419#ifdef CONFIG_DM_I2C
420 i2c_chip->flags |= DM_I2C_CHIP_WR_ADDRESS;
421 ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
422#else
423 ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
424#endif
425 if (ret)
426 return i2c_report_err(ret, I2C_ERR_WRITE);
ff5d2dce
YS
427/*
428 * No write delay with FRAM devices.
429 */
430#if !defined(CONFIG_SYS_I2C_FRAM)
ed16f146 431 udelay(11000);
ff5d2dce 432#endif
ed16f146 433 }
ff5d2dce
YS
434 }
435 return 0;
436}
437
63656b76 438#ifdef CONFIG_DM_I2C
09140113 439static int do_i2c_flags(struct cmd_tbl *cmdtp, int flag, int argc,
63656b76
SG
440 char *const argv[])
441{
442 struct udevice *dev;
443 uint flags;
444 int chip;
445 int ret;
446
447 if (argc < 2)
448 return CMD_RET_USAGE;
449
450 chip = simple_strtoul(argv[1], NULL, 16);
451 ret = i2c_get_cur_bus_chip(chip, &dev);
452 if (ret)
453 return i2c_report_err(ret, I2C_ERR_READ);
454
455 if (argc > 2) {
456 flags = simple_strtoul(argv[2], NULL, 16);
457 ret = i2c_set_chip_flags(dev, flags);
458 } else {
459 ret = i2c_get_chip_flags(dev, &flags);
460 if (!ret)
461 printf("%x\n", flags);
462 }
463 if (ret)
464 return i2c_report_err(ret, I2C_ERR_READ);
465
466 return 0;
467}
c10c8e31 468
09140113
SG
469static int do_i2c_olen(struct cmd_tbl *cmdtp, int flag, int argc,
470 char *const argv[])
c10c8e31
SG
471{
472 struct udevice *dev;
473 uint olen;
474 int chip;
475 int ret;
476
477 if (argc < 2)
478 return CMD_RET_USAGE;
479
480 chip = simple_strtoul(argv[1], NULL, 16);
481 ret = i2c_get_cur_bus_chip(chip, &dev);
482 if (ret)
483 return i2c_report_err(ret, I2C_ERR_READ);
484
485 if (argc > 2) {
486 olen = simple_strtoul(argv[2], NULL, 16);
487 ret = i2c_set_chip_offset_len(dev, olen);
488 } else {
489 ret = i2c_get_chip_offset_len(dev);
490 if (ret >= 0) {
491 printf("%x\n", ret);
492 ret = 0;
493 }
494 }
495 if (ret)
496 return i2c_report_err(ret, I2C_ERR_READ);
497
498 return 0;
499}
63656b76
SG
500#endif
501
06afa388
MV
502/**
503 * do_i2c_md() - Handle the "i2c md" command-line command
504 * @cmdtp: Command data struct pointer
505 * @flag: Command flag
506 * @argc: Command-line argument count
507 * @argv: Array of command-line arguments
508 *
509 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
510 * on error.
511 *
4a8cf338
FM
512 * Syntax:
513 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
514 */
09140113
SG
515static int do_i2c_md(struct cmd_tbl *cmdtp, int flag, int argc,
516 char *const argv[])
81a8824f 517{
5468461d 518 uint chip;
63656b76
SG
519 uint addr, length;
520 int alen;
81a8824f 521 int j, nbytes, linebytes;
63656b76
SG
522 int ret;
523#ifdef CONFIG_DM_I2C
524 struct udevice *dev;
525#endif
81a8824f
WD
526
527 /* We use the last specified parameters, unless new ones are
528 * entered.
529 */
530 chip = i2c_dp_last_chip;
531 addr = i2c_dp_last_addr;
532 alen = i2c_dp_last_alen;
533 length = i2c_dp_last_length;
534
47e26b1b 535 if (argc < 3)
4c12eeb8 536 return CMD_RET_USAGE;
81a8824f
WD
537
538 if ((flag & CMD_FLAG_REPEAT) == 0) {
539 /*
540 * New command specified.
541 */
81a8824f
WD
542
543 /*
544 * I2C chip address
545 */
546 chip = simple_strtoul(argv[1], NULL, 16);
547
548 /*
549 * I2C data address within the chip. This can be 1 or
550 * 2 bytes long. Some day it might be 3 bytes long :-).
551 */
552 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 553 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 554 if (alen > 3)
4c12eeb8 555 return CMD_RET_USAGE;
81a8824f
WD
556
557 /*
558 * If another parameter, it is the length to display.
559 * Length is the number of objects, not number of bytes.
560 */
561 if (argc > 3)
562 length = simple_strtoul(argv[3], NULL, 16);
563 }
564
63656b76
SG
565#ifdef CONFIG_DM_I2C
566 ret = i2c_get_cur_bus_chip(chip, &dev);
567 if (!ret && alen != -1)
568 ret = i2c_set_chip_offset_len(dev, alen);
569 if (ret)
570 return i2c_report_err(ret, I2C_ERR_READ);
571#endif
572
81a8824f
WD
573 /*
574 * Print the lines.
575 *
576 * We buffer all read data, so we can make sure data is read only
577 * once.
578 */
579 nbytes = length;
580 do {
581 unsigned char linebuf[DISP_LINE_LEN];
582 unsigned char *cp;
583
584 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
585
63656b76 586#ifdef CONFIG_DM_I2C
f9a4c2da 587 ret = dm_i2c_read(dev, addr, linebuf, linebytes);
63656b76
SG
588#else
589 ret = i2c_read(chip, addr, alen, linebuf, linebytes);
590#endif
591 if (ret)
9e533cb0 592 return i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 593 else {
81a8824f
WD
594 printf("%04x:", addr);
595 cp = linebuf;
596 for (j=0; j<linebytes; j++) {
597 printf(" %02x", *cp++);
598 addr++;
599 }
4b9206ed 600 puts (" ");
81a8824f
WD
601 cp = linebuf;
602 for (j=0; j<linebytes; j++) {
603 if ((*cp < 0x20) || (*cp > 0x7e))
4b9206ed 604 puts (".");
81a8824f
WD
605 else
606 printf("%c", *cp);
607 cp++;
608 }
4b9206ed 609 putc ('\n');
81a8824f
WD
610 }
611 nbytes -= linebytes;
612 } while (nbytes > 0);
613
614 i2c_dp_last_chip = chip;
615 i2c_dp_last_addr = addr;
616 i2c_dp_last_alen = alen;
617 i2c_dp_last_length = length;
618
619 return 0;
620}
621
06afa388
MV
622/**
623 * do_i2c_mw() - Handle the "i2c mw" command-line command
624 * @cmdtp: Command data struct pointer
625 * @flag: Command flag
626 * @argc: Command-line argument count
627 * @argv: Array of command-line arguments
628 *
629 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
630 * on error.
81a8824f
WD
631 *
632 * Syntax:
0f89c54b 633 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
81a8824f 634 */
09140113
SG
635static int do_i2c_mw(struct cmd_tbl *cmdtp, int flag, int argc,
636 char *const argv[])
81a8824f 637{
5468461d 638 uint chip;
81a8824f 639 ulong addr;
63656b76 640 int alen;
81a8824f
WD
641 uchar byte;
642 int count;
63656b76
SG
643 int ret;
644#ifdef CONFIG_DM_I2C
645 struct udevice *dev;
646#endif
81a8824f 647
47e26b1b 648 if ((argc < 4) || (argc > 5))
4c12eeb8 649 return CMD_RET_USAGE;
81a8824f
WD
650
651 /*
53677ef1
WD
652 * Chip is always specified.
653 */
81a8824f
WD
654 chip = simple_strtoul(argv[1], NULL, 16);
655
656 /*
657 * Address is always specified.
658 */
659 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 660 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 661 if (alen > 3)
4c12eeb8 662 return CMD_RET_USAGE;
81a8824f 663
63656b76
SG
664#ifdef CONFIG_DM_I2C
665 ret = i2c_get_cur_bus_chip(chip, &dev);
666 if (!ret && alen != -1)
667 ret = i2c_set_chip_offset_len(dev, alen);
668 if (ret)
669 return i2c_report_err(ret, I2C_ERR_WRITE);
670#endif
81a8824f
WD
671 /*
672 * Value to write is always specified.
673 */
674 byte = simple_strtoul(argv[3], NULL, 16);
675
676 /*
677 * Optional count
678 */
e857a5bd 679 if (argc == 5)
81a8824f 680 count = simple_strtoul(argv[4], NULL, 16);
e857a5bd 681 else
81a8824f 682 count = 1;
81a8824f
WD
683
684 while (count-- > 0) {
63656b76 685#ifdef CONFIG_DM_I2C
f9a4c2da 686 ret = dm_i2c_write(dev, addr++, &byte, 1);
63656b76
SG
687#else
688 ret = i2c_write(chip, addr++, alen, &byte, 1);
689#endif
690 if (ret)
9e533cb0 691 return i2c_report_err(ret, I2C_ERR_WRITE);
81a8824f
WD
692 /*
693 * Wait for the write to complete. The write can take
694 * up to 10mSec (we allow a little more time).
81a8824f 695 */
d4f5c728 696/*
697 * No write delay with FRAM devices.
698 */
6d0f6bcf 699#if !defined(CONFIG_SYS_I2C_FRAM)
81a8824f 700 udelay(11000);
d4f5c728 701#endif
81a8824f
WD
702 }
703
06afa388 704 return 0;
81a8824f
WD
705}
706
06afa388
MV
707/**
708 * do_i2c_crc() - Handle the "i2c crc32" command-line command
709 * @cmdtp: Command data struct pointer
710 * @flag: Command flag
711 * @argc: Command-line argument count
712 * @argv: Array of command-line arguments
713 *
714 * Calculate a CRC on memory
715 *
716 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
717 * on error.
81a8824f
WD
718 *
719 * Syntax:
0f89c54b 720 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
81a8824f 721 */
09140113
SG
722static int do_i2c_crc(struct cmd_tbl *cmdtp, int flag, int argc,
723 char *const argv[])
81a8824f 724{
5468461d 725 uint chip;
81a8824f 726 ulong addr;
63656b76 727 int alen;
81a8824f
WD
728 int count;
729 uchar byte;
730 ulong crc;
731 ulong err;
63656b76
SG
732 int ret = 0;
733#ifdef CONFIG_DM_I2C
734 struct udevice *dev;
735#endif
81a8824f 736
47e26b1b 737 if (argc < 4)
4c12eeb8 738 return CMD_RET_USAGE;
81a8824f
WD
739
740 /*
53677ef1
WD
741 * Chip is always specified.
742 */
81a8824f
WD
743 chip = simple_strtoul(argv[1], NULL, 16);
744
745 /*
746 * Address is always specified.
747 */
748 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 749 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 750 if (alen > 3)
4c12eeb8 751 return CMD_RET_USAGE;
81a8824f 752
63656b76
SG
753#ifdef CONFIG_DM_I2C
754 ret = i2c_get_cur_bus_chip(chip, &dev);
755 if (!ret && alen != -1)
756 ret = i2c_set_chip_offset_len(dev, alen);
757 if (ret)
758 return i2c_report_err(ret, I2C_ERR_READ);
759#endif
81a8824f
WD
760 /*
761 * Count is always specified
762 */
763 count = simple_strtoul(argv[3], NULL, 16);
764
765 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
766 /*
767 * CRC a byte at a time. This is going to be slooow, but hey, the
768 * memories are small and slow too so hopefully nobody notices.
769 */
770 crc = 0;
771 err = 0;
e857a5bd 772 while (count-- > 0) {
63656b76 773#ifdef CONFIG_DM_I2C
f9a4c2da 774 ret = dm_i2c_read(dev, addr, &byte, 1);
63656b76
SG
775#else
776 ret = i2c_read(chip, addr, alen, &byte, 1);
777#endif
778 if (ret)
81a8824f 779 err++;
b2ea91ba 780 crc = crc32(crc, &byte, 1);
81a8824f
WD
781 addr++;
782 }
e857a5bd 783 if (err > 0)
63656b76 784 i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 785 else
81a8824f 786 printf ("%08lx\n", crc);
81a8824f
WD
787
788 return 0;
789}
790
06afa388
MV
791/**
792 * mod_i2c_mem() - Handle the "i2c mm" and "i2c nm" command-line command
793 * @cmdtp: Command data struct pointer
794 * @flag: Command flag
795 * @argc: Command-line argument count
796 * @argv: Array of command-line arguments
797 *
798 * Modify memory.
799 *
800 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
801 * on error.
81a8824f
WD
802 *
803 * Syntax:
0f89c54b
PT
804 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
805 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
81a8824f 806 */
09140113
SG
807static int mod_i2c_mem(struct cmd_tbl *cmdtp, int incrflag, int flag, int argc,
808 char *const argv[])
81a8824f 809{
5468461d 810 uint chip;
81a8824f 811 ulong addr;
63656b76 812 int alen;
81a8824f
WD
813 ulong data;
814 int size = 1;
815 int nbytes;
63656b76
SG
816 int ret;
817#ifdef CONFIG_DM_I2C
818 struct udevice *dev;
819#endif
81a8824f 820
47e26b1b 821 if (argc != 3)
4c12eeb8 822 return CMD_RET_USAGE;
81a8824f 823
b26440f1 824 bootretry_reset_cmd_timeout(); /* got a good command to get here */
81a8824f
WD
825 /*
826 * We use the last specified parameters, unless new ones are
827 * entered.
828 */
829 chip = i2c_mm_last_chip;
830 addr = i2c_mm_last_addr;
831 alen = i2c_mm_last_alen;
832
833 if ((flag & CMD_FLAG_REPEAT) == 0) {
834 /*
835 * New command specified. Check for a size specification.
836 * Defaults to byte if no or incorrect specification.
837 */
838 size = cmd_get_data_size(argv[0], 1);
839
840 /*
53677ef1
WD
841 * Chip is always specified.
842 */
81a8824f
WD
843 chip = simple_strtoul(argv[1], NULL, 16);
844
845 /*
846 * Address is always specified.
847 */
848 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 849 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 850 if (alen > 3)
4c12eeb8 851 return CMD_RET_USAGE;
81a8824f
WD
852 }
853
63656b76
SG
854#ifdef CONFIG_DM_I2C
855 ret = i2c_get_cur_bus_chip(chip, &dev);
856 if (!ret && alen != -1)
857 ret = i2c_set_chip_offset_len(dev, alen);
858 if (ret)
859 return i2c_report_err(ret, I2C_ERR_WRITE);
860#endif
861
81a8824f
WD
862 /*
863 * Print the address, followed by value. Then accept input for
864 * the next value. A non-converted value exits.
865 */
866 do {
867 printf("%08lx:", addr);
63656b76 868#ifdef CONFIG_DM_I2C
f9a4c2da 869 ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
63656b76
SG
870#else
871 ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
872#endif
873 if (ret)
9e533cb0
MY
874 return i2c_report_err(ret, I2C_ERR_READ);
875
876 data = cpu_to_be32(data);
877 if (size == 1)
878 printf(" %02lx", (data >> 24) & 0x000000FF);
879 else if (size == 2)
880 printf(" %04lx", (data >> 16) & 0x0000FFFF);
881 else
882 printf(" %08lx", data);
81a8824f 883
e1bf824d 884 nbytes = cli_readline(" ? ");
81a8824f
WD
885 if (nbytes == 0) {
886 /*
887 * <CR> pressed as only input, don't modify current
888 * location and move to next.
889 */
890 if (incrflag)
891 addr += size;
892 nbytes = size;
b26440f1
SG
893 /* good enough to not time out */
894 bootretry_reset_cmd_timeout();
81a8824f
WD
895 }
896#ifdef CONFIG_BOOT_RETRY_TIME
e857a5bd 897 else if (nbytes == -2)
81a8824f 898 break; /* timed out, exit the command */
81a8824f
WD
899#endif
900 else {
901 char *endp;
902
903 data = simple_strtoul(console_buffer, &endp, 16);
e857a5bd 904 if (size == 1)
81a8824f 905 data = data << 24;
e857a5bd 906 else if (size == 2)
81a8824f 907 data = data << 16;
81a8824f
WD
908 data = be32_to_cpu(data);
909 nbytes = endp - console_buffer;
910 if (nbytes) {
81a8824f
WD
911 /*
912 * good enough to not time out
913 */
b26440f1 914 bootretry_reset_cmd_timeout();
63656b76 915#ifdef CONFIG_DM_I2C
f9a4c2da
SG
916 ret = dm_i2c_write(dev, addr, (uchar *)&data,
917 size);
63656b76
SG
918#else
919 ret = i2c_write(chip, addr, alen,
920 (uchar *)&data, size);
921#endif
922 if (ret)
9e533cb0
MY
923 return i2c_report_err(ret,
924 I2C_ERR_WRITE);
6d0f6bcf
JCPV
925#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
926 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
2535d602 927#endif
81a8824f
WD
928 if (incrflag)
929 addr += size;
930 }
931 }
932 } while (nbytes);
933
0800707b
PT
934 i2c_mm_last_chip = chip;
935 i2c_mm_last_addr = addr;
936 i2c_mm_last_alen = alen;
81a8824f
WD
937
938 return 0;
939}
940
06afa388
MV
941/**
942 * do_i2c_probe() - Handle the "i2c probe" command-line command
943 * @cmdtp: Command data struct pointer
944 * @flag: Command flag
945 * @argc: Command-line argument count
946 * @argv: Array of command-line arguments
947 *
948 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
949 * on error.
950 *
81a8824f 951 * Syntax:
54b99e51
EN
952 * i2c probe {addr}
953 *
954 * Returns zero (success) if one or more I2C devices was found
81a8824f 955 */
09140113
SG
956static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc,
957 char *const argv[])
81a8824f
WD
958{
959 int j;
54b99e51
EN
960 int addr = -1;
961 int found = 0;
6d0f6bcf 962#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 963 int k, skip;
3f4978c7 964 unsigned int bus = GET_BUS_NUM;
bb99ad6d 965#endif /* NOPROBES */
63656b76
SG
966 int ret;
967#ifdef CONFIG_DM_I2C
968 struct udevice *bus, *dev;
969
970 if (i2c_get_cur_bus(&bus))
971 return CMD_RET_FAILURE;
972#endif
81a8824f 973
54b99e51
EN
974 if (argc == 2)
975 addr = simple_strtol(argv[1], 0, 16);
976
4b9206ed 977 puts ("Valid chip addresses:");
e857a5bd 978 for (j = 0; j < 128; j++) {
54b99e51
EN
979 if ((0 <= addr) && (j != addr))
980 continue;
981
6d0f6bcf 982#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 983 skip = 0;
cfb25cc4 984 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 985 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
81a8824f
WD
986 skip = 1;
987 break;
988 }
989 }
990 if (skip)
991 continue;
992#endif
63656b76 993#ifdef CONFIG_DM_I2C
f9a4c2da 994 ret = dm_i2c_probe(bus, j, 0, &dev);
63656b76
SG
995#else
996 ret = i2c_probe(j);
997#endif
998 if (ret == 0) {
81a8824f 999 printf(" %02X", j);
54b99e51
EN
1000 found++;
1001 }
81a8824f 1002 }
4b9206ed 1003 putc ('\n');
81a8824f 1004
6d0f6bcf 1005#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 1006 puts ("Excluded chip addresses:");
cfb25cc4 1007 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 1008 if (COMPARE_BUS(bus,k))
bb99ad6d
BW
1009 printf(" %02X", NO_PROBE_ADDR(k));
1010 }
4b9206ed 1011 putc ('\n');
81a8824f
WD
1012#endif
1013
54b99e51 1014 return (0 == found);
81a8824f
WD
1015}
1016
06afa388
MV
1017/**
1018 * do_i2c_loop() - Handle the "i2c loop" command-line command
1019 * @cmdtp: Command data struct pointer
1020 * @flag: Command flag
1021 * @argc: Command-line argument count
1022 * @argv: Array of command-line arguments
1023 *
1024 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1025 * on error.
1026 *
81a8824f 1027 * Syntax:
0f89c54b 1028 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
81a8824f
WD
1029 * {length} - Number of bytes to read
1030 * {delay} - A DECIMAL number and defaults to 1000 uSec
1031 */
09140113
SG
1032static int do_i2c_loop(struct cmd_tbl *cmdtp, int flag, int argc,
1033 char *const argv[])
81a8824f 1034{
5468461d 1035 uint chip;
63656b76 1036 int alen;
81a8824f
WD
1037 uint addr;
1038 uint length;
1039 u_char bytes[16];
1040 int delay;
63656b76
SG
1041 int ret;
1042#ifdef CONFIG_DM_I2C
1043 struct udevice *dev;
1044#endif
81a8824f 1045
47e26b1b 1046 if (argc < 3)
4c12eeb8 1047 return CMD_RET_USAGE;
81a8824f
WD
1048
1049 /*
1050 * Chip is always specified.
1051 */
1052 chip = simple_strtoul(argv[1], NULL, 16);
1053
1054 /*
1055 * Address is always specified.
1056 */
1057 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 1058 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 1059 if (alen > 3)
4c12eeb8 1060 return CMD_RET_USAGE;
63656b76
SG
1061#ifdef CONFIG_DM_I2C
1062 ret = i2c_get_cur_bus_chip(chip, &dev);
1063 if (!ret && alen != -1)
1064 ret = i2c_set_chip_offset_len(dev, alen);
1065 if (ret)
1066 return i2c_report_err(ret, I2C_ERR_WRITE);
1067#endif
81a8824f
WD
1068
1069 /*
1070 * Length is the number of objects, not number of bytes.
1071 */
1072 length = 1;
1073 length = simple_strtoul(argv[3], NULL, 16);
e857a5bd 1074 if (length > sizeof(bytes))
81a8824f 1075 length = sizeof(bytes);
81a8824f
WD
1076
1077 /*
1078 * The delay time (uSec) is optional.
1079 */
1080 delay = 1000;
e857a5bd 1081 if (argc > 3)
81a8824f 1082 delay = simple_strtoul(argv[4], NULL, 10);
81a8824f
WD
1083 /*
1084 * Run the loop...
1085 */
e857a5bd 1086 while (1) {
63656b76 1087#ifdef CONFIG_DM_I2C
f9a4c2da 1088 ret = dm_i2c_read(dev, addr, bytes, length);
63656b76
SG
1089#else
1090 ret = i2c_read(chip, addr, alen, bytes, length);
1091#endif
1092 if (ret)
1093 i2c_report_err(ret, I2C_ERR_READ);
81a8824f
WD
1094 udelay(delay);
1095 }
1096
1097 /* NOTREACHED */
1098 return 0;
1099}
1100
81a8824f
WD
1101/*
1102 * The SDRAM command is separately configured because many
1103 * (most?) embedded boards don't use SDRAM DIMMs.
06afa388
MV
1104 *
1105 * FIXME: Document and probably move elsewhere!
81a8824f 1106 */
c76fe474 1107#if defined(CONFIG_CMD_SDRAM)
632de067
LJ
1108static void print_ddr2_tcyc (u_char const b)
1109{
1110 printf ("%d.", (b >> 4) & 0x0F);
1111 switch (b & 0x0F) {
1112 case 0x0:
1113 case 0x1:
1114 case 0x2:
1115 case 0x3:
1116 case 0x4:
1117 case 0x5:
1118 case 0x6:
1119 case 0x7:
1120 case 0x8:
1121 case 0x9:
1122 printf ("%d ns\n", b & 0x0F);
1123 break;
1124 case 0xA:
1125 puts ("25 ns\n");
1126 break;
1127 case 0xB:
1128 puts ("33 ns\n");
1129 break;
1130 case 0xC:
1131 puts ("66 ns\n");
1132 break;
1133 case 0xD:
1134 puts ("75 ns\n");
1135 break;
1136 default:
1137 puts ("?? ns\n");
1138 break;
1139 }
1140}
1141
1142static void decode_bits (u_char const b, char const *str[], int const do_once)
1143{
1144 u_char mask;
1145
1146 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
1147 if (b & mask) {
1148 puts (*str);
1149 if (do_once)
1150 return;
1151 }
1152 }
1153}
81a8824f
WD
1154
1155/*
1156 * Syntax:
0f89c54b 1157 * i2c sdram {i2c_chip}
81a8824f 1158 */
09140113
SG
1159static int do_sdram(struct cmd_tbl *cmdtp, int flag, int argc,
1160 char *const argv[])
81a8824f 1161{
18c4e7f7 1162 enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type;
632de067 1163
5468461d 1164 uint chip;
81a8824f
WD
1165 u_char data[128];
1166 u_char cksum;
28df8ed0
NI
1167 int j, ret;
1168#ifdef CONFIG_DM_I2C
1169 struct udevice *dev;
1170#endif
81a8824f 1171
632de067
LJ
1172 static const char *decode_CAS_DDR2[] = {
1173 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
1174 };
1175
1176 static const char *decode_CAS_default[] = {
1177 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
1178 };
1179
1180 static const char *decode_CS_WE_default[] = {
1181 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
1182 };
1183
1184 static const char *decode_byte21_default[] = {
1185 " TBD (bit 7)\n",
1186 " Redundant row address\n",
1187 " Differential clock input\n",
1188 " Registerd DQMB inputs\n",
1189 " Buffered DQMB inputs\n",
1190 " On-card PLL\n",
1191 " Registered address/control lines\n",
1192 " Buffered address/control lines\n"
1193 };
1194
1195 static const char *decode_byte22_DDR2[] = {
1196 " TBD (bit 7)\n",
1197 " TBD (bit 6)\n",
1198 " TBD (bit 5)\n",
1199 " TBD (bit 4)\n",
1200 " TBD (bit 3)\n",
1201 " Supports partial array self refresh\n",
1202 " Supports 50 ohm ODT\n",
1203 " Supports weak driver\n"
1204 };
1205
1206 static const char *decode_row_density_DDR2[] = {
1207 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
1208 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
1209 };
1210
1211 static const char *decode_row_density_default[] = {
1212 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
1213 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
1214 };
1215
47e26b1b 1216 if (argc < 2)
4c12eeb8 1217 return CMD_RET_USAGE;
47e26b1b 1218
81a8824f
WD
1219 /*
1220 * Chip is always specified.
632de067
LJ
1221 */
1222 chip = simple_strtoul (argv[1], NULL, 16);
81a8824f 1223
28df8ed0
NI
1224#ifdef CONFIG_DM_I2C
1225 ret = i2c_get_cur_bus_chip(chip, &dev);
1226 if (!ret)
1227 ret = dm_i2c_read(dev, 0, data, sizeof(data));
1228#else
1229 ret = i2c_read(chip, 0, 1, data, sizeof(data));
1230#endif
1231 if (ret) {
4b9206ed 1232 puts ("No SDRAM Serial Presence Detect found.\n");
81a8824f
WD
1233 return 1;
1234 }
1235
1236 cksum = 0;
1237 for (j = 0; j < 63; j++) {
1238 cksum += data[j];
1239 }
e857a5bd 1240 if (cksum != data[63]) {
81a8824f 1241 printf ("WARNING: Configuration data checksum failure:\n"
632de067 1242 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
81a8824f 1243 }
632de067 1244 printf ("SPD data revision %d.%d\n",
81a8824f 1245 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
632de067
LJ
1246 printf ("Bytes used 0x%02X\n", data[0]);
1247 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
1248
4b9206ed 1249 puts ("Memory type ");
632de067 1250 switch (data[2]) {
0df6b844
LJ
1251 case 2:
1252 type = EDO;
1253 puts ("EDO\n");
1254 break;
1255 case 4:
1256 type = SDRAM;
1257 puts ("SDRAM\n");
1258 break;
18c4e7f7
MS
1259 case 7:
1260 type = DDR;
1261 puts("DDR\n");
1262 break;
0df6b844
LJ
1263 case 8:
1264 type = DDR2;
1265 puts ("DDR2\n");
1266 break;
18c4e7f7
MS
1267 case 11:
1268 type = DDR3;
1269 puts("DDR3\n");
1270 break;
1271 case 12:
1272 type = DDR4;
1273 puts("DDR4\n");
1274 break;
0df6b844
LJ
1275 default:
1276 type = unknown;
1277 puts ("unknown\n");
1278 break;
81a8824f 1279 }
632de067 1280
4b9206ed 1281 puts ("Row address bits ");
e857a5bd 1282 if ((data[3] & 0x00F0) == 0)
632de067 1283 printf ("%d\n", data[3] & 0x0F);
e857a5bd 1284 else
632de067
LJ
1285 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
1286
4b9206ed 1287 puts ("Column address bits ");
e857a5bd 1288 if ((data[4] & 0x00F0) == 0)
632de067 1289 printf ("%d\n", data[4] & 0x0F);
e857a5bd 1290 else
632de067 1291 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
0df6b844
LJ
1292
1293 switch (type) {
1294 case DDR2:
632de067
LJ
1295 printf ("Number of ranks %d\n",
1296 (data[5] & 0x07) + 1);
0df6b844
LJ
1297 break;
1298 default:
632de067 1299 printf ("Module rows %d\n", data[5]);
0df6b844
LJ
1300 break;
1301 }
1302
1303 switch (type) {
1304 case DDR2:
632de067 1305 printf ("Module data width %d bits\n", data[6]);
0df6b844
LJ
1306 break;
1307 default:
632de067
LJ
1308 printf ("Module data width %d bits\n",
1309 (data[7] << 8) | data[6]);
0df6b844
LJ
1310 break;
1311 }
1312
4b9206ed 1313 puts ("Interface signal levels ");
81a8824f 1314 switch(data[8]) {
0df6b844 1315 case 0: puts ("TTL 5.0 V\n"); break;
4b9206ed 1316 case 1: puts ("LVTTL\n"); break;
0df6b844
LJ
1317 case 2: puts ("HSTL 1.5 V\n"); break;
1318 case 3: puts ("SSTL 3.3 V\n"); break;
1319 case 4: puts ("SSTL 2.5 V\n"); break;
1320 case 5: puts ("SSTL 1.8 V\n"); break;
4b9206ed 1321 default: puts ("unknown\n"); break;
81a8824f 1322 }
0df6b844
LJ
1323
1324 switch (type) {
1325 case DDR2:
632de067
LJ
1326 printf ("SDRAM cycle time ");
1327 print_ddr2_tcyc (data[9]);
0df6b844
LJ
1328 break;
1329 default:
632de067
LJ
1330 printf ("SDRAM cycle time %d.%d ns\n",
1331 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
0df6b844
LJ
1332 break;
1333 }
1334
1335 switch (type) {
1336 case DDR2:
632de067
LJ
1337 printf ("SDRAM access time 0.%d%d ns\n",
1338 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1339 break;
1340 default:
632de067
LJ
1341 printf ("SDRAM access time %d.%d ns\n",
1342 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1343 break;
1344 }
1345
4b9206ed 1346 puts ("EDC configuration ");
632de067 1347 switch (data[11]) {
4b9206ed
WD
1348 case 0: puts ("None\n"); break;
1349 case 1: puts ("Parity\n"); break;
1350 case 2: puts ("ECC\n"); break;
1351 default: puts ("unknown\n"); break;
81a8824f 1352 }
632de067 1353
e857a5bd 1354 if ((data[12] & 0x80) == 0)
4b9206ed 1355 puts ("No self refresh, rate ");
e857a5bd 1356 else
4b9206ed 1357 puts ("Self refresh, rate ");
632de067 1358
81a8824f 1359 switch(data[12] & 0x7F) {
632de067
LJ
1360 case 0: puts ("15.625 us\n"); break;
1361 case 1: puts ("3.9 us\n"); break;
1362 case 2: puts ("7.8 us\n"); break;
1363 case 3: puts ("31.3 us\n"); break;
1364 case 4: puts ("62.5 us\n"); break;
1365 case 5: puts ("125 us\n"); break;
4b9206ed 1366 default: puts ("unknown\n"); break;
81a8824f 1367 }
0df6b844
LJ
1368
1369 switch (type) {
1370 case DDR2:
632de067 1371 printf ("SDRAM width (primary) %d\n", data[13]);
0df6b844
LJ
1372 break;
1373 default:
632de067 1374 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
0df6b844 1375 if ((data[13] & 0x80) != 0) {
632de067
LJ
1376 printf (" (second bank) %d\n",
1377 2 * (data[13] & 0x7F));
0df6b844
LJ
1378 }
1379 break;
1380 }
1381
1382 switch (type) {
1383 case DDR2:
1384 if (data[14] != 0)
632de067 1385 printf ("EDC width %d\n", data[14]);
0df6b844
LJ
1386 break;
1387 default:
1388 if (data[14] != 0) {
632de067
LJ
1389 printf ("EDC width %d\n",
1390 data[14] & 0x7F);
0df6b844
LJ
1391
1392 if ((data[14] & 0x80) != 0) {
632de067
LJ
1393 printf (" (second bank) %d\n",
1394 2 * (data[14] & 0x7F));
0df6b844
LJ
1395 }
1396 }
1397 break;
81a8824f 1398 }
0df6b844 1399
632de067
LJ
1400 if (DDR2 != type) {
1401 printf ("Min clock delay, back-to-back random column addresses "
1402 "%d\n", data[15]);
0df6b844
LJ
1403 }
1404
4b9206ed
WD
1405 puts ("Burst length(s) ");
1406 if (data[16] & 0x80) puts (" Page");
1407 if (data[16] & 0x08) puts (" 8");
1408 if (data[16] & 0x04) puts (" 4");
1409 if (data[16] & 0x02) puts (" 2");
1410 if (data[16] & 0x01) puts (" 1");
1411 putc ('\n');
632de067 1412 printf ("Number of banks %d\n", data[17]);
0df6b844
LJ
1413
1414 switch (type) {
1415 case DDR2:
1416 puts ("CAS latency(s) ");
632de067 1417 decode_bits (data[18], decode_CAS_DDR2, 0);
0df6b844
LJ
1418 putc ('\n');
1419 break;
1420 default:
1421 puts ("CAS latency(s) ");
632de067 1422 decode_bits (data[18], decode_CAS_default, 0);
0df6b844
LJ
1423 putc ('\n');
1424 break;
1425 }
1426
1427 if (DDR2 != type) {
1428 puts ("CS latency(s) ");
632de067 1429 decode_bits (data[19], decode_CS_WE_default, 0);
0df6b844
LJ
1430 putc ('\n');
1431 }
1432
1433 if (DDR2 != type) {
1434 puts ("WE latency(s) ");
632de067 1435 decode_bits (data[20], decode_CS_WE_default, 0);
0df6b844
LJ
1436 putc ('\n');
1437 }
1438
1439 switch (type) {
1440 case DDR2:
1441 puts ("Module attributes:\n");
1442 if (data[21] & 0x80)
1443 puts (" TBD (bit 7)\n");
1444 if (data[21] & 0x40)
1445 puts (" Analysis probe installed\n");
1446 if (data[21] & 0x20)
1447 puts (" TBD (bit 5)\n");
1448 if (data[21] & 0x10)
1449 puts (" FET switch external enable\n");
632de067 1450 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
0df6b844 1451 if (data[20] & 0x11) {
632de067
LJ
1452 printf (" %d active registers on DIMM\n",
1453 (data[21] & 0x03) + 1);
0df6b844
LJ
1454 }
1455 break;
1456 default:
1457 puts ("Module attributes:\n");
1458 if (!data[21])
1459 puts (" (none)\n");
632de067
LJ
1460 else
1461 decode_bits (data[21], decode_byte21_default, 0);
0df6b844
LJ
1462 break;
1463 }
1464
1465 switch (type) {
1466 case DDR2:
632de067 1467 decode_bits (data[22], decode_byte22_DDR2, 0);
0df6b844
LJ
1468 break;
1469 default:
1470 puts ("Device attributes:\n");
1471 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1472 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1473 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1474 else puts (" Upper Vcc tolerance 10%\n");
1475 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1476 else puts (" Lower Vcc tolerance 10%\n");
1477 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1478 if (data[22] & 0x04) puts (" Supports precharge all\n");
1479 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1480 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1481 break;
1482 }
1483
1484 switch (type) {
1485 case DDR2:
632de067
LJ
1486 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1487 print_ddr2_tcyc (data[23]);
0df6b844
LJ
1488 break;
1489 default:
632de067
LJ
1490 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1491 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
0df6b844
LJ
1492 break;
1493 }
1494
1495 switch (type) {
1496 case DDR2:
632de067
LJ
1497 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1498 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1499 break;
1500 default:
632de067
LJ
1501 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1502 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1503 break;
1504 }
1505
1506 switch (type) {
1507 case DDR2:
632de067
LJ
1508 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1509 print_ddr2_tcyc (data[25]);
0df6b844
LJ
1510 break;
1511 default:
632de067
LJ
1512 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1513 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
0df6b844
LJ
1514 break;
1515 }
1516
1517 switch (type) {
1518 case DDR2:
632de067
LJ
1519 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1520 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1521 break;
1522 default:
632de067
LJ
1523 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1524 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1525 break;
1526 }
1527
1528 switch (type) {
1529 case DDR2:
632de067
LJ
1530 printf ("Minimum row precharge %d.%02d ns\n",
1531 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
0df6b844
LJ
1532 break;
1533 default:
632de067 1534 printf ("Minimum row precharge %d ns\n", data[27]);
0df6b844
LJ
1535 break;
1536 }
1537
1538 switch (type) {
1539 case DDR2:
632de067
LJ
1540 printf ("Row active to row active min %d.%02d ns\n",
1541 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
0df6b844
LJ
1542 break;
1543 default:
632de067 1544 printf ("Row active to row active min %d ns\n", data[28]);
0df6b844
LJ
1545 break;
1546 }
1547
1548 switch (type) {
1549 case DDR2:
632de067
LJ
1550 printf ("RAS to CAS delay min %d.%02d ns\n",
1551 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
0df6b844
LJ
1552 break;
1553 default:
632de067 1554 printf ("RAS to CAS delay min %d ns\n", data[29]);
0df6b844
LJ
1555 break;
1556 }
1557
632de067 1558 printf ("Minimum RAS pulse width %d ns\n", data[30]);
0df6b844
LJ
1559
1560 switch (type) {
1561 case DDR2:
632de067
LJ
1562 puts ("Density of each row ");
1563 decode_bits (data[31], decode_row_density_DDR2, 1);
1564 putc ('\n');
0df6b844
LJ
1565 break;
1566 default:
632de067
LJ
1567 puts ("Density of each row ");
1568 decode_bits (data[31], decode_row_density_default, 1);
1569 putc ('\n');
0df6b844
LJ
1570 break;
1571 }
1572
1573 switch (type) {
1574 case DDR2:
632de067 1575 puts ("Command and Address setup ");
0df6b844 1576 if (data[32] >= 0xA0) {
632de067
LJ
1577 printf ("1.%d%d ns\n",
1578 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
0df6b844 1579 } else {
632de067
LJ
1580 printf ("0.%d%d ns\n",
1581 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
0df6b844
LJ
1582 }
1583 break;
1584 default:
632de067
LJ
1585 printf ("Command and Address setup %c%d.%d ns\n",
1586 (data[32] & 0x80) ? '-' : '+',
1587 (data[32] >> 4) & 0x07, data[32] & 0x0F);
0df6b844
LJ
1588 break;
1589 }
1590
1591 switch (type) {
1592 case DDR2:
632de067 1593 puts ("Command and Address hold ");
0df6b844 1594 if (data[33] >= 0xA0) {
632de067
LJ
1595 printf ("1.%d%d ns\n",
1596 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
0df6b844 1597 } else {
632de067
LJ
1598 printf ("0.%d%d ns\n",
1599 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
0df6b844
LJ
1600 }
1601 break;
1602 default:
632de067
LJ
1603 printf ("Command and Address hold %c%d.%d ns\n",
1604 (data[33] & 0x80) ? '-' : '+',
1605 (data[33] >> 4) & 0x07, data[33] & 0x0F);
0df6b844
LJ
1606 break;
1607 }
1608
1609 switch (type) {
1610 case DDR2:
632de067
LJ
1611 printf ("Data signal input setup 0.%d%d ns\n",
1612 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
0df6b844
LJ
1613 break;
1614 default:
632de067
LJ
1615 printf ("Data signal input setup %c%d.%d ns\n",
1616 (data[34] & 0x80) ? '-' : '+',
1617 (data[34] >> 4) & 0x07, data[34] & 0x0F);
0df6b844
LJ
1618 break;
1619 }
1620
1621 switch (type) {
1622 case DDR2:
632de067
LJ
1623 printf ("Data signal input hold 0.%d%d ns\n",
1624 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
0df6b844
LJ
1625 break;
1626 default:
632de067
LJ
1627 printf ("Data signal input hold %c%d.%d ns\n",
1628 (data[35] & 0x80) ? '-' : '+',
1629 (data[35] >> 4) & 0x07, data[35] & 0x0F);
0df6b844
LJ
1630 break;
1631 }
1632
4b9206ed 1633 puts ("Manufacturer's JEDEC ID ");
e857a5bd 1634 for (j = 64; j <= 71; j++)
632de067 1635 printf ("%02X ", data[j]);
4b9206ed 1636 putc ('\n');
632de067 1637 printf ("Manufacturing Location %02X\n", data[72]);
4b9206ed 1638 puts ("Manufacturer's Part Number ");
e857a5bd 1639 for (j = 73; j <= 90; j++)
632de067 1640 printf ("%02X ", data[j]);
4b9206ed 1641 putc ('\n');
632de067
LJ
1642 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1643 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
4b9206ed 1644 puts ("Assembly Serial Number ");
e857a5bd 1645 for (j = 95; j <= 98; j++)
632de067 1646 printf ("%02X ", data[j]);
4b9206ed 1647 putc ('\n');
81a8824f 1648
0df6b844 1649 if (DDR2 != type) {
632de067
LJ
1650 printf ("Speed rating PC%d\n",
1651 data[126] == 0x66 ? 66 : data[126]);
0df6b844 1652 }
81a8824f
WD
1653 return 0;
1654}
90253178 1655#endif
81a8824f 1656
735987c5
TWHT
1657/*
1658 * Syntax:
1659 * i2c edid {i2c_chip}
1660 */
1661#if defined(CONFIG_I2C_EDID)
09140113 1662int do_edid(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
735987c5 1663{
5468461d 1664 uint chip;
735987c5 1665 struct edid1_info edid;
63656b76
SG
1666 int ret;
1667#ifdef CONFIG_DM_I2C
1668 struct udevice *dev;
1669#endif
735987c5
TWHT
1670
1671 if (argc < 2) {
1672 cmd_usage(cmdtp);
1673 return 1;
1674 }
1675
1676 chip = simple_strtoul(argv[1], NULL, 16);
63656b76
SG
1677#ifdef CONFIG_DM_I2C
1678 ret = i2c_get_cur_bus_chip(chip, &dev);
1679 if (!ret)
f9a4c2da 1680 ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
63656b76
SG
1681#else
1682 ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
1683#endif
1684 if (ret)
1685 return i2c_report_err(ret, I2C_ERR_READ);
735987c5
TWHT
1686
1687 if (edid_check_info(&edid)) {
1688 puts("Content isn't valid EDID.\n");
1689 return 1;
1690 }
1691
1692 edid_print_info(&edid);
1693 return 0;
1694
1695}
1696#endif /* CONFIG_I2C_EDID */
1697
59aa9df3
SG
1698#ifdef CONFIG_DM_I2C
1699static void show_bus(struct udevice *bus)
1700{
1701 struct udevice *dev;
1702
1703 printf("Bus %d:\t%s", bus->req_seq, bus->name);
1704 if (device_active(bus))
1705 printf(" (active %d)", bus->seq);
1706 printf("\n");
1707 for (device_find_first_child(bus, &dev);
1708 dev;
1709 device_find_next_child(&dev)) {
1710 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
1711
1712 printf(" %02x: %s, offset len %x, flags %x\n",
1713 chip->chip_addr, dev->name, chip->offset_len,
1714 chip->flags);
1715 }
1716}
1717#endif
1718
06afa388 1719/**
3f4978c7 1720 * do_i2c_show_bus() - Handle the "i2c bus" command-line command
06afa388
MV
1721 * @cmdtp: Command data struct pointer
1722 * @flag: Command flag
1723 * @argc: Command-line argument count
1724 * @argv: Array of command-line arguments
1725 *
1726 * Returns zero always.
1727 */
59aa9df3 1728#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
09140113
SG
1729static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
1730 char *const argv[])
67b23a32 1731{
67b23a32
HS
1732 if (argc == 1) {
1733 /* show all busses */
59aa9df3
SG
1734#ifdef CONFIG_DM_I2C
1735 struct udevice *bus;
1736 struct uclass *uc;
1737 int ret;
1738
1739 ret = uclass_get(UCLASS_I2C, &uc);
1740 if (ret)
1741 return CMD_RET_FAILURE;
1742 uclass_foreach_dev(bus, uc)
1743 show_bus(bus);
1744#else
1745 int i;
1746
3f4978c7
HS
1747 for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
1748 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1749#ifndef CONFIG_SYS_I2C_DIRECT_BUS
59aa9df3
SG
1750 int j;
1751
3f4978c7
HS
1752 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1753 if (i2c_bus[i].next_hop[j].chip == 0)
1754 break;
1755 printf("->%s@0x%2x:%d",
1756 i2c_bus[i].next_hop[j].mux.name,
1757 i2c_bus[i].next_hop[j].chip,
1758 i2c_bus[i].next_hop[j].channel);
67b23a32 1759 }
3f4978c7
HS
1760#endif
1761 printf("\n");
67b23a32 1762 }
59aa9df3 1763#endif
67b23a32 1764 } else {
59aa9df3
SG
1765 int i;
1766
3f4978c7
HS
1767 /* show specific bus */
1768 i = simple_strtoul(argv[1], NULL, 10);
59aa9df3
SG
1769#ifdef CONFIG_DM_I2C
1770 struct udevice *bus;
1771 int ret;
1772
1773 ret = uclass_get_device_by_seq(UCLASS_I2C, i, &bus);
1774 if (ret) {
1775 printf("Invalid bus %d: err=%d\n", i, ret);
1776 return CMD_RET_FAILURE;
1777 }
1778 show_bus(bus);
1779#else
3f4978c7
HS
1780 if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
1781 printf("Invalid bus %d\n", i);
1782 return -1;
1783 }
1784 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1785#ifndef CONFIG_SYS_I2C_DIRECT_BUS
59aa9df3 1786 int j;
3f4978c7
HS
1787 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1788 if (i2c_bus[i].next_hop[j].chip == 0)
1789 break;
1790 printf("->%s@0x%2x:%d",
1791 i2c_bus[i].next_hop[j].mux.name,
1792 i2c_bus[i].next_hop[j].chip,
1793 i2c_bus[i].next_hop[j].channel);
1794 }
1795#endif
1796 printf("\n");
59aa9df3 1797#endif
67b23a32 1798 }
3f4978c7
HS
1799
1800 return 0;
67b23a32 1801}
3f4978c7 1802#endif
67b23a32 1803
06afa388
MV
1804/**
1805 * do_i2c_bus_num() - Handle the "i2c dev" command-line command
1806 * @cmdtp: Command data struct pointer
1807 * @flag: Command flag
1808 * @argc: Command-line argument count
1809 * @argv: Array of command-line arguments
1810 *
1811 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1812 * on error.
1813 */
63656b76
SG
1814#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
1815 defined(CONFIG_DM_I2C)
09140113
SG
1816static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,
1817 char *const argv[])
bb99ad6d 1818{
3f4978c7 1819 int ret = 0;
63656b76 1820 int bus_no;
bb99ad6d 1821
63656b76 1822 if (argc == 1) {
e857a5bd 1823 /* querying current setting */
63656b76
SG
1824#ifdef CONFIG_DM_I2C
1825 struct udevice *bus;
1826
1827 if (!i2c_get_cur_bus(&bus))
1828 bus_no = bus->seq;
1829 else
1830 bus_no = -1;
1831#else
1832 bus_no = i2c_get_bus_num();
1833#endif
1834 printf("Current bus is %d\n", bus_no);
1835 } else {
3f4978c7 1836 bus_no = simple_strtoul(argv[1], NULL, 10);
880a4127 1837#if defined(CONFIG_SYS_I2C)
3f4978c7
HS
1838 if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
1839 printf("Invalid bus %d\n", bus_no);
1840 return -1;
1841 }
880a4127 1842#endif
3f4978c7 1843 printf("Setting bus to %d\n", bus_no);
f9a4c2da
SG
1844#ifdef CONFIG_DM_I2C
1845 ret = cmd_i2c_set_bus_num(bus_no);
1846#else
3f4978c7 1847 ret = i2c_set_bus_num(bus_no);
f9a4c2da 1848#endif
e857a5bd 1849 if (ret)
bb99ad6d 1850 printf("Failure changing bus number (%d)\n", ret);
bb99ad6d 1851 }
4fbd258e
SG
1852
1853 return ret ? CMD_RET_FAILURE : 0;
bb99ad6d 1854}
3f4978c7 1855#endif /* defined(CONFIG_SYS_I2C) */
bb99ad6d 1856
06afa388
MV
1857/**
1858 * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
1859 * @cmdtp: Command data struct pointer
1860 * @flag: Command flag
1861 * @argc: Command-line argument count
1862 * @argv: Array of command-line arguments
1863 *
1864 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1865 * on error.
1866 */
09140113
SG
1867static int do_i2c_bus_speed(struct cmd_tbl *cmdtp, int flag, int argc,
1868 char *const argv[])
bb99ad6d
BW
1869{
1870 int speed, ret=0;
1871
63656b76
SG
1872#ifdef CONFIG_DM_I2C
1873 struct udevice *bus;
1874
1875 if (i2c_get_cur_bus(&bus))
1876 return 1;
1877#endif
1878 if (argc == 1) {
1879#ifdef CONFIG_DM_I2C
ca88b9b9 1880 speed = dm_i2c_get_bus_speed(bus);
63656b76
SG
1881#else
1882 speed = i2c_get_bus_speed();
1883#endif
e857a5bd 1884 /* querying current speed */
63656b76
SG
1885 printf("Current bus speed=%d\n", speed);
1886 } else {
bb99ad6d
BW
1887 speed = simple_strtoul(argv[1], NULL, 10);
1888 printf("Setting bus speed to %d Hz\n", speed);
63656b76 1889#ifdef CONFIG_DM_I2C
ca88b9b9 1890 ret = dm_i2c_set_bus_speed(bus, speed);
63656b76 1891#else
bb99ad6d 1892 ret = i2c_set_bus_speed(speed);
63656b76 1893#endif
e857a5bd 1894 if (ret)
bb99ad6d 1895 printf("Failure changing bus speed (%d)\n", ret);
bb99ad6d 1896 }
4fbd258e
SG
1897
1898 return ret ? CMD_RET_FAILURE : 0;
bb99ad6d
BW
1899}
1900
06afa388
MV
1901/**
1902 * do_i2c_mm() - Handle the "i2c mm" command-line command
1903 * @cmdtp: Command data struct pointer
1904 * @flag: Command flag
1905 * @argc: Command-line argument count
1906 * @argv: Array of command-line arguments
1907 *
1908 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1909 * on error.
1910 */
09140113
SG
1911static int do_i2c_mm(struct cmd_tbl *cmdtp, int flag, int argc,
1912 char *const argv[])
bb99ad6d 1913{
bfc3b77e
FM
1914 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1915}
1916
06afa388
MV
1917/**
1918 * do_i2c_nm() - Handle the "i2c nm" command-line command
1919 * @cmdtp: Command data struct pointer
1920 * @flag: Command flag
1921 * @argc: Command-line argument count
1922 * @argv: Array of command-line arguments
1923 *
1924 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1925 * on error.
1926 */
09140113
SG
1927static int do_i2c_nm(struct cmd_tbl *cmdtp, int flag, int argc,
1928 char *const argv[])
bfc3b77e
FM
1929{
1930 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1931}
e96ad5d3 1932
06afa388
MV
1933/**
1934 * do_i2c_reset() - Handle the "i2c reset" command-line command
1935 * @cmdtp: Command data struct pointer
1936 * @flag: Command flag
1937 * @argc: Command-line argument count
1938 * @argv: Array of command-line arguments
1939 *
1940 * Returns zero always.
1941 */
09140113
SG
1942static int do_i2c_reset(struct cmd_tbl *cmdtp, int flag, int argc,
1943 char *const argv[])
bfc3b77e 1944{
63656b76
SG
1945#if defined(CONFIG_DM_I2C)
1946 struct udevice *bus;
1947
1948 if (i2c_get_cur_bus(&bus))
1949 return CMD_RET_FAILURE;
1950 if (i2c_deblock(bus)) {
1951 printf("Error: Not supported by the driver\n");
1952 return CMD_RET_FAILURE;
1953 }
1954#elif defined(CONFIG_SYS_I2C)
3f4978c7
HS
1955 i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
1956#else
bfc3b77e 1957 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3f4978c7 1958#endif
bfc3b77e
FM
1959 return 0;
1960}
1961
09140113 1962static struct cmd_tbl cmd_i2c_sub[] = {
59aa9df3 1963#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
3f4978c7 1964 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
9a2accb4 1965#endif
bfc3b77e 1966 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
3f4978c7 1967#if defined(CONFIG_SYS_I2C) || \
63656b76 1968 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
bfc3b77e 1969 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
bb99ad6d 1970#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
1971#if defined(CONFIG_I2C_EDID)
1972 U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
1973#endif /* CONFIG_I2C_EDID */
bfc3b77e
FM
1974 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1975 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1976 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1977 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1978 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1979 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
652e5354 1980 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
ed16f146 1981 U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
63656b76
SG
1982#ifdef CONFIG_DM_I2C
1983 U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
c10c8e31 1984 U_BOOT_CMD_MKENT(olen, 2, 1, do_i2c_olen, "", ""),
63656b76 1985#endif
bfc3b77e 1986 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
c76fe474 1987#if defined(CONFIG_CMD_SDRAM)
bfc3b77e 1988 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
90253178 1989#endif
bfc3b77e
FM
1990 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1991};
1992
e4099c8b
MS
1993static __maybe_unused void i2c_reloc(void)
1994{
1995 static int relocated;
1996
1997 if (!relocated) {
1998 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1999 relocated = 1;
2000 };
f1d2b313 2001}
f1d2b313 2002
06afa388
MV
2003/**
2004 * do_i2c() - Handle the "i2c" command-line command
2005 * @cmdtp: Command data struct pointer
2006 * @flag: Command flag
2007 * @argc: Command-line argument count
2008 * @argv: Array of command-line arguments
2009 *
2010 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
2011 * on error.
2012 */
09140113 2013static int do_i2c(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
bfc3b77e 2014{
09140113 2015 struct cmd_tbl *c;
bfc3b77e 2016
e4099c8b
MS
2017#ifdef CONFIG_NEEDS_MANUAL_RELOC
2018 i2c_reloc();
2019#endif
2020
4444b221 2021 if (argc < 2)
4c12eeb8 2022 return CMD_RET_USAGE;
4444b221 2023
bfc3b77e
FM
2024 /* Strip off leading 'i2c' command argument */
2025 argc--;
2026 argv++;
2027
2028 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
2029
47e26b1b 2030 if (c)
4c12eeb8 2031 return c->cmd(cmdtp, flag, argc, argv);
47e26b1b 2032 else
4c12eeb8 2033 return CMD_RET_USAGE;
bb99ad6d 2034}
8bde7f77
WD
2035
2036/***************************************************/
088f1b19
KP
2037#ifdef CONFIG_SYS_LONGHELP
2038static char i2c_help_text[] =
59aa9df3 2039#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
3f4978c7 2040 "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
19f8c4df 2041 "i2c " /* That's the prefix for the crc32 command below. */
9a2accb4 2042#endif
fb0070e9 2043 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
3f4978c7 2044#if defined(CONFIG_SYS_I2C) || \
63656b76 2045 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
9bc2e4ee 2046 "i2c dev [dev] - show or set current I2C bus\n"
d9fc7032 2047#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
2048#if defined(CONFIG_I2C_EDID)
2049 "i2c edid chip - print EDID configuration information\n"
2050#endif /* CONFIG_I2C_EDID */
fb0070e9 2051 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
d9fc7032
MF
2052 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
2053 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
2054 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
2055 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
54b99e51 2056 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
63656b76 2057 "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
ed16f146
LP
2058 "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
2059 " to I2C; the -s option selects bulk write in a single transaction\n"
63656b76
SG
2060#ifdef CONFIG_DM_I2C
2061 "i2c flags chip [flags] - set or get chip flags\n"
c10c8e31 2062 "i2c olen chip [offset_length] - set or get chip offset length\n"
63656b76 2063#endif
e43a27c4 2064 "i2c reset - re-init the I2C Controller\n"
c76fe474 2065#if defined(CONFIG_CMD_SDRAM)
fb0070e9 2066 "i2c sdram chip - print SDRAM configuration information\n"
90253178 2067#endif
088f1b19
KP
2068 "i2c speed [speed] - show or set I2C bus speed";
2069#endif
2070
2071U_BOOT_CMD(
ed16f146 2072 i2c, 7, 1, do_i2c,
088f1b19
KP
2073 "I2C sub-system",
2074 i2c_help_text
d9fc7032 2075);
This page took 0.813588 seconds and 4 git commands to generate.