[J-u-boot.git] / include / configs / M54451EVB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the Freescale MCF54451 EVB board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54451EVB_H
#define _M54451EVB_H

#include <linux/stringify.h>

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M54451EVB	/* M54451EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#define LDS_BOARD_TEXT                  board/freescale/m54451evb/sbf_dram_init.o (.text*)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/* Network configuration */
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		"M54451EVB"
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#else
#define CONFIG_SYS_UBOOT_END	0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)	\
	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE		0x7

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM			2048	/* 2048 KB */

#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR			0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
#define CONFIG_SYS_SDRAM_CFG2		0x57670000
#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
#define CONFIG_SYS_SDRAM_EMOD		0x80810000
#define CONFIG_SYS_SDRAM_MODE		0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44

#ifdef CONFIG_CF_SBF
#	define CONFIG_SERIAL_BOOT
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#undef CONFIG_ENV_OVERWRITE

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }

#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 16MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

 /* Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00004D80

#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE

#endif				/* _M54451EVB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
05316f8e TL	2	/*
	3	* Configuation settings for the Freescale MCF54451 EVB board.
	4	*
	5	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	6	* TsiChung Liew ([email protected])
05316f8e TL	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M54451EVB_H
	14	#define _M54451EVB_H
	15
1af3c7f4 SG	16	#include <linux/stringify.h>
1af3c7f4 SG	17
05316f8e TL	18	/*
	19	* High Level Configuration Options
	20	* (easy to change)
	21	*/
05316f8e TL	22	#define CONFIG_M54451EVB /* M54451EVB board */
	23
	24	#define CONFIG_MCFUART
6d0f6bcf	25	#define CONFIG_SYS_UART_PORT (0)
05316f8e	26
c74dda8b AD	27	#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
c74dda8b AD	28
05316f8e TL	29	#undef CONFIG_WATCHDOG
	30
	31	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	32
	33	/*
	34	* BOOTP options
	35	*/
	36	#define CONFIG_BOOTP_BOOTFILESIZE
05316f8e	37
05316f8e	38	/* Network configuration */
05316f8e	39	#ifdef CONFIG_MCFFEC
05316f8e	40	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	41	# define CONFIG_SYS_DISCOVER_PHY
	42	# define CONFIG_SYS_RX_ETH_BUFFER 8
	43	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e TL	44	# define CONFIG_ETHPRIME "FEC0"
	45	# define CONFIG_IPADDR 192.162.1.2
	46	# define CONFIG_NETMASK 255.255.255.0
	47	# define CONFIG_SERVERIP 192.162.1.1
	48	# define CONFIG_GATEWAYIP 192.162.1.1
05316f8e	49
6d0f6bcf JCPV	50	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	51	# ifndef CONFIG_SYS_DISCOVER_PHY
05316f8e TL	52	# define FECDUPLEX FULL
	53	# define FECSPEED _100BASET
	54	# else
6d0f6bcf JCPV	55	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	56	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	57	# endif
6d0f6bcf	58	# endif /* CONFIG_SYS_DISCOVER_PHY */
05316f8e TL	59	#endif
05316f8e TL	60
5bc0543d	61	#define CONFIG_HOSTNAME "M54451EVB"
6d0f6bcf	62	#ifdef CONFIG_SYS_STMICRO_BOOT
05316f8e	63	/* ST Micro serial flash */
6d0f6bcf	64	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
05316f8e TL	65	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	66	"netdev=eth0\0" \
5368c55d	67	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	68	"loadaddr=0x40010000\0" \
	69	"sbfhdr=sbfhdr.bin\0" \
	70	"uboot=u-boot.bin\0" \
	71	"load=tftp ${loadaddr} ${sbfhdr};" \
5368c55d	72	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
05316f8e	73	"upd=run load; run prog\0" \
09933fb0	74	"prog=sf probe 0:1 1000000 3;" \
05316f8e TL	75	"sf erase 0 30000;" \
	76	"sf write ${loadaddr} 0 30000;" \
	77	"save\0" \
	78	""
	79	#else
6d0f6bcf	80	#define CONFIG_SYS_UBOOT_END 0x3FFFF
05316f8e TL	81	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	82	"netdev=eth0\0" \
5368c55d	83	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	84	"loadaddr=40010000\0" \
	85	"u-boot=u-boot.bin\0" \
	86	"load=tftp ${loadaddr) ${u-boot}\0" \
	87	"upd=run load; run prog\0" \
5368c55d MV	88	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
5368c55d MV	89	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
05316f8e TL	90	"cp.b ${loadaddr} 0 ${filesize};" \
	91	"save\0" \
	92	""
	93	#endif
	94
	95	/* Realtime clock */
	96	#define CONFIG_MCFRTC
	97	#undef RTC_DEBUG
6d0f6bcf	98	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
05316f8e TL	99
	100	/* Timer */
	101	#define CONFIG_MCFTMR
05316f8e TL	102
05316f8e TL	103	/* I2c */
00f792e0 HS	104	#define CONFIG_SYS_I2C
	105	#define CONFIG_SYS_I2C_FSL
	106	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	107	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	108	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
709b384b	109	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
05316f8e TL	110
	111	/* DSPI and Serial Flash */
	112	#define CONFIG_CF_DSPI
	113	#define CONFIG_SERIAL_FLASH
6d0f6bcf	114	#define CONFIG_SYS_SBFHDR_SIZE 0x7
05316f8e TL	115
	116	/* Input, PCI, Flexbus, and VCO */
	117	#define CONFIG_EXTRA_CLOCK
	118
709b384b	119	#define CONFIG_PRAM 2048 /* 2048 KB */
05316f8e	120
6d0f6bcf	121	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
05316f8e	122
6d0f6bcf	123	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
05316f8e	124
709b384b	125	#define CONFIG_SYS_MBAR 0xFC000000
05316f8e TL	126
	127	/*
	128	* Low Level Configuration Settings
	129	* (address mappings, register initial values, etc.)
	130	* You should know what you are doing if you make changes here.
	131	*/
	132
	133	/*-----------------------------------------------------------------------
	134	* Definitions for initial stack pointer and data area (in DPRAM)
	135	*/
6d0f6bcf	136	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	137	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	138	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	139	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	140	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	141	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
05316f8e TL	142
	143	/*-----------------------------------------------------------------------
	144	* Start addresses for the final memory configuration
	145	* (Set up by the startup code)
6d0f6bcf	146	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
05316f8e	147	*/
6d0f6bcf JCPV	148	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	149	#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
	150	#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
	151	#define CONFIG_SYS_SDRAM_CFG2 0x57670000
	152	#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
	153	#define CONFIG_SYS_SDRAM_EMOD 0x80810000
	154	#define CONFIG_SYS_SDRAM_MODE 0x008D0000
	155	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
	156
05316f8e	157	#ifdef CONFIG_CF_SBF
09933fb0	158	# define CONFIG_SERIAL_BOOT
14d0a02a	159	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
05316f8e	160	#else
6d0f6bcf	161	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
05316f8e	162	#endif
6d0f6bcf JCPV	163	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	164	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
05316f8e	165
09933fb0 JJ	166	/* Reserve 256 kB for malloc() */
09933fb0 JJ	167	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
05316f8e TL	168	/*
	169	* For booting Linux, the board info and command line data
	170	* have to be in the first 8 MB of memory, since this is
	171	* the maximum mapped by the Linux kernel during initialization ??
	172	*/
	173	/* Initial Memory map for Linux */
6d0f6bcf	174	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
05316f8e TL	175
05316f8e TL	176	/* Configuration for environment
09933fb0 JJ	177	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	178	* crc error warning if there is no correct environment on the flash.
05316f8e	179	*/
05316f8e	180	#undef CONFIG_ENV_OVERWRITE
05316f8e	181
ee0a8462 TL	182	/* FLASH organization */
ee0a8462 TL	183	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
05316f8e	184
6d0f6bcf	185	#ifdef CONFIG_SYS_FLASH_CFI
05316f8e	186
6d0f6bcf JCPV	187	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	188	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	189	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	190	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
6d0f6bcf JCPV	191	# define CONFIG_SYS_FLASH_CHECKSUM
6d0f6bcf JCPV	192	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
05316f8e TL	193
	194	#endif
	195
	196	/*
	197	* This is setting for JFFS2 support in u-boot.
	198	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	199	*/
709b384b	200	#ifdef CONFIG_CMD_JFFS2
05316f8e TL	201	# define CONFIG_JFFS2_DEV "nor0"
05316f8e TL	202	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	203	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
05316f8e TL	204	#endif
05316f8e TL	205
709b384b	206	/* Cache Configuration */
6d0f6bcf	207	#define CONFIG_SYS_CACHELINE_SIZE 16
05316f8e	208
dd9f054e	209	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	210	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	211	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	212	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	213	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	214	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	215	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	216	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	217	CF_ACR_EN \| CF_ACR_SM_ALL)
	218	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	219	CF_CACR_ICINVA \| CF_CACR_EUSP)
	220	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	221	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	222	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	223
05316f8e TL	224	/*-----------------------------------------------------------------------
	225	* Memory bank definitions
	226	*/
	227	/*
709b384b	228	* CS0 - NOR Flash 16MB
05316f8e TL	229	* CS1 - Available
	230	* CS2 - Available
	231	* CS3 - Available
	232	* CS4 - Available
	233	* CS5 - Available
	234	*/
	235
709b384b	236	/* Flash */
6d0f6bcf	237	#define CONFIG_SYS_CS0_BASE 0x00000000
709b384b TL	238	#define CONFIG_SYS_CS0_MASK 0x00FF0001
709b384b TL	239	#define CONFIG_SYS_CS0_CTRL 0x00004D80
05316f8e	240
6d0f6bcf	241	#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
05316f8e TL	242
05316f8e TL	243	#endif /* _M54451EVB_H */