[J-u-boot.git] / include / configs / M5208EVBE.h

/*
 * Configuation settings for the Freescale MCF5208EVBe.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _M5208EVBE_H
#define _M5208EVBE_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF520x		/* define processor family */
#define CONFIG_M5208		/* define processor type */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE			115200

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT		5000

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C			/* I2C with hw support */
#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		80000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5208EVBe
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 3ffff;"		\
	"era 0 3ffff;"				\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_PROMPT	"-> "
#define CONFIG_SYS_LONGHELP	/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
#define CONFIG_SYS_LOAD_ADDR	0x40010000

#define CONFIG_SYS_HZ		1000
#define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
#define CONFIG_SYS_PLL_ODR	0x36
#define CONFIG_SYS_PLL_FDR	0x7D

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
#define CONFIG_SYS_SDRAM_EMOD		0x80010000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER		1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	254	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/*
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		0x2000
#define CONFIG_ENV_SIZE			0x1000
#define CONFIG_ENV_SECT_SIZE		0x2000
#define CONFIG_ENV_IS_IN_FLASH		1

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/* Chipselect bank definitions */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x007F0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0

#endif				/* _M5208EVBE_H */
Commit	Line	Data
bf9a5215 TL	1	/*
	2	* Configuation settings for the Freescale MCF5208EVBe.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew ([email protected])
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef _M5208EVBE_H
	27	#define _M5208EVBE_H
	28
	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
	33	#define CONFIG_MCF520x /* define processor family */
	34	#define CONFIG_M5208 /* define processor type */
	35
	36	#define CONFIG_MCFUART
	37	#define CONFIG_SYS_UART_PORT (0)
	38	#define CONFIG_BAUDRATE 115200
bf9a5215 TL	39
	40	#undef CONFIG_WATCHDOG
	41	#define CONFIG_WATCHDOG_TIMEOUT 5000
	42
	43	/* Command line configuration */
	44	#include <config_cmd_default.h>
	45
	46	#define CONFIG_CMD_CACHE
	47	#define CONFIG_CMD_ELF
	48	#define CONFIG_CMD_FLASH
	49	#undef CONFIG_CMD_I2C
	50	#define CONFIG_CMD_MEMORY
	51	#define CONFIG_CMD_MISC
	52	#define CONFIG_CMD_MII
	53	#define CONFIG_CMD_NET
	54	#define CONFIG_CMD_PING
	55	#define CONFIG_CMD_REGINFO
	56
	57	#define CONFIG_MCFFEC
	58	#ifdef CONFIG_MCFFEC
bf9a5215 TL	59	# define CONFIG_MII 1
	60	# define CONFIG_MII_INIT 1
	61	# define CONFIG_SYS_DISCOVER_PHY
	62	# define CONFIG_SYS_RX_ETH_BUFFER 8
	63	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	64	# define CONFIG_HAS_ETH1
	65
	66	# define CONFIG_SYS_FEC0_PINMUX 0
	67	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	68	# define MCFFEC_TOUT_LOOP 50000
	69	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
	70	# ifndef CONFIG_SYS_DISCOVER_PHY
	71	# define FECDUPLEX FULL
	72	# define FECSPEED _100BASET
	73	# else
	74	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	75	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	76	# endif
	77	# endif /* CONFIG_SYS_DISCOVER_PHY */
	78	#endif
	79
	80	/* Timer */
	81	#define CONFIG_MCFTMR
	82	#undef CONFIG_MCFPIT
	83
	84	/* I2C */
	85	#define CONFIG_FSL_I2C
	86	#define CONFIG_HARD_I2C /* I2C with hw support */
	87	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	88	#define CONFIG_SYS_I2C_SPEED 80000
	89	#define CONFIG_SYS_I2C_SLAVE 0x7F
	90	#define CONFIG_SYS_I2C_OFFSET 0x58000
	91	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	92
	93	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	94	#define CONFIG_UDP_CHECKSUM
	95
	96	#ifdef CONFIG_MCFFEC
	97	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	98	# define CONFIG_IPADDR 192.162.1.2
	99	# define CONFIG_NETMASK 255.255.255.0
	100	# define CONFIG_SERVERIP 192.162.1.1
	101	# define CONFIG_GATEWAYIP 192.162.1.1
	102	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	103	#endif /* CONFIG_MCFFEC */
	104
	105	#define CONFIG_HOSTNAME M5208EVBe
	106	#define CONFIG_EXTRA_ENV_SETTINGS \
	107	"netdev=eth0\0" \
	108	"loadaddr=40010000\0" \
	109	"u-boot=u-boot.bin\0" \
	110	"load=tftp ${loadaddr) ${u-boot}\0" \
	111	"upd=run load; run prog\0" \
	112	"prog=prot off 0 3ffff;" \
	113	"era 0 3ffff;" \
	114	"cp.b ${loadaddr} 0 ${filesize};" \
	115	"save\0" \
	116	""
	117
	118	#define CONFIG_PRAM 512 /* 512 KB */
	119	#define CONFIG_SYS_PROMPT "-> "
	120	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	121
	122	#ifdef CONFIG_CMD_KGDB
123	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
124	#else
125	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126	#endif
127
128	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
129	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
130	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
131	#define CONFIG_SYS_LOAD_ADDR 0x40010000
132
133	#define CONFIG_SYS_HZ 1000
134	#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
135	#define CONFIG_SYS_PLL_ODR 0x36
136	#define CONFIG_SYS_PLL_FDR 0x7D
137
138	#define CONFIG_SYS_MBAR 0xFC000000
139
140	/*
141	* Low Level Configuration Settings
142	* (address mappings, register initial values, etc.)
143	* You should know what you are doing if you make changes here.
144	*/
145	/* Definitions for initial stack pointer and data area (in DPRAM) */
146	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	147	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
bf9a5215	148	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	149	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
bf9a5215 TL	150	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	151
	152	/*
	153	* Start addresses for the final memory configuration
	154	* (Set up by the startup code)
	155	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	156	*/
	157	#define CONFIG_SYS_SDRAM_BASE 0x40000000
f628e2f7	158	#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
bf9a5215 TL	159	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	160	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	161	#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
	162	#define CONFIG_SYS_SDRAM_EMOD 0x80010000
	163	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
	164
	165	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	166	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	167
	168	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	169	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	170
	171	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	172	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	173
	174	/*
	175	* For booting Linux, the board info and command line data
	176	* have to be in the first 8 MB of memory, since this is
	177	* the maximum mapped by the Linux kernel during initialization ??
	178	*/
	179	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
	180	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
	181
	182	/* FLASH organization */
	183	#define CONFIG_SYS_FLASH_CFI
	184	#ifdef CONFIG_SYS_FLASH_CFI
	185	# define CONFIG_FLASH_CFI_DRIVER 1
	186	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	187	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	188	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	189	# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
	190	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	191	#endif
	192
	193	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	194
	195	/*
	196	* Configuration for environment
	197	* Environment is embedded in u-boot in the second sector of the flash
	198	*/
	199	#define CONFIG_ENV_OFFSET 0x2000
	200	#define CONFIG_ENV_SIZE 0x1000
	201	#define CONFIG_ENV_SECT_SIZE 0x2000
	202	#define CONFIG_ENV_IS_IN_FLASH 1
	203
	204	/* Cache Configuration */
	205	#define CONFIG_SYS_CACHELINE_SIZE 16
	206
dd9f054e	207	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	208	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	209	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	210	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	211	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	212	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	213	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	214	CF_ACR_EN \| CF_ACR_SM_ALL)
	215	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	216	CF_CACR_DISD \| CF_CACR_INVI \| \
	217	CF_CACR_CEIB \| CF_CACR_DCM \| \
	218	CF_CACR_EUSP)
	219
bf9a5215 TL	220	/* Chipselect bank definitions */
	221	/*
	222	* CS0 - NOR Flash
	223	* CS1 - Available
	224	* CS2 - Available
	225	* CS3 - Available
	226	* CS4 - Available
	227	* CS5 - Available
	228	*/
	229	#define CONFIG_SYS_CS0_BASE 0
	230	#define CONFIG_SYS_CS0_MASK 0x007F0001
	231	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	232
	233	#endif /* _M5208EVBE_H */