projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7530d341 PK |
1 | /* |
| 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * BSC9131 RDB board configuration file | |
| 25 | */ | |
| 26 | ||
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 30 | #ifdef CONFIG_BSC9131RDB | |
| 31 | #define CONFIG_BSC9131 | |
| 32 | #define CONFIG_NAND_FSL_IFC | |
| 33 | #endif | |
| 34 | ||
| 35 | #ifdef CONFIG_SPIFLASH | |
| 36 | #define CONFIG_RAMBOOT_SPIFLASH | |
| 37 | #define CONFIG_SYS_RAMBOOT | |
| 38 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 39 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| 40 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
| 41 | #endif | |
| 42 | ||
| 43 | #ifndef CONFIG_SYS_MONITOR_BASE | |
| 44 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 45 | #endif | |
| 46 | ||
| 47 | /* High Level Configuration Options */ | |
| 48 | #define CONFIG_BOOKE /* BOOKE */ | |
| 49 | #define CONFIG_E500 /* BOOKE e500 family */ | |
| 50 | #define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ | |
| 51 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
| 52 | ||
| 53 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
| 54 | #define CONFIG_TSEC_ENET | |
| 55 | #define CONFIG_ENV_OVERWRITE | |
| 56 | ||
| 57 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ | |
| 58 | #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ | |
| 59 | ||
| 60 | #define CONFIG_HWCONFIG | |
| 61 | /* | |
| 62 | * These can be toggled for performance analysis, otherwise use default. | |
| 63 | */ | |
| 64 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 65 | #define CONFIG_BTB /* enable branch predition */ | |
| 66 | ||
| 67 | #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ | |
| 68 | #define CONFIG_SYS_MEMTEST_END 0x01ffffff | |
| 69 | ||
| 70 | /* DDR Setup */ | |
| 71 | #define CONFIG_FSL_DDR3 | |
| 72 | #undef CONFIG_SYS_DDR_RAW_TIMING | |
| 73 | #undef CONFIG_DDR_SPD | |
| 74 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 75 | #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ | |
| 76 | ||
| 77 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 78 | ||
| 79 | #ifndef __ASSEMBLY__ | |
| 80 | extern unsigned long get_sdram_size(void); | |
| 81 | #endif | |
| 82 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ | |
| 83 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 84 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 85 | ||
| 86 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 87 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 88 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 89 | ||
| 90 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
| 91 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
| 92 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 93 | ||
| 94 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 95 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 96 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 97 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 98 | ||
| 99 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
| 100 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 101 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 102 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| 103 | #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ | |
| 104 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 | |
| 105 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 | |
| 106 | #define CONFIG_SYS_DDR_TIMING_5 0x02401400 | |
| 107 | ||
| 108 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 | |
| 109 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 | |
| 110 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 | |
| 111 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf | |
| 112 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
| 113 | #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 | |
| 114 | #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 | |
| 115 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 | |
| 116 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 | |
| 117 | ||
| 118 | /* | |
| 119 | * Base addresses -- Note these are effective addresses where the | |
| 120 | * actual resources get mapped (not physical addresses) | |
| 121 | */ | |
| 122 | /* relocated CCSRBAR */ | |
| 123 | #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT | |
| 124 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT | |
| 125 | ||
| 126 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ | |
| 127 | /* CONFIG_SYS_IMMR */ | |
| 128 | ||
| 129 | /* | |
| 130 | * Memory map | |
| 131 | * | |
| 132 | * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable | |
| 133 | * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M | |
| 134 | * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M | |
| 135 | * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K | |
| 136 | * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K | |
| 137 | * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K | |
| 138 | * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M | |
| 139 | * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M | |
| 140 | * | |
| 141 | */ | |
| 142 | ||
| 143 | /* | |
| 144 | * IFC Definitions | |
| 145 | */ | |
| 146 | #define CONFIG_SYS_NO_FLASH | |
| 147 | ||
| 148 | /* NAND Flash on IFC */ | |
| 149 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 150 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 151 | ||
| 152 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 153 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ | |
| 154 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 155 | | CSPR_V) | |
| 156 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 157 | ||
| 158 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 159 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 160 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 161 | | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ | |
| 162 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 163 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | |
| 164 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 165 | ||
| 166 | /* NAND Flash Timing Params */ | |
| 167 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ | |
| 168 | | FTIM0_NAND_TWP(0x06) \ | |
| 169 | | FTIM0_NAND_TWCHT(0x03) \ | |
| 170 | | FTIM0_NAND_TWH(0x04)) | |
| 171 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ | |
| 172 | | FTIM1_NAND_TWBE(0x23) \ | |
| 173 | | FTIM1_NAND_TRR(0x08) \ | |
| 174 | | FTIM1_NAND_TRP(0x05)) | |
| 175 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ | |
| 176 | | FTIM2_NAND_TREH(0x04) \ | |
| 177 | | FTIM2_NAND_TWHRE(0x3f)) | |
| 178 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) | |
| 179 | ||
| 180 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 181 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 182 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| 183 | #define CONFIG_CMD_NAND | |
| 184 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 185 | ||
| 186 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 187 | ||
| 188 | /* Set up IFC registers for boot location NAND */ | |
| 189 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 190 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 191 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 192 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 193 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 194 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 195 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 196 | ||
| 197 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ | |
| 198 | ||
| 199 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 200 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| 201 | #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ | |
| 202 | ||
| 203 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ | |
| 204 | - GENERATED_GBL_DATA_SIZE) | |
| 205 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 206 | ||
| 207 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ | |
| 208 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ | |
| 209 | ||
| 210 | /* Serial Port */ | |
| 211 | #define CONFIG_CONS_INDEX 1 | |
| 212 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 213 | #define CONFIG_SYS_NS16550 | |
| 214 | #define CONFIG_SYS_NS16550_SERIAL | |
| 215 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 216 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 217 | ||
| 218 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ | |
| 219 | ||
| 220 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 221 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 222 | ||
| 223 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 224 | ||
| 225 | /* Use the HUSH parser */ | |
| 226 | #define CONFIG_SYS_HUSH_PARSER | |
| 227 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 228 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 229 | #endif | |
| 230 | ||
| 231 | /* | |
| 232 | * Pass open firmware flat tree | |
| 233 | */ | |
| 234 | #define CONFIG_OF_LIBFDT | |
| 235 | #define CONFIG_OF_BOARD_SETUP | |
| 236 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
| 237 | ||
| 238 | /* new uImage format support */ | |
| 239 | #define CONFIG_FIT | |
| 240 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
| 241 | ||
| 242 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 243 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 244 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 245 | #define CONFIG_I2C_MULTI_BUS | |
| 246 | #define CONFIG_I2C_CMD_TREE | |
| 247 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
| 248 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 249 | ||
| 250 | /* I2C EEPROM */ | |
| 251 | #define CONFIG_CMD_EEPROM | |
| 252 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
| 253 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 254 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 255 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 256 | ||
| 257 | #define CONFIG_CMD_I2C | |
| 258 | ||
| 259 | ||
| 260 | #define CONFIG_FSL_ESPI | |
| 261 | /* eSPI - Enhanced SPI */ | |
| 262 | #ifdef CONFIG_FSL_ESPI | |
| 263 | #define CONFIG_SPI_FLASH | |
| 264 | #define CONFIG_SPI_FLASH_SPANSION | |
| 265 | #define CONFIG_CMD_SF | |
| 266 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 267 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 268 | #endif | |
| 269 | ||
| 270 | #if defined(CONFIG_TSEC_ENET) | |
| 271 | ||
| 272 | #define CONFIG_MII /* MII PHY management */ | |
| 273 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 274 | #define CONFIG_TSEC1 1 | |
| 275 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 276 | #define CONFIG_TSEC2 1 | |
| 277 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 278 | ||
| 279 | #define TSEC1_PHY_ADDR 0 | |
| 280 | #define TSEC2_PHY_ADDR 3 | |
| 281 | ||
| 282 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 283 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 284 | ||
| 285 | #define TSEC1_PHYIDX 0 | |
| 286 | ||
| 287 | #define TSEC2_PHYIDX 0 | |
| 288 | ||
| 289 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 290 | ||
| 291 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
| 292 | ||
| 293 | #endif /* CONFIG_TSEC_ENET */ | |
| 294 | ||
| 295 | /* | |
| 296 | * Environment | |
| 297 | */ | |
| 298 | #if defined(CONFIG_SYS_RAMBOOT) | |
| 299 | #if defined(CONFIG_RAMBOOT_SPIFLASH) | |
| 300 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 301 | #define CONFIG_ENV_SPI_BUS 0 | |
| 302 | #define CONFIG_ENV_SPI_CS 0 | |
| 303 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 304 | #define CONFIG_ENV_SPI_MODE 0 | |
| 305 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 306 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 307 | #define CONFIG_ENV_SIZE 0x2000 | |
| 308 | #else | |
| 309 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
| 310 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 311 | #define CONFIG_ENV_SIZE 0x2000 | |
| 312 | #endif | |
| 313 | #else | |
| 314 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 315 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 316 | #define CONFIG_ENV_SIZE 0x400 | |
| 317 | #endif | |
| 318 | ||
| 319 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 320 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 321 | ||
| 322 | /* | |
| 323 | * Command line configuration. | |
| 324 | */ | |
| 325 | #include <config_cmd_default.h> | |
| 326 | ||
| 327 | #define CONFIG_CMD_DHCP | |
| 328 | #define CONFIG_CMD_ERRATA | |
| 329 | #define CONFIG_CMD_ELF | |
| 330 | #define CONFIG_CMD_EXT2 | |
| 331 | #define CONFIG_CMD_FAT | |
| 332 | #define CONFIG_CMD_IRQ | |
| 333 | #define CONFIG_CMD_MII | |
| 334 | #define CONFIG_DOS_PARTITION | |
| 335 | #define CONFIG_CMD_PING | |
| 336 | #define CONFIG_CMD_REGINFO | |
| 337 | #define CONFIG_CMD_SETEXPR | |
| 338 | ||
| 339 | /* | |
| 340 | * Miscellaneous configurable options | |
| 341 | */ | |
| 342 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 343 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 344 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 345 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 346 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 347 | ||
| 348 | #if defined(CONFIG_CMD_KGDB) | |
| 349 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 350 | #else | |
| 351 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 352 | #endif | |
| 353 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 354 | /* Print Buffer Size */ | |
| 355 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 356 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
| 357 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 358 | ||
| 359 | /* | |
| 360 | * For booting Linux, the board info and command line data | |
| 361 | * have to be in the first 64 MB of memory, since this is | |
| 362 | * the maximum mapped by the Linux kernel during initialization. | |
| 363 | */ | |
| 364 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
| 365 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 366 | ||
| 367 | #if defined(CONFIG_CMD_KGDB) | |
| 368 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 369 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 370 | #endif | |
| 371 | ||
| 372 | #define CONFIG_USB_EHCI | |
| 373 | ||
| 374 | #ifdef CONFIG_USB_EHCI | |
| 375 | #define CONFIG_CMD_USB | |
| 376 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 377 | #define CONFIG_USB_EHCI_FSL | |
| 378 | #define CONFIG_USB_STORAGE | |
| 379 | #define CONFIG_HAS_FSL_DR_USB | |
| 380 | #endif | |
| 381 | ||
| 382 | /* | |
| 383 | * Environment Configuration | |
| 384 | */ | |
| 385 | ||
| 386 | #if defined(CONFIG_TSEC_ENET) | |
| 387 | #define CONFIG_HAS_ETH0 | |
| 388 | #endif | |
| 389 | ||
| 390 | #define CONFIG_HOSTNAME BSC9131rdb | |
| 391 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 392 | #define CONFIG_BOOTFILE "uImage" | |
| 393 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ | |
| 394 | ||
| 395 | #define CONFIG_BAUDRATE 115200 | |
| 396 | ||
| 397 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 398 | "netdev=eth0\0" \ | |
| 399 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
| 400 | "loadaddr=1000000\0" \ | |
| 401 | "bootfile=uImage\0" \ | |
| 402 | "consoledev=ttyS0\0" \ | |
| 403 | "ramdiskaddr=2000000\0" \ | |
| 404 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 405 | "fdtaddr=c00000\0" \ | |
| 406 | "fdtfile=bsc9131rdb.dtb\0" \ | |
| 407 | "bdev=sda1\0" \ | |
| 408 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ | |
| 409 | "othbootargs=ramdisk_size=600000 \0" \ | |
| 410 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 411 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 412 | "usb start;" \ | |
| 413 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 414 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 415 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| 416 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 417 | ||
| 418 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 419 | "setenv bootargs root=/dev/ram rw " \ | |
| 420 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 421 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 422 | "tftp $loadaddr $bootfile;" \ | |
| 423 | "tftp $fdtaddr $fdtfile;" \ | |
| 424 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 425 | ||
| 426 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 427 | ||
| 428 | #endif /* __CONFIG_H */ |