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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
0044c42e SR |
2 | /* |
3 | * (C) Copyright 2011 | |
4 | * Heiko Schocher, DENX Software Engineering, [email protected]. | |
5 | * | |
abcaa6ee TR |
6 | * A bootcount driver for the RTC IP block found on many TI platforms. |
7 | * This requires the RTC clocks, etc, to be enabled prior to use and | |
8 | * not all boards with this IP block on it will have the RTC in use. | |
0044c42e SR |
9 | */ |
10 | ||
11 | #include <bootcount.h> | |
155d424a | 12 | #include <asm/davinci_rtc.h> |
0044c42e SR |
13 | |
14 | void bootcount_store(ulong a) | |
15 | { | |
16 | struct davinci_rtc *reg = | |
17 | (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; | |
18 | ||
19 | /* | |
bac9170f TM |
20 | * write RTC kick registers to enable write |
21 | * for RTC Scratch registers. Scratch register 2 is | |
22 | * used for bootcount value. | |
0044c42e SR |
23 | */ |
24 | writel(RTC_KICK0R_WE, ®->kick0r); | |
25 | writel(RTC_KICK1R_WE, ®->kick1r); | |
22ee3975 | 26 | raw_bootcount_store(®->scratch2, |
758694ff | 27 | (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff)); |
0044c42e SR |
28 | } |
29 | ||
30 | ulong bootcount_load(void) | |
31 | { | |
22ee3975 | 32 | unsigned long val; |
0044c42e SR |
33 | struct davinci_rtc *reg = |
34 | (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; | |
35 | ||
22ee3975 | 36 | val = raw_bootcount_load(®->scratch2); |
758694ff | 37 | if ((val & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) |
0044c42e SR |
38 | return 0; |
39 | else | |
22ee3975 | 40 | return val & 0x0000ffff; |
0044c42e | 41 | } |