[J-u-boot.git] / arch / arm / mach-at91 / arm926ejs / clock.c

/*
 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
 *
 * Copyright (C) 2005 David Brownell
 * Copyright (C) 2005 Ivan Kokshaysky
 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>

#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif

DECLARE_GLOBAL_DATA_PTR;

static unsigned long at91_css_to_rate(unsigned long css)
{
	switch (css) {
	case AT91_PMC_MCKR_CSS_SLOW:
		return CONFIG_SYS_AT91_SLOW_CLOCK;
	case AT91_PMC_MCKR_CSS_MAIN:
		return gd->arch.main_clk_rate_hz;
	case AT91_PMC_MCKR_CSS_PLLA:
		return gd->arch.plla_rate_hz;
	case AT91_PMC_MCKR_CSS_PLLB:
		return gd->arch.pllb_rate_hz;
	}

	return 0;
}

#ifdef CONFIG_USB_ATMEL
static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;

	/* PLL output max 240 MHz (or 180 MHz per errata) */
	if (out_freq > 240000000)
		goto fail;

	for (i = 1; i < 256; i++) {
		int diff1;
		unsigned input, mul1;

		/*
		 * PLL input between 1MHz and 32MHz per spec, but lower
		 * frequences seem necessary in some cases so allow 100K.
		 * Warning: some newer products need 2MHz min.
		 */
		input = main_freq / i;
#if defined(CONFIG_AT91SAM9G20)
		if (input < 2000000)
			continue;
#endif
		if (input < 100000)
			continue;
		if (input > 32000000)
			continue;

		mul1 = out_freq / input;
#if defined(CONFIG_AT91SAM9G20)
		if (mul > 63)
			continue;
#endif
		if (mul1 > 2048)
			continue;
		if (mul1 < 2)
			goto fail;

		diff1 = out_freq - input * mul1;
		if (diff1 < 0)
			diff1 = -diff1;
		if (diff > diff1) {
			diff = diff1;
			div = i;
			mul = mul1;
			if (diff == 0)
				break;
		}
	}
	if (i == 256 && diff > (out_freq >> 5))
		goto fail;
	return ret | ((mul - 1) << 16) | div;
fail:
	return 0;
}
#endif

static u32 at91_pll_rate(u32 freq, u32 reg)
{
	unsigned mul, div;

	div = reg & 0xff;
	mul = (reg >> 16) & 0x7ff;
	if (div && mul) {
		freq /= div;
		freq *= mul + 1;
	} else
		freq = 0;

	return freq;
}

int at91_clock_init(unsigned long main_clock)
{
	unsigned freq, mckr;
	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
	unsigned tmp;
	/*
	 * When the bootloader initialized the main oscillator correctly,
	 * there's no problem using the cycle counter.  But if it didn't,
	 * or when using oscillator bypass mode, we must be told the speed
	 * of the main clock.
	 */
	if (!main_clock) {
		do {
			tmp = readl(&pmc->mcfr);
		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
		tmp &= AT91_PMC_MCFR_MAINF_MASK;
		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
	}
#endif
	gd->arch.main_clk_rate_hz = main_clock;

	/* report if PLLA is more than mildly overclocked */
	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));

#ifdef CONFIG_USB_ATMEL
	/*
	 * USB clock init:  choose 48 MHz PLLB value,
	 * disable 48MHz clock during usb peripheral suspend.
	 *
	 * REVISIT:  assumes MCK doesn't derive from PLLB!
	 */
	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
			     AT91_PMC_PLLBR_USBDIV_2;
	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
					      gd->arch.at91_pllb_usb_init);
#endif

	/*
	 * MCK and CPU derive from one of those primary clocks.
	 * For now, assume this parentage won't change.
	 */
	mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
	/* plla divisor by 2 */
	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
	freq = gd->arch.mck_rate_hz;

	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
#if defined(CONFIG_AT91SAM9G20)
	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
		freq /= 2;			/* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
	/* mdiv <==> divisor
	 *  0   <==>   1
	 *  1   <==>   2
	 *  2   <==>   4
	 *  3   <==>   3
	 */
	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
		? freq / 3
		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
	gd->arch.mck_rate_hz = freq /
			(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
	gd->arch.cpu_clk_rate_hz = freq;

	return 0;
}

#if !defined(AT91_PLL_LOCK_TIMEOUT)
#define AT91_PLL_LOCK_TIMEOUT	1000000
#endif

void at91_plla_init(u32 pllar)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	int timeout = AT91_PLL_LOCK_TIMEOUT;

	writel(pllar, &pmc->pllar);
	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
		timeout--;
		if (timeout == 0)
			break;
	}
}
void at91_pllb_init(u32 pllbr)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	int timeout = AT91_PLL_LOCK_TIMEOUT;

	writel(pllbr, &pmc->pllbr);
	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
		timeout--;
		if (timeout == 0)
			break;
	}
}

void at91_mck_init(u32 mckr)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	int timeout = AT91_PLL_LOCK_TIMEOUT;
	u32 tmp;

	tmp = readl(&pmc->mckr);
	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
		 AT91_PMC_MCKR_MDIV_MASK |
		 AT91_PMC_MCKR_PLLADIV_MASK |
		 AT91_PMC_MCKR_CSS_MASK);
	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
		       AT91_PMC_MCKR_MDIV_MASK |
		       AT91_PMC_MCKR_PLLADIV_MASK |
		       AT91_PMC_MCKR_CSS_MASK);
	writel(tmp, &pmc->mckr);

	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
		timeout--;
		if (timeout == 0)
			break;
	}
}

void at91_periph_clk_enable(int id)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	writel(1 << id, &pmc->pcer);
}
Commit	Line	Data
dc39ae95 JCPV	1	/*
	2	* [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
	3	*
	4	* Copyright (C) 2005 David Brownell
	5	* Copyright (C) 2005 Ivan Kokshaysky
	6	* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
dc39ae95 JCPV	9	*/
dc39ae95 JCPV	10
5dca710a	11	#include <common.h>
86592f60	12	#include <asm/io.h>
dc39ae95 JCPV	13	#include <asm/arch/hardware.h>
	14	#include <asm/arch/at91_pmc.h>
	15	#include <asm/arch/clk.h>
dc39ae95	16
5dca710a RM	17	#if !defined(CONFIG_AT91FAMILY)
	18	# error You need to define CONFIG_AT91FAMILY in your board config!
	19	#endif
	20
	21	DECLARE_GLOBAL_DATA_PTR;
dc39ae95	22
dc39ae95 JCPV	23	static unsigned long at91_css_to_rate(unsigned long css)
	24	{
	25	switch (css) {
0cf0b931	26	case AT91_PMC_MCKR_CSS_SLOW:
9f3fe90f	27	return CONFIG_SYS_AT91_SLOW_CLOCK;
0cf0b931	28	case AT91_PMC_MCKR_CSS_MAIN:
f47e6ecd	29	return gd->arch.main_clk_rate_hz;
0cf0b931	30	case AT91_PMC_MCKR_CSS_PLLA:
f47e6ecd	31	return gd->arch.plla_rate_hz;
0cf0b931	32	case AT91_PMC_MCKR_CSS_PLLB:
f47e6ecd	33	return gd->arch.pllb_rate_hz;
dc39ae95 JCPV	34	}
	35
	36	return 0;
	37	}
	38
	39	#ifdef CONFIG_USB_ATMEL
	40	static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
	41	{
	42	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	43	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
	44
	45	/* PLL output max 240 MHz (or 180 MHz per errata) */
	46	if (out_freq > 240000000)
	47	goto fail;
	48
	49	for (i = 1; i < 256; i++) {
	50	int diff1;
	51	unsigned input, mul1;
	52
	53	/*
	54	* PLL input between 1MHz and 32MHz per spec, but lower
	55	* frequences seem necessary in some cases so allow 100K.
	56	* Warning: some newer products need 2MHz min.
	57	*/
	58	input = main_freq / i;
	59	#if defined(CONFIG_AT91SAM9G20)
	60	if (input < 2000000)
	61	continue;
	62	#endif
	63	if (input < 100000)
	64	continue;
	65	if (input > 32000000)
	66	continue;
	67
	68	mul1 = out_freq / input;
	69	#if defined(CONFIG_AT91SAM9G20)
	70	if (mul > 63)
	71	continue;
	72	#endif
	73	if (mul1 > 2048)
	74	continue;
	75	if (mul1 < 2)
	76	goto fail;
	77
	78	diff1 = out_freq - input * mul1;
	79	if (diff1 < 0)
	80	diff1 = -diff1;
	81	if (diff > diff1) {
	82	diff = diff1;
	83	div = i;
	84	mul = mul1;
	85	if (diff == 0)
	86	break;
	87	}
	88	}
	89	if (i == 256 && diff > (out_freq >> 5))
	90	goto fail;
	91	return ret \| ((mul - 1) << 16) \| div;
	92	fail:
	93	return 0;
	94	}
a1e5f931	95	#endif
dc39ae95 JCPV	96
	97	static u32 at91_pll_rate(u32 freq, u32 reg)
	98	{
	99	unsigned mul, div;
	100
	101	div = reg & 0xff;
	102	mul = (reg >> 16) & 0x7ff;
	103	if (div && mul) {
	104	freq /= div;
	105	freq *= mul + 1;
	106	} else
	107	freq = 0;
	108
	109	return freq;
	110	}
dc39ae95 JCPV	111
	112	int at91_clock_init(unsigned long main_clock)
	113	{
	114	unsigned freq, mckr;
9f3fe90f	115	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
7c966a8b	116	#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
dc39ae95 JCPV	117	unsigned tmp;
	118	/*
	119	* When the bootloader initialized the main oscillator correctly,
	120	* there's no problem using the cycle counter. But if it didn't,
	121	* or when using oscillator bypass mode, we must be told the speed
	122	* of the main clock.
	123	*/
	124	if (!main_clock) {
	125	do {
7cedb298 JS	126	tmp = readl(&pmc->mcfr);
	127	} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
	128	tmp &= AT91_PMC_MCFR_MAINF_MASK;
9f3fe90f	129	main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
dc39ae95 JCPV	130	}
dc39ae95 JCPV	131	#endif
f47e6ecd	132	gd->arch.main_clk_rate_hz = main_clock;
dc39ae95 JCPV	133
dc39ae95 JCPV	134	/* report if PLLA is more than mildly overclocked */
f47e6ecd	135	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
dc39ae95 JCPV	136
	137	#ifdef CONFIG_USB_ATMEL
	138	/*
	139	* USB clock init: choose 48 MHz PLLB value,
	140	* disable 48MHz clock during usb peripheral suspend.
	141	*
	142	* REVISIT: assumes MCK doesn't derive from PLLB!
	143	*/
f47e6ecd	144	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) \|
0cf0b931	145	AT91_PMC_PLLBR_USBDIV_2;
f47e6ecd SG	146	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
f47e6ecd SG	147	gd->arch.at91_pllb_usb_init);
dc39ae95 JCPV	148	#endif
	149
	150	/*
	151	* MCK and CPU derive from one of those primary clocks.
	152	* For now, assume this parentage won't change.
	153	*/
0cf0b931	154	mckr = readl(&pmc->mckr);
f7fa2f37	155	#if defined(CONFIG_AT91SAM9G45) \|\| defined(CONFIG_AT91SAM9M10G45) \
9e336903	156	\|\| defined(CONFIG_AT91SAM9N12) \|\| defined(CONFIG_AT91SAM9X5)
22ee6473	157	/* plla divisor by 2 */
f47e6ecd	158	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
22ee6473	159	#endif
f47e6ecd SG	160	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
f47e6ecd SG	161	freq = gd->arch.mck_rate_hz;
22ee6473	162
0cf0b931	163	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
c3a383f5	164	#if defined(CONFIG_AT91SAM9G20)
0cf0b931	165	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
f47e6ecd	166	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
0cf0b931 JS	167	freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
	168	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
	169	freq /= 2; /* processor clock division */
f7fa2f37	170	#elif defined(CONFIG_AT91SAM9G45) \|\| defined(CONFIG_AT91SAM9M10G45) \
9e336903	171	\|\| defined(CONFIG_AT91SAM9N12) \|\| defined(CONFIG_AT91SAM9X5)
f7fa2f37 BS	172	/* mdiv <==> divisor
	173	* 0 <==> 1
	174	* 1 <==> 2
	175	* 2 <==> 4
	176	* 3 <==> 3
	177	*/
f47e6ecd	178	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
e99056e3	179	(AT91_PMC_MCKR_MDIV_2 \| AT91_PMC_MCKR_MDIV_4)
0cf0b931 JS	180	? freq / 3
0cf0b931 JS	181	: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
dc39ae95	182	#else
f47e6ecd SG	183	gd->arch.mck_rate_hz = freq /
f47e6ecd SG	184	(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
dc39ae95	185	#endif
f47e6ecd	186	gd->arch.cpu_clk_rate_hz = freq;
dc39ae95	187
0cf0b931	188	return 0;
dc39ae95	189	}
5abc00d0 HS	190
	191	#if !defined(AT91_PLL_LOCK_TIMEOUT)
	192	#define AT91_PLL_LOCK_TIMEOUT 1000000
	193	#endif
	194
	195	void at91_plla_init(u32 pllar)
	196	{
	197	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	198	int timeout = AT91_PLL_LOCK_TIMEOUT;
	199
	200	writel(pllar, &pmc->pllar);
	201	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA \| AT91_PMC_MCKRDY))) {
	202	timeout--;
	203	if (timeout == 0)
	204	break;
	205	}
	206	}
	207	void at91_pllb_init(u32 pllbr)
	208	{
	209	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	210	int timeout = AT91_PLL_LOCK_TIMEOUT;
	211
	212	writel(pllbr, &pmc->pllbr);
	213	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB \| AT91_PMC_MCKRDY))) {
	214	timeout--;
	215	if (timeout == 0)
	216	break;
	217	}
	218	}
	219
	220	void at91_mck_init(u32 mckr)
	221	{
	222	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	223	int timeout = AT91_PLL_LOCK_TIMEOUT;
	224	u32 tmp;
	225
	226	tmp = readl(&pmc->mckr);
	227	tmp &= ~(AT91_PMC_MCKR_PRES_MASK \|
	228	AT91_PMC_MCKR_MDIV_MASK \|
	229	AT91_PMC_MCKR_PLLADIV_MASK \|
	230	AT91_PMC_MCKR_CSS_MASK);
	231	tmp \|= mckr & (AT91_PMC_MCKR_PRES_MASK \|
	232	AT91_PMC_MCKR_MDIV_MASK \|
	233	AT91_PMC_MCKR_PLLADIV_MASK \|
	234	AT91_PMC_MCKR_CSS_MASK);
	235	writel(tmp, &pmc->mckr);
	236
	237	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
	238	timeout--;
	239	if (timeout == 0)
	240	break;
	241	}
	242	}
	243
	244	void at91_periph_clk_enable(int id)
	245	{
	246	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	247
	248	writel(1 << id, &pmc->pcer);
	249	}