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37e3a36a SDPP |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Copyright (C) 2018 Xilinx, Inc. | |
4 | */ | |
5 | ||
6 | #ifndef _ZYNQ_BOOTIMG_H_ | |
7 | #define _ZYNQ_BOOTIMG_H_ | |
8 | ||
9 | #define ZYNQ_MAX_PARTITION_NUMBER 0xE | |
10 | ||
11 | struct partition_hdr { | |
12 | u32 imagewordlen; /* 0x0 */ | |
13 | u32 datawordlen; /* 0x4 */ | |
14 | u32 partitionwordlen; /* 0x8 */ | |
15 | u32 loadaddr; /* 0xC */ | |
16 | u32 execaddr; /* 0x10 */ | |
17 | u32 partitionstart; /* 0x14 */ | |
18 | u32 partitionattr; /* 0x18 */ | |
19 | u32 sectioncount; /* 0x1C */ | |
20 | u32 checksumoffset; /* 0x20 */ | |
21 | u32 pads1[1]; | |
22 | u32 acoffset; /* 0x28 */ | |
23 | u32 pads2[4]; | |
24 | u32 checksum; /* 0x3C */ | |
25 | }; | |
26 | ||
27 | int zynq_get_part_count(struct partition_hdr *part_hdr_info); | |
28 | int zynq_get_partition_info(u32 image_base_addr, u32 *fsbl_len, | |
29 | struct partition_hdr *part_hdr); | |
30 | int zynq_validate_hdr(struct partition_hdr *header); | |
31 | int zynq_validate_partition(u32 start_addr, u32 len, u32 chksum_off); | |
32 | ||
33 | #endif /* _ZYNQ_BOOTIMG_H_ */ |