[J-u-boot.git] / drivers / net / hifemac_mdio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Hisilicon Fast Ethernet MDIO Bus Driver
 *
 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
 */

#include <dm.h>
#include <clk.h>
#include <miiphy.h>
#include <dm/device_compat.h>
#include <linux/io.h>
#include <linux/iopoll.h>

#define MDIO_RWCTRL		0x00
#define MDIO_RO_DATA		0x04
#define MDIO_WRITE		BIT(13)
#define MDIO_RW_FINISH		BIT(15)
#define BIT_PHY_ADDR_OFFSET	8
#define BIT_WR_DATA_OFFSET	16

struct hisi_femac_mdio_data {
	struct clk *clk;
	void __iomem *membase;
};

static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
{
	u32 val;

	return readl_poll_timeout(data->membase + MDIO_RWCTRL,
				  val, val & MDIO_RW_FINISH, 10000);
}

static int hisi_femac_mdio_read(struct udevice *dev, int addr, int devad, int reg)
{
	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	int ret;

	ret = hisi_femac_mdio_wait_ready(data);
	if (ret)
		return ret;

	writel((addr << BIT_PHY_ADDR_OFFSET) | reg,
	       data->membase + MDIO_RWCTRL);

	ret = hisi_femac_mdio_wait_ready(data);
	if (ret)
		return ret;

	return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
}

static int hisi_femac_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
{
	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	int ret;

	ret = hisi_femac_mdio_wait_ready(data);
	if (ret)
		return ret;

	writel(MDIO_WRITE | (val << BIT_WR_DATA_OFFSET) |
	       (addr << BIT_PHY_ADDR_OFFSET) | reg,
	       data->membase + MDIO_RWCTRL);

	return hisi_femac_mdio_wait_ready(data);
}

static int hisi_femac_mdio_of_to_plat(struct udevice *dev)
{
	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	int ret;

	data->membase = dev_remap_addr(dev);
	if (IS_ERR(data->membase)) {
		ret = PTR_ERR(data->membase);
		dev_err(dev, "Failed to remap base addr %d\n", ret);
		return log_msg_ret("mdio", ret);
	}

	// clk is optional
	data->clk = devm_clk_get_optional(dev, NULL);

	return 0;
}

static int hisi_femac_mdio_probe(struct udevice *dev)
{
	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	int ret;

	ret = clk_prepare_enable(data->clk);
	if (ret) {
		dev_err(dev, "Failed to enable clock: %d\n", ret);
		return log_msg_ret("clk", ret);
	}

	return 0;
}

static const struct mdio_ops hisi_femac_mdio_ops = {
	.read = hisi_femac_mdio_read,
	.write = hisi_femac_mdio_write,
};

static const struct udevice_id hisi_femac_mdio_dt_ids[] = {
	{ .compatible = "hisilicon,hisi-femac-mdio" },
	{ }
};

U_BOOT_DRIVER(hisi_femac_mdio_driver) = {
	.name = "hisi-femac-mdio",
	.id = UCLASS_MDIO,
	.of_match = hisi_femac_mdio_dt_ids,
	.of_to_plat = hisi_femac_mdio_of_to_plat,
	.probe = hisi_femac_mdio_probe,
	.ops = &hisi_femac_mdio_ops,
	.plat_auto = sizeof(struct mdio_perdev_priv),
	.priv_auto = sizeof(struct hisi_femac_mdio_data),
};
Commit	Line	Data
6b5c8d98 YX	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Hisilicon Fast Ethernet MDIO Bus Driver
	4	*
	5	* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
	6	*/
	7
	8	#include <dm.h>
	9	#include <clk.h>
	10	#include <miiphy.h>
3724ec4e	11	#include <dm/device_compat.h>
6b5c8d98 YX	12	#include <linux/io.h>
	13	#include <linux/iopoll.h>
	14
	15	#define MDIO_RWCTRL 0x00
	16	#define MDIO_RO_DATA 0x04
	17	#define MDIO_WRITE BIT(13)
	18	#define MDIO_RW_FINISH BIT(15)
	19	#define BIT_PHY_ADDR_OFFSET 8
	20	#define BIT_WR_DATA_OFFSET 16
	21
	22	struct hisi_femac_mdio_data {
	23	struct clk *clk;
	24	void __iomem *membase;
	25	};
	26
	27	static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
	28	{
	29	u32 val;
	30
	31	return readl_poll_timeout(data->membase + MDIO_RWCTRL,
	32	val, val & MDIO_RW_FINISH, 10000);
	33	}
	34
	35	static int hisi_femac_mdio_read(struct udevice *dev, int addr, int devad, int reg)
	36	{
	37	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	38	int ret;
	39
	40	ret = hisi_femac_mdio_wait_ready(data);
	41	if (ret)
	42	return ret;
	43
	44	writel((addr << BIT_PHY_ADDR_OFFSET) \| reg,
	45	data->membase + MDIO_RWCTRL);
	46
	47	ret = hisi_femac_mdio_wait_ready(data);
	48	if (ret)
	49	return ret;
	50
	51	return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
	52	}
	53
	54	static int hisi_femac_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
	55	{
	56	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	57	int ret;
	58
	59	ret = hisi_femac_mdio_wait_ready(data);
	60	if (ret)
	61	return ret;
	62
	63	writel(MDIO_WRITE \| (val << BIT_WR_DATA_OFFSET) \|
	64	(addr << BIT_PHY_ADDR_OFFSET) \| reg,
	65	data->membase + MDIO_RWCTRL);
	66
	67	return hisi_femac_mdio_wait_ready(data);
	68	}
	69
	70	static int hisi_femac_mdio_of_to_plat(struct udevice *dev)
	71	{
	72	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	73	int ret;
	74
	75	data->membase = dev_remap_addr(dev);
76	if (IS_ERR(data->membase)) {
77	ret = PTR_ERR(data->membase);
3724ec4e YX	78	dev_err(dev, "Failed to remap base addr %d\n", ret);
3724ec4e YX	79	return log_msg_ret("mdio", ret);
6b5c8d98 YX	80	}
	81
	82	// clk is optional
	83	data->clk = devm_clk_get_optional(dev, NULL);
	84
	85	return 0;
	86	}
	87
	88	static int hisi_femac_mdio_probe(struct udevice *dev)
	89	{
	90	struct hisi_femac_mdio_data *data = dev_get_priv(dev);
	91	int ret;
	92
	93	ret = clk_prepare_enable(data->clk);
3724ec4e YX	94	if (ret) {
	95	dev_err(dev, "Failed to enable clock: %d\n", ret);
	96	return log_msg_ret("clk", ret);
	97	}
6b5c8d98 YX	98
	99	return 0;
	100	}
	101
	102	static const struct mdio_ops hisi_femac_mdio_ops = {
	103	.read = hisi_femac_mdio_read,
	104	.write = hisi_femac_mdio_write,
	105	};
	106
	107	static const struct udevice_id hisi_femac_mdio_dt_ids[] = {
	108	{ .compatible = "hisilicon,hisi-femac-mdio" },
	109	{ }
	110	};
	111
	112	U_BOOT_DRIVER(hisi_femac_mdio_driver) = {
	113	.name = "hisi-femac-mdio",
	114	.id = UCLASS_MDIO,
	115	.of_match = hisi_femac_mdio_dt_ids,
	116	.of_to_plat = hisi_femac_mdio_of_to_plat,
	117	.probe = hisi_femac_mdio_probe,
	118	.ops = &hisi_femac_mdio_ops,
3724ec4e	119	.plat_auto = sizeof(struct mdio_perdev_priv),
6b5c8d98 YX	120	.priv_auto = sizeof(struct hisi_femac_mdio_data),
6b5c8d98 YX	121	};