projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 52568c36 WD |
1 | /* |
| 2 | * (C) Copyright 2009 Wolfgang Denk <[email protected]> | |
| 3 | * (C) Copyright 2009, DAVE Srl <www.dave.eu> | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 52568c36 WD |
6 | */ |
| 7 | ||
| 8 | /* | |
| 9 | * Aria board configuration file | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __CONFIG_H | |
| 13 | #define __CONFIG_H | |
| 14 | ||
| 15 | #define CONFIG_ARIA 1 | |
| 32ff89dc AG |
16 | #define CONFIG_DISPLAY_BOARDINFO |
| 17 | #define CONFIG_SYS_GENERIC_BOARD | |
| 18 | ||
| 52568c36 WD |
19 | /* |
| 20 | * Memory map for the ARIA board: | |
| 21 | * | |
| 22 | * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) | |
| 23 | * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) | |
| 24 | * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6 | |
| 25 | * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2 | |
| 26 | * 0x8000_0000-0x803F_FFFF IMMR (4 MB) | |
| 27 | * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB) | |
| 28 | * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB) | |
| 29 | * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
| 30 | * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) | |
| 31 | */ | |
| 32 | ||
| 33 | /* | |
| 34 | * High Level Configuration Options | |
| 35 | */ | |
| 36 | #define CONFIG_E300 1 /* E300 Family */ | |
| 52568c36 | 37 | #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ |
| 52568c36 | 38 | |
| 2ae18241 WD |
39 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 40 | ||
| 52568c36 WD |
41 | /* video */ |
| 42 | #undef CONFIG_VIDEO | |
| 43 | ||
| 44 | #if defined(CONFIG_VIDEO) | |
| 45 | #define CONFIG_CFB_CONSOLE | |
| 46 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 47 | #endif | |
| 48 | ||
| 49 | /* CONFIG_PCI is defined at config time */ | |
| 50 | ||
| 51 | #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ | |
| 52 | ||
| 52568c36 WD |
53 | #define CONFIG_MISC_INIT_R |
| 54 | ||
| 55 | #define CONFIG_SYS_IMMR 0x80000000 | |
| 56 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) | |
| 57 | ||
| 58 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
| 59 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 60 | ||
| 61 | /* | |
| 62 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
| 63 | */ | |
| 64 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ | |
| 65 | #define CONFIG_SYS_DDR_BASE 0x00000000 | |
| 66 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| b9947bbb | 67 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
| 52568c36 | 68 | |
| 5d937e8b AG |
69 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
| 70 | ||
| 52568c36 WD |
71 | /* DDR Controller Configuration |
| 72 | * | |
| 73 | * SYS_CFG: | |
| 74 | * [31:31] MDDRC Soft Reset: Diabled | |
| 75 | * [30:30] DRAM CKE pin: Enabled | |
| 76 | * [29:29] DRAM CLK: Enabled | |
| 77 | * [28:28] Command Mode: Enabled (For initialization only) | |
| 78 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
| 79 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
| 80 | * [20:19] Read Test: DON'T USE | |
| 81 | * [18:18] Self Refresh: Enabled | |
| 82 | * [17:17] 16bit Mode: Disabled | |
| 83 | * [16:13] Ready Delay: 2 | |
| 84 | * [12:12] Half DQS Delay: Disabled | |
| 85 | * [11:11] Quarter DQS Delay: Disabled | |
| 86 | * [10:08] Write Delay: 2 | |
| 87 | * [07:07] Early ODT: Disabled | |
| 88 | * [06:06] On DIE Termination: Disabled | |
| 89 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
| 90 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
| 91 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
| 92 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
| 93 | * [01:01] FIFO Overlfow Enabled: Enabled | |
| 94 | * [00:00] FIFO Underflow Enabled: Enabled | |
| 95 | * TIME_CFG0 | |
| 96 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
| 97 | * [15:8] DRAM Command Time: 0 CSB clocks | |
| 98 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
| 99 | * TIME_CFG1 | |
| 100 | * [31:26] DRAM tRFC: | |
| 101 | * [25:21] DRAM tWR1: | |
| 102 | * [20:17] DRAM tWRT1: | |
| 103 | * [16:11] DRAM tDRR: | |
| 104 | * [10:05] DRAM tRC: | |
| 105 | * [04:00] DRAM tRAS: | |
| 106 | * TIME_CFG2 | |
| 107 | * [31:28] DRAM tRCD: | |
| 108 | * [27:23] DRAM tFAW: | |
| 109 | * [22:19] DRAM tRTW1: | |
| 110 | * [18:15] DRAM tCCD: | |
| 111 | * [14:10] DRAM tRTP: | |
| 112 | * [09:05] DRAM tRP: | |
| 113 | * [04:00] DRAM tRPA | |
| 114 | */ | |
| 25671c86 WD |
115 | #define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ |
| 116 | (1 << 30) | /* CKE */ \ | |
| 117 | (1 << 29) | /* CLK_ON */ \ | |
| 054197ba | 118 | (0 << 28) | /* CMD_MODE */ \ |
| 25671c86 WD |
119 | (4 << 25) | /* DRAM_ROW_SELECT */ \ |
| 120 | (3 << 21) | /* DRAM_BANK_SELECT */ \ | |
| 121 | (0 << 18) | /* SELF_REF_EN */ \ | |
| 122 | (0 << 17) | /* 16BIT_MODE */ \ | |
| 123 | (2 << 13) | /* RDLY */ \ | |
| 124 | (0 << 12) | /* HALF_DQS_DLY */ \ | |
| 125 | (1 << 11) | /* QUART_DQS_DLY */ \ | |
| 126 | (2 << 8) | /* WDLY */ \ | |
| 127 | (0 << 7) | /* EARLY_ODT */ \ | |
| 128 | (1 << 6) | /* ON_DIE_TERMINATE */ \ | |
| 129 | (0 << 5) | /* FIFO_OV_CLEAR */ \ | |
| 130 | (0 << 4) | /* FIFO_UV_CLEAR */ \ | |
| 131 | (0 << 1) | /* FIFO_OV_EN */ \ | |
| 132 | (0 << 0) /* FIFO_UV_EN */ \ | |
| 133 | ) | |
| 134 | ||
| 054197ba | 135 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E |
| 25671c86 WD |
136 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 |
| 137 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 | |
| 52568c36 | 138 | |
| 054197ba MS |
139 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
| 140 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 | |
| 25671c86 WD |
141 | #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ |
| 142 | (0 << 22) | /* DRAM_CS */ \ | |
| 143 | (0 << 21) | /* DRAM_RAS */ \ | |
| 144 | (0 << 20) | /* DRAM_CAS */ \ | |
| 145 | (0 << 19) | /* DRAM_WEB */ \ | |
| 146 | (1 << 16) | /* DRAM_BS[2:0] */ \ | |
| 147 | (0 << 15) | /* */ \ | |
| 148 | (0 << 12) | /* A12->out */ \ | |
| 149 | (0 << 11) | /* A11->RDQS */ \ | |
| 150 | (0 << 10) | /* A10->DQS# */ \ | |
| 151 | (0 << 7) | /* OCD program */ \ | |
| 152 | (0 << 6) | /* Rtt1 */ \ | |
| 153 | (0 << 3) | /* posted CAS# */ \ | |
| 154 | (0 << 2) | /* Rtt0 */ \ | |
| 155 | (1 << 1) | /* ODS */ \ | |
| 156 | (0 << 0) /* DLL */ \ | |
| 157 | ) | |
| 158 | #define CONFIG_SYS_MICRON_EMR2 0x01020000 | |
| 159 | #define CONFIG_SYS_MICRON_EMR3 0x01030000 | |
| 054197ba | 160 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 |
| 52568c36 | 161 | #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 |
| 25671c86 WD |
162 | #define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ |
| 163 | (0 << 22) | /* DRAM_CS */ \ | |
| 164 | (0 << 21) | /* DRAM_RAS */ \ | |
| 165 | (0 << 20) | /* DRAM_CAS */ \ | |
| 166 | (0 << 19) | /* DRAM_WEB */ \ | |
| 167 | (1 << 16) | /* DRAM_BS[2:0] */ \ | |
| 168 | (0 << 15) | /* */ \ | |
| 169 | (0 << 12) | /* A12->out */ \ | |
| 170 | (0 << 11) | /* A11->RDQS */ \ | |
| 171 | (1 << 10) | /* A10->DQS# */ \ | |
| 172 | (7 << 7) | /* OCD program */ \ | |
| 173 | (0 << 6) | /* Rtt1 */ \ | |
| 174 | (0 << 3) | /* posted CAS# */ \ | |
| 175 | (1 << 2) | /* Rtt0 */ \ | |
| 176 | (0 << 1) | /* ODS (Output Drive Strength) */ \ | |
| 177 | (0 << 0) /* DLL */ \ | |
| 178 | ) | |
| 179 | ||
| 180 | /* | |
| 181 | * Backward compatible definitions, | |
| a47a12be | 182 | * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c |
| 25671c86 | 183 | */ |
| 054197ba MS |
184 | #define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) |
| 185 | #define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) | |
| 186 | #define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) | |
| 187 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) | |
| 52568c36 WD |
188 | |
| 189 | /* DDR Priority Manager Configuration */ | |
| 190 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 | |
| 191 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
| 192 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
| 193 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
| 194 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
| 195 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
| 196 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
| 197 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
| 198 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
| 199 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
| 200 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
| 201 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
| 202 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
| 203 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
| 204 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
| 205 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
| 206 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
| 207 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
| 208 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
| 209 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
| 210 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
| 211 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
| 212 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
| 213 | ||
| 214 | /* | |
| 215 | * NOR FLASH on the Local Bus | |
| 216 | */ | |
| 217 | #define CONFIG_SYS_FLASH_CFI /* use the CFI code */ | |
| 218 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 219 | #define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */ | |
| 220 | #define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */ | |
| 221 | ||
| 222 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 223 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 224 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
| 225 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */ | |
| 226 | ||
| 227 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 228 | ||
| a6d6d46a WD |
229 | /* |
| 230 | * NAND FLASH support | |
| 231 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) | |
| 232 | */ | |
| 1f1f82f3 WD |
233 | #define CONFIG_CMD_NAND /* enable NAND support */ |
| 234 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ | |
| a6d6d46a WD |
235 | #define CONFIG_NAND_MPC5121_NFC |
| 236 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
| a6d6d46a | 237 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| a6d6d46a | 238 | |
| a6d6d46a WD |
239 | /* |
| 240 | * Configuration parameters for MPC5121 NAND driver | |
| 241 | */ | |
| 242 | #define CONFIG_FSL_NFC_WIDTH 1 | |
| 243 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
| 244 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
| 245 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
| 246 | ||
| 52568c36 WD |
247 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
| 248 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
| 249 | ||
| 25671c86 WD |
250 | /* Make two SRAM regions contiguous */ |
| 251 | #define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ | |
| 252 | CONFIG_SYS_SRAM_SIZE) | |
| 253 | #define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ | |
| 676c6691 AG |
254 | #define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE |
| 255 | #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE | |
| 52568c36 WD |
256 | |
| 257 | #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ | |
| 258 | CONFIG_SYS_ARIA_SRAM_SIZE) | |
| 259 | #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ | |
| 260 | ||
| 676c6691 AG |
261 | #define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE |
| 262 | #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE | |
| 263 | ||
| 52568c36 WD |
264 | #define CONFIG_SYS_CS0_CFG 0x05059150 |
| 265 | #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ | |
| 266 | (5 << 16) | \ | |
| 267 | (1 << 15) | \ | |
| 268 | (0 << 14) | \ | |
| 269 | (0 << 13) | \ | |
| 270 | (1 << 12) | \ | |
| 271 | (0 << 10) | \ | |
| 272 | (3 << 8) | /* 32 bit */ \ | |
| 273 | (0 << 7) | \ | |
| 274 | (1 << 6) | \ | |
| 275 | (1 << 4) | \ | |
| 276 | (0 << 3) | \ | |
| 277 | (0 << 2) | \ | |
| 278 | (0 << 1) | \ | |
| 279 | (0 << 0) \ | |
| 280 | ) | |
| 281 | #define CONFIG_SYS_CS6_CFG 0x05059150 | |
| 282 | ||
| 283 | /* Use alternative CS timing for CS0 and CS2 */ | |
| 284 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 | |
| 285 | ||
| 286 | /* Use SRAM for initial stack */ | |
| 287 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE | |
| 553f0982 | 288 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE |
| 52568c36 | 289 | |
| 553f0982 | 290 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 25ddd1fb | 291 | GENERATED_GBL_DATA_SIZE) |
| 52568c36 WD |
292 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 293 | ||
| 14d0a02a | 294 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| a6d6d46a | 295 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) |
| 52568c36 WD |
296 | |
| 297 | #ifdef CONFIG_FSL_DIU_FB | |
| 298 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) | |
| 299 | #else | |
| 300 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
| 301 | #endif | |
| 302 | ||
| 303 | /* FPGA */ | |
| 304 | #define CONFIG_ARIA_FPGA 1 | |
| 305 | ||
| 306 | /* | |
| 307 | * Serial Port | |
| 308 | */ | |
| 309 | #define CONFIG_CONS_INDEX 1 | |
| 52568c36 WD |
310 | |
| 311 | /* | |
| 312 | * Serial console configuration | |
| 313 | */ | |
| 314 | #define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ | |
| bfb31279 | 315 | #define CONFIG_SYS_PSC3 |
| 52568c36 WD |
316 | #if CONFIG_PSC_CONSOLE != 3 |
| 317 | #error CONFIG_PSC_CONSOLE must be 3 | |
| 318 | #endif | |
| 319 | ||
| 320 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
| 321 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 322 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 323 | ||
| 324 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
| 325 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
| 326 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
| 327 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
| 328 | ||
| 329 | #define CONFIG_CMDLINE_EDITING 1 /* command line history */ | |
| 330 | /* Use the HUSH parser */ | |
| 331 | #define CONFIG_SYS_HUSH_PARSER | |
| 332 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 52568c36 WD |
333 | #endif |
| 334 | ||
| 335 | /* | |
| 336 | * PCI | |
| 337 | */ | |
| 338 | #ifdef CONFIG_PCI | |
| 842033e6 | 339 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 52568c36 WD |
340 | |
| 341 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 | |
| 342 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
| 343 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
| 344 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \ | |
| 345 | CONFIG_SYS_PCI_MEM_SIZE) | |
| 346 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
| 347 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
| 348 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
| 349 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
| 350 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
| 351 | ||
| 352 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 353 | ||
| 354 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 355 | ||
| 356 | #endif | |
| 357 | ||
| 358 | /* I2C */ | |
| 359 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 52568c36 | 360 | #define CONFIG_I2C_MULTI_BUS |
| 52568c36 WD |
361 | |
| 362 | /* I2C speed and slave address */ | |
| 363 | #define CONFIG_SYS_I2C_SPEED 100000 | |
| 364 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 365 | #if 0 | |
| 366 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
| 367 | #endif | |
| 368 | ||
| 369 | /* | |
| 370 | * IIM - IC Identification Module | |
| 371 | */ | |
| 83306927 | 372 | #undef CONFIG_FSL_IIM |
| 52568c36 WD |
373 | |
| 374 | /* | |
| 375 | * EEPROM configuration for Atmel AT24C32A-10TQ-2.7: | |
| 376 | * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode | |
| 377 | */ | |
| 378 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 379 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
| 380 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 381 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
| 382 | ||
| 383 | /* | |
| 384 | * Ethernet configuration | |
| 385 | */ | |
| 386 | #define CONFIG_MPC512x_FEC 1 | |
| 52568c36 WD |
387 | #define CONFIG_PHY_ADDR 0x17 |
| 388 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 389 | #define CONFIG_FEC_AN_TIMEOUT 1 | |
| 390 | #define CONFIG_HAS_ETH0 | |
| 391 | ||
| 392 | /* | |
| 393 | * Environment | |
| 394 | */ | |
| 395 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 396 | /* This has to be a multiple of the flash sector size */ | |
| 397 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
| 398 | CONFIG_SYS_MONITOR_LEN) | |
| 399 | #define CONFIG_ENV_SIZE 0x2000 | |
| 400 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */ | |
| 401 | ||
| 402 | /* Address and size of Redundant Environment Sector */ | |
| 403 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ | |
| 404 | CONFIG_ENV_SECT_SIZE) | |
| 405 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 406 | ||
| 407 | #define CONFIG_LOADS_ECHO 1 | |
| 408 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 | |
| 409 | ||
| 410 | #include <config_cmd_default.h> | |
| 411 | ||
| 412 | #define CONFIG_CMD_ASKENV | |
| 413 | #define CONFIG_CMD_DHCP | |
| 414 | #define CONFIG_CMD_EEPROM | |
| 415 | #undef CONFIG_CMD_FUSE | |
| 416 | #define CONFIG_CMD_I2C | |
| 417 | #undef CONFIG_CMD_IDE | |
| 1f1f82f3 | 418 | #define CONFIG_CMD_JFFS2 |
| 52568c36 WD |
419 | #define CONFIG_CMD_MII |
| 420 | #define CONFIG_CMD_NFS | |
| 421 | #define CONFIG_CMD_PING | |
| 422 | #define CONFIG_CMD_REGINFO | |
| 423 | ||
| 424 | #if defined(CONFIG_PCI) | |
| 425 | #define CONFIG_CMD_PCI | |
| 426 | #endif | |
| 427 | ||
| 1f1f82f3 | 428 | #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) |
| 52568c36 WD |
429 | #define CONFIG_DOS_PARTITION |
| 430 | #define CONFIG_MAC_PARTITION | |
| 431 | #define CONFIG_ISO_PARTITION | |
| 432 | #endif /* defined(CONFIG_CMD_IDE) */ | |
| 433 | ||
| 1f1f82f3 WD |
434 | /* |
| 435 | * Dynamic MTD partition support | |
| 436 | */ | |
| 437 | #define CONFIG_CMD_MTDPARTS | |
| 438 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
| 439 | #define CONFIG_FLASH_CFI_MTD | |
| 440 | #define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand" | |
| 441 | ||
| 442 | /* | |
| 443 | * NOR flash layout: | |
| 444 | * | |
| 445 | * F8000000 - FEAFFFFF 107 MiB User Data | |
| 446 | * FEB00000 - FFAFFFFF 16 MiB Root File System | |
| 447 | * FFB00000 - FFFEFFFF 4 MiB Linux Kernel | |
| 448 | * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env | |
| 449 | * FFFC0000 - FFFFFFFF 256 KiB Device Tree | |
| 450 | * | |
| 451 | * NAND flash layout: one big partition | |
| 452 | */ | |
| 453 | #define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \ | |
| 454 | "16m(rootfs)," \ | |
| 455 | "4m(kernel)," \ | |
| 456 | "768k(u-boot)," \ | |
| 457 | "256k(dtb);" \ | |
| 458 | "mpc5121.nand:-(data)" | |
| 459 | ||
| 52568c36 WD |
460 | /* |
| 461 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. | |
| 462 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE | |
| 463 | * is set to 0xFFFF, watchdog timeouts after about 64s. For details | |
| 464 | * refer to chapter 36 of the MPC5121e Reference Manual. | |
| 465 | */ | |
| 466 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ | |
| 467 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF | |
| 468 | ||
| 469 | /* | |
| 470 | * Miscellaneous configurable options | |
| 471 | */ | |
| 472 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 473 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 52568c36 WD |
474 | |
| 475 | #ifdef CONFIG_CMD_KGDB | |
| 476 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 477 | #else | |
| 478 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 479 | #endif | |
| 480 | ||
| 481 | /* Print Buffer Size */ | |
| 482 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
| 483 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 484 | /* max number of command args */ | |
| 485 | #define CONFIG_SYS_MAXARGS 32 | |
| 486 | /* Boot Argument Buffer Size */ | |
| 487 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 488 | ||
| 52568c36 WD |
489 | /* |
| 490 | * For booting Linux, the board info and command line data | |
| 9f530d59 | 491 | * have to be in the first 256 MB of memory, since this is |
| 52568c36 WD |
492 | * the maximum mapped by the Linux kernel during initialization. |
| 493 | */ | |
| 9f530d59 | 494 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
| 52568c36 WD |
495 | |
| 496 | /* Cache Configuration */ | |
| 497 | #define CONFIG_SYS_DCACHE_SIZE 32768 | |
| 498 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
| 499 | #ifdef CONFIG_CMD_KGDB | |
| 500 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ | |
| 501 | #endif | |
| 502 | ||
| 503 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
| 504 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
| 505 | HID0_ICE) | |
| 506 | #define CONFIG_SYS_HID2 HID2_HBE | |
| 507 | ||
| 508 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
| 509 | ||
| 52568c36 WD |
510 | #ifdef CONFIG_CMD_KGDB |
| 511 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
| 52568c36 WD |
512 | #endif |
| 513 | ||
| 514 | /* | |
| 515 | * Environment Configuration | |
| 516 | */ | |
| 517 | #define CONFIG_ENV_OVERWRITE | |
| 518 | #define CONFIG_TIMESTAMP | |
| 519 | ||
| 520 | #define CONFIG_HOSTNAME aria | |
| b3f44c21 | 521 | #define CONFIG_BOOTFILE "aria/uImage" |
| 8b3637c6 | 522 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
| 52568c36 WD |
523 | |
| 524 | #define CONFIG_LOADADDR 400000 /* default load addr */ | |
| 525 | ||
| 526 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ | |
| 527 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 528 | ||
| 529 | #define CONFIG_BAUDRATE 115200 | |
| 530 | ||
| 531 | #define CONFIG_PREBOOT "echo;" \ | |
| 532 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
| 533 | "echo" | |
| 534 | ||
| 535 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 536 | "u-boot_addr_r=200000\0" \ | |
| 537 | "kernel_addr_r=600000\0" \ | |
| 538 | "fdt_addr_r=880000\0" \ | |
| 539 | "ramdisk_addr_r=900000\0" \ | |
| 540 | "u-boot_addr=FFF00000\0" \ | |
| 1f1f82f3 WD |
541 | "kernel_addr=FFB00000\0" \ |
| 542 | "fdt_addr=FFFC0000\0" \ | |
| 543 | "ramdisk_addr=FEB00000\0" \ | |
| 52568c36 WD |
544 | "ramdiskfile=aria/uRamdisk\0" \ |
| 545 | "u-boot=aria/u-boot.bin\0" \ | |
| 546 | "fdtfile=aria/aria.dtb\0" \ | |
| 547 | "netdev=eth0\0" \ | |
| 548 | "consdev=ttyPSC0\0" \ | |
| 549 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 550 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 551 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 552 | "addip=setenv bootargs ${bootargs} " \ | |
| 553 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 554 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 555 | "addtty=setenv bootargs ${bootargs} " \ | |
| 556 | "console=${consdev},${baudrate}\0" \ | |
| 557 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 558 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
| 559 | "flash_self=run ramargs addip addtty;" \ | |
| 560 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
| 561 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
| 562 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
| 563 | "run nfsargs addip addtty;" \ | |
| 564 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
| 565 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
| 566 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
| 567 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
| 568 | "run ramargs addip addtty;" \ | |
| 569 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ | |
| 570 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
| 571 | "update=protect off ${u-boot_addr} +${filesize};" \ | |
| 572 | "era ${u-boot_addr} +${filesize};" \ | |
| 573 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
| 574 | "upd=run load update\0" \ | |
| 575 | "" | |
| 576 | ||
| 577 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 578 | ||
| 579 | #define CONFIG_OF_LIBFDT 1 | |
| 580 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 581 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 | |
| 582 | ||
| 583 | #define OF_CPU "PowerPC,5121@0" | |
| 584 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" | |
| 585 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
| 586 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" | |
| 587 | ||
| 588 | /*----------------------------------------------------------------------- | |
| 589 | * IDE/ATA stuff | |
| 590 | *----------------------------------------------------------------------- | |
| 591 | */ | |
| 592 | ||
| 593 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
| 594 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 595 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ | |
| 596 | ||
| 597 | #define CONFIG_IDE_RESET /* reset for IDE supported */ | |
| 598 | #define CONFIG_IDE_PREINIT | |
| 599 | ||
| 600 | #define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ | |
| 601 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */ | |
| 602 | ||
| 603 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
| 604 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() | |
| 605 | ||
| 606 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ | |
| 607 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) | |
| 608 | ||
| 609 | /* Offset for normal register accesses */ | |
| 610 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
| 611 | ||
| 612 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ | |
| 613 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) | |
| 614 | ||
| 615 | /* Interval between registers */ | |
| 616 | #define CONFIG_SYS_ATA_STRIDE 4 | |
| 617 | ||
| 618 | #define ATA_BASE_ADDR get_pata_base() | |
| 619 | ||
| 620 | /* | |
| 621 | * Control register bit definitions | |
| 622 | */ | |
| 623 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 | |
| 624 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 | |
| 625 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 | |
| 626 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 | |
| 627 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 | |
| 628 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 | |
| 629 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 | |
| 630 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 | |
| 631 | ||
| e5f53864 AG |
632 | /* Clocks in use */ |
| 633 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ | |
| 634 | CLOCK_SCCR1_LPC_EN | \ | |
| 635 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ | |
| 636 | CLOCK_SCCR1_PSCFIFO_EN | \ | |
| 637 | CLOCK_SCCR1_DDR_EN | \ | |
| 638 | CLOCK_SCCR1_FEC_EN | \ | |
| 639 | CLOCK_SCCR1_NFC_EN | \ | |
| 640 | CLOCK_SCCR1_PATA_EN | \ | |
| 641 | CLOCK_SCCR1_PCI_EN | \ | |
| 642 | CLOCK_SCCR1_TPR_EN) | |
| 643 | ||
| 644 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ | |
| 645 | CLOCK_SCCR2_SPDIF_EN | \ | |
| 646 | CLOCK_SCCR2_DIU_EN | \ | |
| 647 | CLOCK_SCCR2_I2C_EN) | |
| 648 | ||
| 52568c36 | 649 | #endif /* __CONFIG_H */ |