[J-u-boot.git] / board / renesas / sh7757lcr / sh7757lcr.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2011  Renesas Solutions Corp.
 */

#include <common.h>
#include <env.h>
#include <flash.h>
#include <init.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmc.h>
#include <spi.h>
#include <spi_flash.h>

int checkboard(void)
{
	puts("BOARD: R0P7757LC0030RL board\n");

	return 0;
}

static void init_gctrl(void)
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	unsigned long graofst;

	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	writel(graofst | 0x20000f00, &gctrl->gracr3);
}

static int init_pcie_bridge_from_spi(void *buf, size_t size)
{
#ifdef CONFIG_DEPRECATED
	struct spi_flash *spi;
	int ret;
	unsigned long pcie_addr;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	if (is_sh7757_b0())
		pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
	else
		pcie_addr = SH7757LCR_PCIEBRG_ADDR;

	ret = spi_flash_read(spi, pcie_addr, size, buf);
	if (ret) {
		printf("%s: spi_flash read error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	return 0;
#else
	printf("No SPI support so no PCIe support\n");
	return 1;
#endif
}

static void init_pcie_bridge(void)
{
	struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	int i;
	unsigned char *data;
	unsigned short tmp;
	unsigned long pcie_size;

	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
		return;

	if (is_sh7757_b0())
		pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
	else
		pcie_size = SH7757LCR_PCIEBRG_SIZE;

	data = malloc(pcie_size);
	if (!data) {
		printf("%s: malloc error.\n", __func__);
		return;
	}
	if (init_pcie_bridge_from_spi(data, pcie_size)) {
		free(data);
		return;
	}

	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
	    data[3] == 0xff) {
		free(data);
		printf("%s: skipped initialization\n", __func__);
		return;
	}

	writew(0xa501, &pciebrg->ctrl_h8s);	/* reset */
	writew(0x0000, &pciebrg->cp_ctrl);
	writew(0x0000, &pciebrg->cp_addr);

	for (i = 0; i < pcie_size; i += 2) {
		tmp = (data[i] << 8) | data[i + 1];
		writew(tmp, &pciebrg->cp_data);
	}

	writew(0xa500, &pciebrg->ctrl_h8s);	/* start */
	if (!is_sh7757_b0())
		writel(0x00000001, &pcie_setup->pbictl3);

	free(data);
}

static void init_usb_phy(void)
{
	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	struct usb1_port_regs *port = USB1_PORT_BASE;
	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;

	writew(0x0100, &phy->reset);		/* set reset */
	/* port0 = USB0, port1 = USB1 */
	writew(0x0002, &phy->portsel);
	writel(0x0001, &port->port1sel);	/* port1 = Host */
	writew(0x0111, &phy->reset);		/* clear reset */

	writew(0x4000, &common0->suspmode);
	writew(0x4000, &common1->suspmode);

#if defined(__LITTLE_ENDIAN)
	writel(0x00000000, &align->ehcidatac);
	writel(0x00000000, &align->ohcidatac);
#endif
}

static void set_mac_to_sh_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	string_to_enetaddr(mac_string, mac);

	if (!channel)
		ether = ETHER0_MAC_BASE;
	else
		ether = ETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	string_to_enetaddr(mac_string, mac);

	if (!channel)
		ether = GETHER0_MAC_BASE;
	else
		ether = GETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

/*****************************************************************
 * This PMB must be set on this timing. The lowlevel_init is run on
 * Area 0(phys 0x00000000), so we have to map it.
 *
 * The new PMB table is following:
 * ent	virt		phys		v	sz	c	wt
 * 0	0xa0000000	0x40000000	1	128M	0	1
 * 1	0xa8000000	0x48000000	1	128M	0	1
 * 2	0xb0000000	0x50000000	1	128M	0	1
 * 3	0xb8000000	0x58000000	1	128M	0	1
 * 4	0x80000000	0x40000000	1	128M	1	1
 * 5	0x88000000	0x48000000	1	128M	1	1
 * 6	0x90000000	0x50000000	1	128M	1	1
 * 7	0x98000000	0x58000000	1	128M	1	1
 */
static void set_pmb_on_board_init(void)
{
	struct mmu_regs *mmu = MMU_BASE;

	/* clear ITLB */
	writel(0x00000004, &mmu->mmucr);

	/* delete PMB for SPIBOOT */
	writel(0, PMB_ADDR_BASE(0));
	writel(0, PMB_DATA_BASE(0));

	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	/*			ppn  ub v s1 s0  c  wt */
	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
}

int board_init(void)
{
	struct gether_control_regs *gether = GETHER_CONTROL_BASE;

	set_pmb_on_board_init();

	/* enable RMII's MDIO (disable GRMII's MDIO) */
	writel(0x00030000, &gether->gbecont);

	init_gctrl();
	init_usb_phy();

	return 0;
}

int board_mmc_init(bd_t *bis)
{
	return mmcif_mmc_init();
}

static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
#ifdef CONFIG_DEPRECATED
	struct spi_flash *spi;
	int ret;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (spi == NULL) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
	if (ret) {
		printf("%s: spi_flash read error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);
#endif

	return 0;
}

static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
{
	memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
		SH7757LCR_ETHERNET_MAC_SIZE);
	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */

	return 0;
}

static void init_ethernet_mac(void)
{
	char mac_string[64];
	char env_string[64];
	int i;
	unsigned char *buf;

	buf = malloc(256);
	if (!buf) {
		printf("%s: malloc error.\n", __func__);
		return;
	}
	get_sh_eth_mac_raw(buf, 256);

	/* Fast Ethernet */
	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i, mac_string, buf);
		if (i == 0)
			env_set("ethaddr", mac_string);
		else {
			sprintf(env_string, "eth%daddr", i);
			env_set(env_string, mac_string);
		}

		set_mac_to_sh_eth_register(i, mac_string);
	}

	/* Gigabit Ethernet */
	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
		sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
		env_set(env_string, mac_string);

		set_mac_to_sh_giga_eth_register(i, mac_string);
	}

	free(buf);
}

static void init_pcie(void)
{
	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;

	writel(0x00000ff2, &pcie_setup->ladmsk0);
	writel(0x00000001, &pcie_setup->barmap);
	writel(0xffcaa000, &pcie_setup->lad0);
	writel(0x00030000, &pcie_sysbus->endictl0);
	writel(0x00000003, &pcie_sysbus->endictl1);
	writel(0x00000004, &pcie_setup->pbictl2);
}

static void finish_spiboot(void)
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	/*
	 *  SH7757 B0 does not use LBSC.
	 *  So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
	 *  This setting is not cleared by manual reset, So we have to set it
	 *  to 0.
	 */
	writel(0x00000000, &gctrl->spibootcan);
}

int board_late_init(void)
{
	init_ethernet_mac();
	init_pcie_bridge();
	init_pcie();
	finish_spiboot();

	return 0;
}

int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	unsigned long graofst;

	writel(0xfedcba98, &gctrl->wprotect);
	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	writel(graofst | 0xa0000f00, &gctrl->gracr3);

	return 0;
}

U_BOOT_CMD(
	sh_g200,	1,	1,	do_sh_g200,
	"enable sh-g200",
	"enable SH-G200 bus (disable PCIe-G200)"
);

#ifdef CONFIG_DEPRECATED
int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int i, ret;
	char mac_string[256];
	struct spi_flash *spi;
	unsigned char *buf;

	if (argc != 5) {
		buf = malloc(256);
		if (!buf) {
			printf("%s: malloc error.\n", __func__);
			return 1;
		}

		get_sh_eth_mac_raw(buf, 256);

		/* print current MAC address */
		for (i = 0; i < 4; i++) {
			get_sh_eth_mac(i, mac_string, buf);
			if (i < 2)
				printf(" ETHERC ch%d = %s\n", i, mac_string);
			else
				printf("GETHERC ch%d = %s\n", i-2, mac_string);
		}
		free(buf);
		return 0;
	}

	/* new setting */
	memset(mac_string, 0xff, sizeof(mac_string));
	sprintf(mac_string, "%s\t%s\t%s\t%s",
		argv[1], argv[2], argv[3], argv[4]);

	/* write MAC data to SPI rom */
	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
				SH7757LCR_SPI_SECTOR_SIZE);
	if (ret) {
		printf("%s: spi_flash erase error.\n", __func__);
		return 1;
	}

	ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
				sizeof(mac_string), mac_string);
	if (ret) {
		printf("%s: spi_flash write error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	puts("The writing of the MAC address to SPI ROM was completed.\n");

	return 0;
}

U_BOOT_CMD(
	write_mac,	5,	1,	do_write_mac,
	"write MAC address for ETHERC/GETHERC",
	"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8e9c897b YS	2	/*
8e9c897b YS	3	* Copyright (C) 2011 Renesas Solutions Corp.
8e9c897b YS	4	*/
	5
	6	#include <common.h>
9fb625ce	7	#include <env.h>
b79fdc76	8	#include <flash.h>
5255932f	9	#include <init.h>
8e9c897b YS	10	#include <malloc.h>
	11	#include <asm/processor.h>
	12	#include <asm/io.h>
4f0e8477	13	#include <asm/mmc.h>
ff0960f9	14	#include <spi.h>
8e9c897b YS	15	#include <spi_flash.h>
	16
	17	int checkboard(void)
	18	{
	19	puts("BOARD: R0P7757LC0030RL board\n");
	20
	21	return 0;
	22	}
	23
	24	static void init_gctrl(void)
	25	{
	26	struct gctrl_regs *gctrl = GCTRL_BASE;
	27	unsigned long graofst;
	28
	29	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	30	writel(graofst \| 0x20000f00, &gctrl->gracr3);
	31	}
	32
	33	static int init_pcie_bridge_from_spi(void *buf, size_t size)
	34	{
88369d33	35	#ifdef CONFIG_DEPRECATED
8e9c897b YS	36	struct spi_flash *spi;
	37	int ret;
	38	unsigned long pcie_addr;
	39
	40	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	41	if (!spi) {
	42	printf("%s: spi_flash probe error.\n", __func__);
	43	return 1;
	44	}
	45
	46	if (is_sh7757_b0())
	47	pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
	48	else
	49	pcie_addr = SH7757LCR_PCIEBRG_ADDR;
	50
	51	ret = spi_flash_read(spi, pcie_addr, size, buf);
	52	if (ret) {
	53	printf("%s: spi_flash read error.\n", __func__);
	54	spi_flash_free(spi);
	55	return 1;
	56	}
	57	spi_flash_free(spi);
	58
	59	return 0;
88369d33 TR	60	#else
	61	printf("No SPI support so no PCIe support\n");
	62	return 1;
	63	#endif
8e9c897b YS	64	}
	65
	66	static void init_pcie_bridge(void)
	67	{
	68	struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
	69	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	70	int i;
	71	unsigned char *data;
	72	unsigned short tmp;
	73	unsigned long pcie_size;
	74
	75	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
	76	return;
	77
	78	if (is_sh7757_b0())
	79	pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
	80	else
	81	pcie_size = SH7757LCR_PCIEBRG_SIZE;
	82
	83	data = malloc(pcie_size);
	84	if (!data) {
	85	printf("%s: malloc error.\n", __func__);
	86	return;
	87	}
	88	if (init_pcie_bridge_from_spi(data, pcie_size)) {
	89	free(data);
	90	return;
	91	}
	92
	93	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
	94	data[3] == 0xff) {
	95	free(data);
	96	printf("%s: skipped initialization\n", __func__);
	97	return;
	98	}
	99
	100	writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
	101	writew(0x0000, &pciebrg->cp_ctrl);
	102	writew(0x0000, &pciebrg->cp_addr);
	103
	104	for (i = 0; i < pcie_size; i += 2) {
	105	tmp = (data[i] << 8) \| data[i + 1];
	106	writew(tmp, &pciebrg->cp_data);
	107	}
	108
	109	writew(0xa500, &pciebrg->ctrl_h8s); /* start */
	110	if (!is_sh7757_b0())
	111	writel(0x00000001, &pcie_setup->pbictl3);
	112
	113	free(data);
	114	}
	115
	116	static void init_usb_phy(void)
	117	{
	118	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	119	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	120	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	121	struct usb1_port_regs *port = USB1_PORT_BASE;
	122	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
	123
	124	writew(0x0100, &phy->reset); /* set reset */
	125	/* port0 = USB0, port1 = USB1 */
	126	writew(0x0002, &phy->portsel);
	127	writel(0x0001, &port->port1sel); /* port1 = Host */
128	writew(0x0111, &phy->reset); /* clear reset */
129
130	writew(0x4000, &common0->suspmode);
131	writew(0x4000, &common1->suspmode);
132
133	#if defined(__LITTLE_ENDIAN)
134	writel(0x00000000, &align->ehcidatac);
135	writel(0x00000000, &align->ohcidatac);
136	#endif
137	}
138
139	static void set_mac_to_sh_eth_register(int channel, char *mac_string)
140	{
141	struct ether_mac_regs *ether;
142	unsigned char mac[6];
143	unsigned long val;
144
fb8977c5	145	string_to_enetaddr(mac_string, mac);
8e9c897b YS	146
	147	if (!channel)
	148	ether = ETHER0_MAC_BASE;
	149	else
	150	ether = ETHER1_MAC_BASE;
	151
	152	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
	153	writel(val, &ether->mahr);
	154	val = (mac[4] << 8) \| mac[5];
	155	writel(val, &ether->malr);
	156	}
	157
	158	static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
	159	{
	160	struct ether_mac_regs *ether;
	161	unsigned char mac[6];
	162	unsigned long val;
	163
fb8977c5	164	string_to_enetaddr(mac_string, mac);
8e9c897b YS	165
	166	if (!channel)
	167	ether = GETHER0_MAC_BASE;
	168	else
	169	ether = GETHER1_MAC_BASE;
	170
	171	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
	172	writel(val, &ether->mahr);
	173	val = (mac[4] << 8) \| mac[5];
	174	writel(val, &ether->malr);
	175	}
	176
	177	/*****************************************************************
	178	* This PMB must be set on this timing. The lowlevel_init is run on
	179	* Area 0(phys 0x00000000), so we have to map it.
	180	*
	181	* The new PMB table is following:
	182	* ent virt phys v sz c wt
	183	* 0 0xa0000000 0x40000000 1 128M 0 1
	184	* 1 0xa8000000 0x48000000 1 128M 0 1
	185	* 2 0xb0000000 0x50000000 1 128M 0 1
	186	* 3 0xb8000000 0x58000000 1 128M 0 1
	187	* 4 0x80000000 0x40000000 1 128M 1 1
	188	* 5 0x88000000 0x48000000 1 128M 1 1
	189	* 6 0x90000000 0x50000000 1 128M 1 1
	190	* 7 0x98000000 0x58000000 1 128M 1 1
	191	*/
	192	static void set_pmb_on_board_init(void)
	193	{
	194	struct mmu_regs *mmu = MMU_BASE;
	195
	196	/* clear ITLB */
	197	writel(0x00000004, &mmu->mmucr);
	198
	199	/* delete PMB for SPIBOOT */
	200	writel(0, PMB_ADDR_BASE(0));
	201	writel(0, PMB_DATA_BASE(0));
	202
	203	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	204	/* ppn ub v s1 s0 c wt */
	205	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	206	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	207	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	208	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	209	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	210	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	211	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	212	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	213	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	214	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	215	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	216	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
	217	}
	218
	219	int board_init(void)
	220	{
	221	struct gether_control_regs *gether = GETHER_CONTROL_BASE;
	222
	223	set_pmb_on_board_init();
	224
	225	/* enable RMII's MDIO (disable GRMII's MDIO) */
	226	writel(0x00030000, &gether->gbecont);
	227
	228	init_gctrl();
229	init_usb_phy();
230
231	return 0;
232	}
233
566f63d5 YS	234	int board_mmc_init(bd_t *bis)
	235	{
	236	return mmcif_mmc_init();
	237	}
	238
8e9c897b YS	239	static int get_sh_eth_mac_raw(unsigned char *buf, int size)
8e9c897b YS	240	{
88369d33	241	#ifdef CONFIG_DEPRECATED
8e9c897b YS	242	struct spi_flash *spi;
	243	int ret;
	244
	245	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	246	if (spi == NULL) {
	247	printf("%s: spi_flash probe error.\n", __func__);
	248	return 1;
	249	}
	250
	251	ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
	252	if (ret) {
	253	printf("%s: spi_flash read error.\n", __func__);
	254	spi_flash_free(spi);
	255	return 1;
	256	}
	257	spi_flash_free(spi);
88369d33	258	#endif
8e9c897b YS	259
	260	return 0;
	261	}
	262
	263	static int get_sh_eth_mac(int channel, char mac_string, unsigned char buf)
	264	{
	265	memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
	266	SH7757LCR_ETHERNET_MAC_SIZE);
	267	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
	268
	269	return 0;
	270	}
	271
	272	static void init_ethernet_mac(void)
	273	{
	274	char mac_string[64];
	275	char env_string[64];
	276	int i;
	277	unsigned char *buf;
	278
	279	buf = malloc(256);
	280	if (!buf) {
	281	printf("%s: malloc error.\n", __func__);
	282	return;
	283	}
	284	get_sh_eth_mac_raw(buf, 256);
	285
	286	/* Fast Ethernet */
	287	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
	288	get_sh_eth_mac(i, mac_string, buf);
	289	if (i == 0)
382bee57	290	env_set("ethaddr", mac_string);
8e9c897b YS	291	else {
8e9c897b YS	292	sprintf(env_string, "eth%daddr", i);
382bee57	293	env_set(env_string, mac_string);
8e9c897b YS	294	}
	295
	296	set_mac_to_sh_eth_register(i, mac_string);
	297	}
	298
	299	/* Gigabit Ethernet */
	300	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
	301	get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
	302	sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
382bee57	303	env_set(env_string, mac_string);
8e9c897b YS	304
	305	set_mac_to_sh_giga_eth_register(i, mac_string);
	306	}
	307
	308	free(buf);
	309	}
	310
	311	static void init_pcie(void)
	312	{
	313	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	314	struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
	315
	316	writel(0x00000ff2, &pcie_setup->ladmsk0);
	317	writel(0x00000001, &pcie_setup->barmap);
	318	writel(0xffcaa000, &pcie_setup->lad0);
	319	writel(0x00030000, &pcie_sysbus->endictl0);
	320	writel(0x00000003, &pcie_sysbus->endictl1);
	321	writel(0x00000004, &pcie_setup->pbictl2);
	322	}
	323
	324	static void finish_spiboot(void)
	325	{
	326	struct gctrl_regs *gctrl = GCTRL_BASE;
	327	/*
	328	* SH7757 B0 does not use LBSC.
	329	* So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
	330	* This setting is not cleared by manual reset, So we have to set it
	331	* to 0.
	332	*/
	333	writel(0x00000000, &gctrl->spibootcan);
	334	}
	335
	336	int board_late_init(void)
	337	{
	338	init_ethernet_mac();
	339	init_pcie_bridge();
	340	init_pcie();
	341	finish_spiboot();
	342
	343	return 0;
	344	}
	345
	346	int do_sh_g200(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	347	{
	348	struct gctrl_regs *gctrl = GCTRL_BASE;
	349	unsigned long graofst;
	350
	351	writel(0xfedcba98, &gctrl->wprotect);
	352	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	353	writel(graofst \| 0xa0000f00, &gctrl->gracr3);
	354
	355	return 0;
	356	}
	357
	358	U_BOOT_CMD(
	359	sh_g200, 1, 1, do_sh_g200,
	360	"enable sh-g200",
	361	"enable SH-G200 bus (disable PCIe-G200)"
	362	);
	363
88369d33	364	#ifdef CONFIG_DEPRECATED
8e9c897b YS	365	int do_write_mac(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	366	{
	367	int i, ret;
	368	char mac_string[256];
	369	struct spi_flash *spi;
	370	unsigned char *buf;
	371
	372	if (argc != 5) {
	373	buf = malloc(256);
	374	if (!buf) {
	375	printf("%s: malloc error.\n", __func__);
	376	return 1;
	377	}
	378
	379	get_sh_eth_mac_raw(buf, 256);
	380
	381	/* print current MAC address */
	382	for (i = 0; i < 4; i++) {
	383	get_sh_eth_mac(i, mac_string, buf);
	384	if (i < 2)
	385	printf(" ETHERC ch%d = %s\n", i, mac_string);
	386	else
	387	printf("GETHERC ch%d = %s\n", i-2, mac_string);
	388	}
	389	free(buf);
	390	return 0;
	391	}
	392
	393	/* new setting */
	394	memset(mac_string, 0xff, sizeof(mac_string));
	395	sprintf(mac_string, "%s\t%s\t%s\t%s",
	396	argv[1], argv[2], argv[3], argv[4]);
	397
	398	/* write MAC data to SPI rom */
	399	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	400	if (!spi) {
	401	printf("%s: spi_flash probe error.\n", __func__);
	402	return 1;
	403	}
	404
	405	ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
	406	SH7757LCR_SPI_SECTOR_SIZE);
	407	if (ret) {
	408	printf("%s: spi_flash erase error.\n", __func__);
	409	return 1;
	410	}
	411
	412	ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
	413	sizeof(mac_string), mac_string);
	414	if (ret) {
	415	printf("%s: spi_flash write error.\n", __func__);
	416	spi_flash_free(spi);
	417	return 1;
	418	}
	419	spi_flash_free(spi);
	420
	421	puts("The writing of the MAC address to SPI ROM was completed.\n");
	422
	423	return 0;
	424	}
	425
	426	U_BOOT_CMD(
	427	write_mac, 5, 1, do_write_mac,
	428	"write MAC address for ETHERC/GETHERC",
429	"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
430	);
88369d33	431	#endif