[J-u-boot.git] / board / renesas / sh7753evb / sh7753evb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2012  Renesas Solutions Corp.
 */

#include <common.h>
#include <env.h>
#include <flash.h>
#include <init.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmc.h>
#include <spi.h>
#include <spi_flash.h>

int checkboard(void)
{
	puts("BOARD: SH7753 EVB\n");

	return 0;
}

static void init_gpio(void)
{
	struct gpio_regs *gpio = GPIO_BASE;
	struct sermux_regs *sermux = SERMUX_BASE;

	/* GPIO */
	writew(0x0000, &gpio->pacr);	/* GETHER */
	writew(0x0001, &gpio->pbcr);	/* INTC */
	writew(0x0000, &gpio->pccr);	/* PWMU, INTC */
	writew(0x0000, &gpio->pdcr);	/* SPI0 */
	writew(0xeaff, &gpio->pecr);	/* GPIO */
	writew(0x0000, &gpio->pfcr);	/* WDT */
	writew(0x0004, &gpio->pgcr);	/* SPI0, GETHER MDIO gate(PTG1) */
	writew(0x0000, &gpio->phcr);	/* SPI1 */
	writew(0x0000, &gpio->picr);	/* SDHI */
	writew(0x0000, &gpio->pjcr);	/* SCIF4 */
	writew(0x0003, &gpio->pkcr);	/* SerMux */
	writew(0x0000, &gpio->plcr);	/* SerMux */
	writew(0x0000, &gpio->pmcr);	/* RIIC */
	writew(0x0000, &gpio->pncr);	/* USB, SGPIO */
	writew(0x0000, &gpio->pocr);	/* SGPIO */
	writew(0xd555, &gpio->pqcr);	/* GPIO */
	writew(0x0000, &gpio->prcr);	/* RIIC */
	writew(0x0000, &gpio->pscr);	/* RIIC */
	writew(0x0000, &gpio->ptcr);	/* STATUS */
	writeb(0x00, &gpio->pudr);
	writew(0x5555, &gpio->pucr);	/* Debug LED */
	writew(0x0000, &gpio->pvcr);	/* RSPI */
	writew(0x0000, &gpio->pwcr);	/* EVC */
	writew(0x0000, &gpio->pxcr);	/* LBSC */
	writew(0x0000, &gpio->pycr);	/* LBSC */
	writew(0x0000, &gpio->pzcr);	/* eMMC */
	writew(0xfe00, &gpio->psel0);
	writew(0x0000, &gpio->psel1);
	writew(0x3000, &gpio->psel2);
	writew(0xff00, &gpio->psel3);
	writew(0x771f, &gpio->psel4);
	writew(0x0ffc, &gpio->psel5);
	writew(0x00ff, &gpio->psel6);
	writew(0xfc00, &gpio->psel7);

	writeb(0x10, &sermux->smr0);	/* SMR0: SerMux mode 0 */
}

static void init_usb_phy(void)
{
	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	struct usb1_port_regs *port = USB1_PORT_BASE;
	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;

	writew(0x0100, &phy->reset);		/* set reset */
	/* port0 = USB0, port1 = USB1 */
	writew(0x0002, &phy->portsel);
	writel(0x0001, &port->port1sel);	/* port1 = Host */
	writew(0x0111, &phy->reset);		/* clear reset */

	writew(0x4000, &common0->suspmode);
	writew(0x4000, &common1->suspmode);

#if defined(__LITTLE_ENDIAN)
	writel(0x00000000, &align->ehcidatac);
	writel(0x00000000, &align->ohcidatac);
#endif
}

static void init_gether_mdio(void)
{
	struct gpio_regs *gpio = GPIO_BASE;

	writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
	writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr);	/* Use ET0-MDIO */
}

static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	string_to_enetaddr(mac_string, mac);

	if (!channel)
		ether = GETHER0_MAC_BASE;
	else
		ether = GETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

#if defined(CONFIG_SH_32BIT)
/*****************************************************************
 * This PMB must be set on this timing. The lowlevel_init is run on
 * Area 0(phys 0x00000000), so we have to map it.
 *
 * The new PMB table is following:
 * ent	virt		phys		v	sz	c	wt
 * 0	0xa0000000	0x40000000	1	128M	0	1
 * 1	0xa8000000	0x48000000	1	128M	0	1
 * 2	0xb0000000	0x50000000	1	128M	0	1
 * 3	0xb8000000	0x58000000	1	128M	0	1
 * 4	0x80000000	0x40000000	1	128M	1	1
 * 5	0x88000000	0x48000000	1	128M	1	1
 * 6	0x90000000	0x50000000	1	128M	1	1
 * 7	0x98000000	0x58000000	1	128M	1	1
 */
static void set_pmb_on_board_init(void)
{
	struct mmu_regs *mmu = MMU_BASE;

	/* clear ITLB */
	writel(0x00000004, &mmu->mmucr);

	/* delete PMB for SPIBOOT */
	writel(0, PMB_ADDR_BASE(0));
	writel(0, PMB_DATA_BASE(0));

	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	/*			ppn  ub v s1 s0  c  wt */
	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
}
#endif

int board_init(void)
{
	struct gether_control_regs *gether = GETHER_CONTROL_BASE;

	init_gpio();
#if defined(CONFIG_SH_32BIT)
	set_pmb_on_board_init();
#endif

	/* Sets TXnDLY to B'010 */
	writel(0x00000202, &gether->gbecont);

	init_usb_phy();
	init_gether_mdio();

	return 0;
}

int board_mmc_init(bd_t *bis)
{
	struct gpio_regs *gpio = GPIO_BASE;

	writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
	writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
	udelay(1);
	writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr);	/* Release reset */
	udelay(200);

	return mmcif_mmc_init();
}

static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
#ifdef CONFIG_DEPRECATED
	struct spi_flash *spi;
	int ret;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (spi == NULL) {
		printf("%s: spi_flash probe failed.\n", __func__);
		return 1;
	}

	ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
	if (ret) {
		printf("%s: spi_flash read failed.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);
#endif

	return 0;
}

static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
{
	memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
		SH7753EVB_ETHERNET_MAC_SIZE);
	mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */

	return 0;
}

static void init_ethernet_mac(void)
{
	char mac_string[64];
	char env_string[64];
	int i;
	unsigned char *buf;

	buf = malloc(256);
	if (!buf) {
		printf("%s: malloc failed.\n", __func__);
		return;
	}
	get_sh_eth_mac_raw(buf, 256);

	/* Gigabit Ethernet */
	for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i, mac_string, buf);
		if (i == 0)
			env_set("ethaddr", mac_string);
		else {
			sprintf(env_string, "eth%daddr", i);
			env_set(env_string, mac_string);
		}
		set_mac_to_sh_giga_eth_register(i, mac_string);
	}

	free(buf);
}

int board_late_init(void)
{
	init_ethernet_mac();

	return 0;
}

#ifdef CONFIG_DEPRECATED
int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int i, ret;
	char mac_string[256];
	struct spi_flash *spi;
	unsigned char *buf;

	if (argc != 3) {
		buf = malloc(256);
		if (!buf) {
			printf("%s: malloc failed.\n", __func__);
			return 1;
		}

		get_sh_eth_mac_raw(buf, 256);

		/* print current MAC address */
		for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
			get_sh_eth_mac(i, mac_string, buf);
			printf("GETHERC ch%d = %s\n", i, mac_string);
		}
		free(buf);
		return 0;
	}

	/* new setting */
	memset(mac_string, 0xff, sizeof(mac_string));
	sprintf(mac_string, "%s\t%s",
		argv[1], argv[2]);

	/* write MAC data to SPI rom */
	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe failed.\n", __func__);
		return 1;
	}

	ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
				SH7753EVB_SPI_SECTOR_SIZE);
	if (ret) {
		printf("%s: spi_flash erase failed.\n", __func__);
		return 1;
	}

	ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
				sizeof(mac_string), mac_string);
	if (ret) {
		printf("%s: spi_flash write failed.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	puts("The writing of the MAC address to SPI ROM was completed.\n");

	return 0;
}

U_BOOT_CMD(
	write_mac,	3,	1,	do_write_mac,
	"write MAC address for GETHERC",
	"[GETHERC ch0] [GETHERC ch1]\n"
);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
320cf350 YS	2	/*
320cf350 YS	3	* Copyright (C) 2012 Renesas Solutions Corp.
320cf350 YS	4	*/
	5
	6	#include <common.h>
9fb625ce	7	#include <env.h>
b79fdc76	8	#include <flash.h>
5255932f	9	#include <init.h>
320cf350 YS	10	#include <malloc.h>
	11	#include <asm/processor.h>
	12	#include <asm/io.h>
	13	#include <asm/mmc.h>
ff0960f9	14	#include <spi.h>
320cf350 YS	15	#include <spi_flash.h>
	16
	17	int checkboard(void)
	18	{
	19	puts("BOARD: SH7753 EVB\n");
	20
	21	return 0;
	22	}
	23
	24	static void init_gpio(void)
	25	{
	26	struct gpio_regs *gpio = GPIO_BASE;
	27	struct sermux_regs *sermux = SERMUX_BASE;
	28
	29	/* GPIO */
	30	writew(0x0000, &gpio->pacr); /* GETHER */
	31	writew(0x0001, &gpio->pbcr); /* INTC */
	32	writew(0x0000, &gpio->pccr); /* PWMU, INTC */
	33	writew(0x0000, &gpio->pdcr); /* SPI0 */
	34	writew(0xeaff, &gpio->pecr); /* GPIO */
	35	writew(0x0000, &gpio->pfcr); /* WDT */
	36	writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
	37	writew(0x0000, &gpio->phcr); /* SPI1 */
	38	writew(0x0000, &gpio->picr); /* SDHI */
	39	writew(0x0000, &gpio->pjcr); /* SCIF4 */
	40	writew(0x0003, &gpio->pkcr); /* SerMux */
	41	writew(0x0000, &gpio->plcr); /* SerMux */
	42	writew(0x0000, &gpio->pmcr); /* RIIC */
	43	writew(0x0000, &gpio->pncr); /* USB, SGPIO */
	44	writew(0x0000, &gpio->pocr); /* SGPIO */
	45	writew(0xd555, &gpio->pqcr); /* GPIO */
	46	writew(0x0000, &gpio->prcr); /* RIIC */
	47	writew(0x0000, &gpio->pscr); /* RIIC */
	48	writew(0x0000, &gpio->ptcr); /* STATUS */
	49	writeb(0x00, &gpio->pudr);
	50	writew(0x5555, &gpio->pucr); /* Debug LED */
	51	writew(0x0000, &gpio->pvcr); /* RSPI */
	52	writew(0x0000, &gpio->pwcr); /* EVC */
	53	writew(0x0000, &gpio->pxcr); /* LBSC */
	54	writew(0x0000, &gpio->pycr); /* LBSC */
	55	writew(0x0000, &gpio->pzcr); /* eMMC */
	56	writew(0xfe00, &gpio->psel0);
	57	writew(0x0000, &gpio->psel1);
	58	writew(0x3000, &gpio->psel2);
	59	writew(0xff00, &gpio->psel3);
	60	writew(0x771f, &gpio->psel4);
	61	writew(0x0ffc, &gpio->psel5);
	62	writew(0x00ff, &gpio->psel6);
	63	writew(0xfc00, &gpio->psel7);
	64
	65	writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
	66	}
	67
	68	static void init_usb_phy(void)
	69	{
	70	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	71	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	72	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	73	struct usb1_port_regs *port = USB1_PORT_BASE;
	74	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
	75
	76	writew(0x0100, &phy->reset); /* set reset */
	77	/* port0 = USB0, port1 = USB1 */
	78	writew(0x0002, &phy->portsel);
79	writel(0x0001, &port->port1sel); /* port1 = Host */
80	writew(0x0111, &phy->reset); /* clear reset */
81
82	writew(0x4000, &common0->suspmode);
83	writew(0x4000, &common1->suspmode);
84
85	#if defined(__LITTLE_ENDIAN)
86	writel(0x00000000, &align->ehcidatac);
87	writel(0x00000000, &align->ohcidatac);
88	#endif
89	}
90
91	static void init_gether_mdio(void)
92	{
93	struct gpio_regs *gpio = GPIO_BASE;
94
95	writew(readw(&gpio->pgcr) \| 0x0004, &gpio->pgcr);
96	writeb(readb(&gpio->pgdr) \| 0x02, &gpio->pgdr); /* Use ET0-MDIO */
97	}
98
99	static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
100	{
101	struct ether_mac_regs *ether;
102	unsigned char mac[6];
103	unsigned long val;
104
fb8977c5	105	string_to_enetaddr(mac_string, mac);
320cf350 YS	106
	107	if (!channel)
	108	ether = GETHER0_MAC_BASE;
	109	else
	110	ether = GETHER1_MAC_BASE;
	111
	112	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
	113	writel(val, &ether->mahr);
	114	val = (mac[4] << 8) \| mac[5];
	115	writel(val, &ether->malr);
	116	}
	117
b3ce9081	118	#if defined(CONFIG_SH_32BIT)
320cf350 YS	119	/*****************************************************************
	120	* This PMB must be set on this timing. The lowlevel_init is run on
	121	* Area 0(phys 0x00000000), so we have to map it.
	122	*
	123	* The new PMB table is following:
	124	* ent virt phys v sz c wt
	125	* 0 0xa0000000 0x40000000 1 128M 0 1
	126	* 1 0xa8000000 0x48000000 1 128M 0 1
	127	* 2 0xb0000000 0x50000000 1 128M 0 1
	128	* 3 0xb8000000 0x58000000 1 128M 0 1
	129	* 4 0x80000000 0x40000000 1 128M 1 1
	130	* 5 0x88000000 0x48000000 1 128M 1 1
	131	* 6 0x90000000 0x50000000 1 128M 1 1
	132	* 7 0x98000000 0x58000000 1 128M 1 1
	133	*/
	134	static void set_pmb_on_board_init(void)
	135	{
	136	struct mmu_regs *mmu = MMU_BASE;
	137
	138	/* clear ITLB */
	139	writel(0x00000004, &mmu->mmucr);
	140
	141	/* delete PMB for SPIBOOT */
	142	writel(0, PMB_ADDR_BASE(0));
	143	writel(0, PMB_DATA_BASE(0));
	144
	145	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	146	/* ppn ub v s1 s0 c wt */
	147	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	148	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	149	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	150	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	151	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	152	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	153	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	154	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	155	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	156	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	157	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	158	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
	159	}
b3ce9081	160	#endif
320cf350 YS	161
	162	int board_init(void)
	163	{
	164	struct gether_control_regs *gether = GETHER_CONTROL_BASE;
	165
	166	init_gpio();
b3ce9081	167	#if defined(CONFIG_SH_32BIT)
320cf350	168	set_pmb_on_board_init();
b3ce9081	169	#endif
320cf350 YS	170
	171	/* Sets TXnDLY to B'010 */
	172	writel(0x00000202, &gether->gbecont);
	173
	174	init_usb_phy();
	175	init_gether_mdio();
	176
	177	return 0;
	178	}
	179
320cf350 YS	180	int board_mmc_init(bd_t *bis)
	181	{
	182	struct gpio_regs *gpio = GPIO_BASE;
	183
	184	writew(readw(&gpio->pgcr) \| 0x0040, &gpio->pgcr);
	185	writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
	186	udelay(1);
	187	writeb(readb(&gpio->pgdr) \| 0x08, &gpio->pgdr); /* Release reset */
	188	udelay(200);
	189
	190	return mmcif_mmc_init();
	191	}
	192
	193	static int get_sh_eth_mac_raw(unsigned char *buf, int size)
	194	{
88369d33	195	#ifdef CONFIG_DEPRECATED
320cf350 YS	196	struct spi_flash *spi;
	197	int ret;
	198
	199	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	200	if (spi == NULL) {
	201	printf("%s: spi_flash probe failed.\n", __func__);
	202	return 1;
	203	}
	204
	205	ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
	206	if (ret) {
	207	printf("%s: spi_flash read failed.\n", __func__);
	208	spi_flash_free(spi);
	209	return 1;
	210	}
	211	spi_flash_free(spi);
88369d33	212	#endif
320cf350 YS	213
	214	return 0;
	215	}
	216
	217	static int get_sh_eth_mac(int channel, char mac_string, unsigned char buf)
	218	{
	219	memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
	220	SH7753EVB_ETHERNET_MAC_SIZE);
	221	mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
	222
	223	return 0;
	224	}
	225
	226	static void init_ethernet_mac(void)
	227	{
	228	char mac_string[64];
	229	char env_string[64];
	230	int i;
	231	unsigned char *buf;
	232
	233	buf = malloc(256);
	234	if (!buf) {
	235	printf("%s: malloc failed.\n", __func__);
	236	return;
	237	}
	238	get_sh_eth_mac_raw(buf, 256);
	239
	240	/* Gigabit Ethernet */
	241	for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
	242	get_sh_eth_mac(i, mac_string, buf);
	243	if (i == 0)
382bee57	244	env_set("ethaddr", mac_string);
320cf350 YS	245	else {
320cf350 YS	246	sprintf(env_string, "eth%daddr", i);
382bee57	247	env_set(env_string, mac_string);
320cf350 YS	248	}
	249	set_mac_to_sh_giga_eth_register(i, mac_string);
	250	}
	251
	252	free(buf);
	253	}
	254
	255	int board_late_init(void)
	256	{
	257	init_ethernet_mac();
	258
	259	return 0;
	260	}
	261
88369d33	262	#ifdef CONFIG_DEPRECATED
320cf350 YS	263	int do_write_mac(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	264	{
	265	int i, ret;
	266	char mac_string[256];
	267	struct spi_flash *spi;
	268	unsigned char *buf;
	269
	270	if (argc != 3) {
	271	buf = malloc(256);
	272	if (!buf) {
	273	printf("%s: malloc failed.\n", __func__);
	274	return 1;
	275	}
	276
	277	get_sh_eth_mac_raw(buf, 256);
	278
	279	/* print current MAC address */
	280	for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
	281	get_sh_eth_mac(i, mac_string, buf);
	282	printf("GETHERC ch%d = %s\n", i, mac_string);
	283	}
	284	free(buf);
	285	return 0;
	286	}
	287
	288	/* new setting */
	289	memset(mac_string, 0xff, sizeof(mac_string));
	290	sprintf(mac_string, "%s\t%s",
	291	argv[1], argv[2]);
	292
	293	/* write MAC data to SPI rom */
	294	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	295	if (!spi) {
	296	printf("%s: spi_flash probe failed.\n", __func__);
	297	return 1;
	298	}
	299
	300	ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
	301	SH7753EVB_SPI_SECTOR_SIZE);
	302	if (ret) {
	303	printf("%s: spi_flash erase failed.\n", __func__);
	304	return 1;
	305	}
	306
	307	ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
	308	sizeof(mac_string), mac_string);
	309	if (ret) {
	310	printf("%s: spi_flash write failed.\n", __func__);
	311	spi_flash_free(spi);
	312	return 1;
	313	}
	314	spi_flash_free(spi);
	315
	316	puts("The writing of the MAC address to SPI ROM was completed.\n");
	317
	318	return 0;
	319	}
	320
	321	U_BOOT_CMD(
	322	write_mac, 3, 1, do_write_mac,
	323	"write MAC address for GETHERC",
	324	"[GETHERC ch0] [GETHERC ch1]\n"
	325	);
88369d33	326	#endif