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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
765547dc | 2 | /* |
4c2e3da8 | 3 | * Copyright (C) 2009 Freescale Semiconductor, Inc. |
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4 | */ |
5 | ||
6 | #include <common.h> | |
b79fdc76 | 7 | #include <flash.h> |
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8 | #include <asm/io.h> |
9 | ||
10 | #include "bcsr.h" | |
11 | ||
e56143e5 | 12 | void enable_8569mds_flash_write(void) |
765547dc | 13 | { |
16e7559c | 14 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); |
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15 | } |
16 | ||
e56143e5 | 17 | void disable_8569mds_flash_write(void) |
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18 | { |
19 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); | |
20 | } | |
21 | ||
e56143e5 | 22 | void enable_8569mds_qe_uec(void) |
765547dc | 23 | { |
f82107f6 | 24 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
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25 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), |
26 | BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); | |
27 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), | |
28 | BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); | |
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29 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), |
30 | BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); | |
31 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), | |
32 | BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); | |
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33 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
34 | /* Set UCC1-4 working at RMII mode */ | |
35 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), | |
36 | BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); | |
37 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), | |
38 | BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); | |
39 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), | |
40 | BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); | |
41 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), | |
42 | BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); | |
43 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); | |
44 | #endif | |
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45 | } |
46 | ||
e56143e5 | 47 | void disable_8569mds_brd_eeprom_write_protect(void) |
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48 | { |
49 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); | |
50 | } |