[J-u-boot.git] / board / freescale / mpc8568mds / mpc8568mds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2002 Scott McNutt <[email protected]>
 */

#include <common.h>
#include <flash.h>
#include <init.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
#include <linux/libfdt.h>
#include <fdt_support.h>

#include "bcsr.h"

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{4, 10, 1, 0, 2}, /* TxD0 */
	{4,  9, 1, 0, 2}, /* TxD1 */
	{4,  8, 1, 0, 2}, /* TxD2 */
	{4,  7, 1, 0, 2}, /* TxD3 */
	{4, 23, 1, 0, 2}, /* TxD4 */
	{4, 22, 1, 0, 2}, /* TxD5 */
	{4, 21, 1, 0, 2}, /* TxD6 */
	{4, 20, 1, 0, 2}, /* TxD7 */
	{4, 15, 2, 0, 2}, /* RxD0 */
	{4, 14, 2, 0, 2}, /* RxD1 */
	{4, 13, 2, 0, 2}, /* RxD2 */
	{4, 12, 2, 0, 2}, /* RxD3 */
	{4, 29, 2, 0, 2}, /* RxD4 */
	{4, 28, 2, 0, 2}, /* RxD5 */
	{4, 27, 2, 0, 2}, /* RxD6 */
	{4, 26, 2, 0, 2}, /* RxD7 */
	{4, 11, 1, 0, 2}, /* TX_EN */
	{4, 24, 1, 0, 2}, /* TX_ER */
	{4, 16, 2, 0, 2}, /* RX_DV */
	{4, 30, 2, 0, 2}, /* RX_ER */
	{4, 17, 2, 0, 2}, /* RX_CLK */
	{4, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */

	/* GETH2 */
	{5, 10, 1, 0, 2}, /* TxD0 */
	{5,  9, 1, 0, 2}, /* TxD1 */
	{5,  8, 1, 0, 2}, /* TxD2 */
	{5,  7, 1, 0, 2}, /* TxD3 */
	{5, 23, 1, 0, 2}, /* TxD4 */
	{5, 22, 1, 0, 2}, /* TxD5 */
	{5, 21, 1, 0, 2}, /* TxD6 */
	{5, 20, 1, 0, 2}, /* TxD7 */
	{5, 15, 2, 0, 2}, /* RxD0 */
	{5, 14, 2, 0, 2}, /* RxD1 */
	{5, 13, 2, 0, 2}, /* RxD2 */
	{5, 12, 2, 0, 2}, /* RxD3 */
	{5, 29, 2, 0, 2}, /* RxD4 */
	{5, 28, 2, 0, 2}, /* RxD5 */
	{5, 27, 2, 0, 3}, /* RxD6 */
	{5, 26, 2, 0, 2}, /* RxD7 */
	{5, 11, 1, 0, 2}, /* TX_EN */
	{5, 24, 1, 0, 2}, /* TX_ER */
	{5, 16, 2, 0, 2}, /* RX_DV */
	{5, 30, 2, 0, 2}, /* RX_ER */
	{5, 17, 2, 0, 2}, /* RX_CLK */
	{5, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */
	{4,  6, 3, 0, 2}, /* MDIO */
	{4,  5, 1, 0, 2}, /* MDC */

	/* UART1 */
	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
	{2, 1, 1, 0, 2}, /* UART_RTS1 */
	{2, 2, 2, 0, 2}, /* UART_CTS1 */
	{2, 3, 2, 0, 2}, /* UART_SIN1 */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

void local_bus_init(void);

int board_early_init_f (void)
{
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	enable_8568mds_duart();
	enable_8568mds_flash_write();
#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
	reset_8568mds_uccs();
#endif
#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	enable_8568mds_qe_mdio();
#endif

#ifdef CONFIG_SYS_I2C2_OFFSET
	/* Enable I2C2_SCL and I2C2_SDA */
	volatile struct par_io *port_c;
	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
	port_c->cpdir2 |= 0x0f000000;
	port_c->cppar2 &= ~0x0f000000;
	port_c->cppar2 |= 0x0a000000;
#endif

	return 0;
}

int checkboard (void)
{
	printf ("Board: 8568 MDS\n");

	return 0;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)

	uint idx;
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint lsdmr_common;

	puts("LBC SDRAM: ");
	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
		   "\n       ");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
	asm("msync");

	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");

	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8568 uses "new" 15-16 style addressing.
	 */
	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
	lsdmr_common |= LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_PCI)
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8568mds_config_table[] = {
	{
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 pci_cfgfunc_config_device,
	 {PCI_ENET0_IOADDR,
	  PCI_ENET0_MEMADDR,
	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
	 },
	{}
};
#endif

static struct pci_controller pci1_hose;
#endif	/* CONFIG_PCI */

/*
 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
 */
void
pib_init(void)
{
	u8 val8, orig_i2c_bus;
	/*
	 * Assign PIB PMC2/3 to PCI bus
	 */

	/*switch temporarily to I2C bus #2 */
	orig_i2c_bus = i2c_get_bus_num();
	i2c_set_bus_num(1);

	val8 = 0x00;
	i2c_write(0x23, 0x6, 1, &val8, 1);
	i2c_write(0x23, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x23, 0x2, 1, &val8, 1);
	i2c_write(0x23, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x26, 0x6, 1, &val8, 1);
	val8 = 0x34;
	i2c_write(0x26, 0x7, 1, &val8, 1);
	val8 = 0xf9;
	i2c_write(0x26, 0x2, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x26, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x27, 0x6, 1, &val8, 1);
	i2c_write(0x27, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x27, 0x2, 1, &val8, 1);
	val8 = 0xef;
	i2c_write(0x27, 0x3, 1, &val8, 1);

	asm("eieio");
	i2c_set_bus_num(orig_i2c_bus);
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int first_free_busno = 0;
#ifdef CONFIG_PCI1
	struct fsl_pci_info pci_info;
	u32 devdisr, pordevsr, io_sel;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);
	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);

	pci_speed = 66666000;
	pci_32 = 1;
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info.regs);

#ifndef CONFIG_PCI_PNP
		pci1_hose.config_table = pci_mpc8568mds_config_table;
#endif
		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif

	fsl_pcie_init_board(first_free_busno);
}
#endif /* CONFIG_PCI */

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
67431059	2	/*
b092072e	3	* Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
67431059 AF	4	*
67431059 AF	5	* (C) Copyright 2002 Scott McNutt <[email protected]>
67431059 AF	6	*/
	7
	8	#include <common.h>
b79fdc76	9	#include <flash.h>
2cf431c2	10	#include <init.h>
67431059 AF	11	#include <pci.h>
67431059 AF	12	#include <asm/processor.h>
e6f5b35b	13	#include <asm/mmu.h>
67431059	14	#include <asm/immap_85xx.h>
c8514622	15	#include <asm/fsl_pci.h>
5614e71b	16	#include <fsl_ddr_sdram.h>
5d27e02c	17	#include <asm/fsl_serdes.h>
a30a549a	18	#include <spd_sdram.h>
c59e4091	19	#include <i2c.h>
da9d4610	20	#include <ioports.h>
b08c8c48	21	#include <linux/libfdt.h>
c480861b	22	#include <fdt_support.h>
1563f56e	23
67431059 AF	24	#include "bcsr.h"
67431059 AF	25
da9d4610 AF	26	const qe_iop_conf_t qe_iop_conf_tab[] = {
	27	/* GETH1 */
	28	{4, 10, 1, 0, 2}, /* TxD0 */
	29	{4, 9, 1, 0, 2}, /* TxD1 */
	30	{4, 8, 1, 0, 2}, /* TxD2 */
	31	{4, 7, 1, 0, 2}, /* TxD3 */
	32	{4, 23, 1, 0, 2}, /* TxD4 */
	33	{4, 22, 1, 0, 2}, /* TxD5 */
	34	{4, 21, 1, 0, 2}, /* TxD6 */
	35	{4, 20, 1, 0, 2}, /* TxD7 */
	36	{4, 15, 2, 0, 2}, /* RxD0 */
	37	{4, 14, 2, 0, 2}, /* RxD1 */
	38	{4, 13, 2, 0, 2}, /* RxD2 */
	39	{4, 12, 2, 0, 2}, /* RxD3 */
	40	{4, 29, 2, 0, 2}, /* RxD4 */
	41	{4, 28, 2, 0, 2}, /* RxD5 */
	42	{4, 27, 2, 0, 2}, /* RxD6 */
	43	{4, 26, 2, 0, 2}, /* RxD7 */
	44	{4, 11, 1, 0, 2}, /* TX_EN */
	45	{4, 24, 1, 0, 2}, /* TX_ER */
	46	{4, 16, 2, 0, 2}, /* RX_DV */
	47	{4, 30, 2, 0, 2}, /* RX_ER */
	48	{4, 17, 2, 0, 2}, /* RX_CLK */
	49	{4, 19, 1, 0, 2}, /* GTX_CLK */
	50	{1, 31, 2, 0, 3}, /* GTX125 */
	51
	52	/* GETH2 */
	53	{5, 10, 1, 0, 2}, /* TxD0 */
	54	{5, 9, 1, 0, 2}, /* TxD1 */
	55	{5, 8, 1, 0, 2}, /* TxD2 */
	56	{5, 7, 1, 0, 2}, /* TxD3 */
	57	{5, 23, 1, 0, 2}, /* TxD4 */
	58	{5, 22, 1, 0, 2}, /* TxD5 */
	59	{5, 21, 1, 0, 2}, /* TxD6 */
	60	{5, 20, 1, 0, 2}, /* TxD7 */
	61	{5, 15, 2, 0, 2}, /* RxD0 */
	62	{5, 14, 2, 0, 2}, /* RxD1 */
	63	{5, 13, 2, 0, 2}, /* RxD2 */
	64	{5, 12, 2, 0, 2}, /* RxD3 */
	65	{5, 29, 2, 0, 2}, /* RxD4 */
	66	{5, 28, 2, 0, 2}, /* RxD5 */
	67	{5, 27, 2, 0, 3}, /* RxD6 */
	68	{5, 26, 2, 0, 2}, /* RxD7 */
	69	{5, 11, 1, 0, 2}, /* TX_EN */
	70	{5, 24, 1, 0, 2}, /* TX_ER */
	71	{5, 16, 2, 0, 2}, /* RX_DV */
	72	{5, 30, 2, 0, 2}, /* RX_ER */
	73	{5, 17, 2, 0, 2}, /* RX_CLK */
	74	{5, 19, 1, 0, 2}, /* GTX_CLK */
	75	{1, 31, 2, 0, 3}, /* GTX125 */
	76	{4, 6, 3, 0, 2}, /* MDIO */
	77	{4, 5, 1, 0, 2}, /* MDC */
64d4bcb0 AV	78
	79	/* UART1 */
	80	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
	81	{2, 1, 1, 0, 2}, /* UART_RTS1 */
	82	{2, 2, 2, 0, 2}, /* UART_CTS1 */
	83	{2, 3, 2, 0, 2}, /* UART_SIN1 */
	84
da9d4610 AF	85	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	86	};
	87
67431059	88	void local_bus_init(void);
67431059 AF	89
	90	int board_early_init_f (void)
	91	{
	92	/*
	93	* Initialize local bus.
	94	*/
	95	local_bus_init ();
	96
	97	enable_8568mds_duart();
	98	enable_8568mds_flash_write();
ad162249 AV	99	#if defined(CONFIG_UEC_ETH1) \|\| defined(CONFIG_UEC_ETH2)
	100	reset_8568mds_uccs();
	101	#endif
da9d4610 AF	102	#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	103	enable_8568mds_qe_mdio();
	104	#endif
67431059	105
6d0f6bcf	106	#ifdef CONFIG_SYS_I2C2_OFFSET
c59e4091 HW	107	/* Enable I2C2_SCL and I2C2_SDA */
c59e4091 HW	108	volatile struct par_io *port_c;
6d0f6bcf	109	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
c59e4091 HW	110	port_c->cpdir2 \|= 0x0f000000;
	111	port_c->cppar2 &= ~0x0f000000;
	112	port_c->cppar2 \|= 0x0a000000;
	113	#endif
	114
67431059 AF	115	return 0;
	116	}
	117
	118	int checkboard (void)
	119	{
	120	printf ("Board: 8568 MDS\n");
	121
	122	return 0;
	123	}
	124
67431059 AF	125	/*
	126	* Initialize Local Bus
	127	*/
	128	void
	129	local_bus_init(void)
	130	{
6d0f6bcf	131	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	132	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
67431059 AF	133
67431059 AF	134	uint clkdiv;
67431059 AF	135	sys_info_t sysinfo;
	136
	137	get_sys_info(&sysinfo);
a5d212a2	138	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
67431059 AF	139
	140	gur->lbiuiplldcr1 = 0x00078080;
	141	if (clkdiv == 16) {
	142	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	143	} else if (clkdiv == 8) {
	144	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	145	} else if (clkdiv == 4) {
	146	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	147	}
	148
	149	lbc->lcrr \|= 0x00030000;
	150
	151	asm("sync;isync;msync");
	152	}
	153
	154	/*
	155	* Initialize SDRAM memory on the Local Bus.
	156	*/
70961ba4	157	void lbc_sdram_init(void)
67431059	158	{
6d0f6bcf	159	#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
67431059 AF	160
67431059 AF	161	uint idx;
f51cdaf1	162	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	163	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
67431059 AF	164	uint lsdmr_common;
67431059 AF	165
7ea3871e BB	166	puts("LBC SDRAM: ");
	167	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
	168	"\n ");
67431059 AF	169
	170	/*
	171	* Setup SDRAM Base and Option Registers
	172	*/
f51cdaf1 BB	173	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
f51cdaf1 BB	174	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
67431059 AF	175	asm("msync");
67431059 AF	176
6d0f6bcf	177	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
67431059 AF	178	asm("msync");
67431059 AF	179
6d0f6bcf JCPV	180	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	181	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
67431059 AF	182	asm("msync");
	183
	184	/*
	185	* MPC8568 uses "new" 15-16 style addressing.
	186	*/
6d0f6bcf	187	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
b0fe93ed	188	lsdmr_common \|= LSDMR_BSMA1516;
67431059 AF	189
	190	/*
	191	* Issue PRECHARGE ALL command.
	192	*/
b0fe93ed	193	lbc->lsdmr = lsdmr_common \| LSDMR_OP_PCHALL;
67431059 AF	194	asm("sync;msync");
	195	*sdram_addr = 0xff;
	196	ppcDcbf((unsigned long) sdram_addr);
	197	udelay(100);
	198
	199	/*
	200	* Issue 8 AUTO REFRESH commands.
	201	*/
	202	for (idx = 0; idx < 8; idx++) {
b0fe93ed	203	lbc->lsdmr = lsdmr_common \| LSDMR_OP_ARFRSH;
67431059 AF	204	asm("sync;msync");
	205	*sdram_addr = 0xff;
	206	ppcDcbf((unsigned long) sdram_addr);
	207	udelay(100);
	208	}
	209
	210	/*
	211	* Issue 8 MODE-set command.
	212	*/
b0fe93ed	213	lbc->lsdmr = lsdmr_common \| LSDMR_OP_MRW;
67431059 AF	214	asm("sync;msync");
	215	*sdram_addr = 0xff;
	216	ppcDcbf((unsigned long) sdram_addr);
	217	udelay(100);
	218
	219	/*
	220	* Issue NORMAL OP command.
	221	*/
b0fe93ed	222	lbc->lsdmr = lsdmr_common \| LSDMR_OP_NORMAL;
67431059 AF	223	asm("sync;msync");
	224	*sdram_addr = 0xff;
	225	ppcDcbf((unsigned long) sdram_addr);
	226	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	227
	228	#endif /* enable SDRAM init */
	229	}
	230
67431059 AF	231	#if defined(CONFIG_PCI)
	232	#ifndef CONFIG_PCI_PNP
	233	static struct pci_config_table pci_mpc8568mds_config_table[] = {
	234	{
	235	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	236	pci_cfgfunc_config_device,
	237	{PCI_ENET0_IOADDR,
	238	PCI_ENET0_MEMADDR,
	239	PCI_COMMON_MEMORY \| PCI_COMMAND_MASTER}
	240	},
	241	{}
	242	};
	243	#endif
	244
b092072e	245	static struct pci_controller pci1_hose;
67431059 AF	246	#endif /* CONFIG_PCI */
67431059 AF	247
c59e4091 HW	248	/*
	249	* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
	250	*/
	251	void
	252	pib_init(void)
	253	{
	254	u8 val8, orig_i2c_bus;
	255	/*
	256	* Assign PIB PMC2/3 to PCI bus
	257	*/
	258
	259	/switch temporarily to I2C bus #2 /
	260	orig_i2c_bus = i2c_get_bus_num();
	261	i2c_set_bus_num(1);
	262
	263	val8 = 0x00;
	264	i2c_write(0x23, 0x6, 1, &val8, 1);
	265	i2c_write(0x23, 0x7, 1, &val8, 1);
	266	val8 = 0xff;
	267	i2c_write(0x23, 0x2, 1, &val8, 1);
	268	i2c_write(0x23, 0x3, 1, &val8, 1);
	269
	270	val8 = 0x00;
	271	i2c_write(0x26, 0x6, 1, &val8, 1);
	272	val8 = 0x34;
	273	i2c_write(0x26, 0x7, 1, &val8, 1);
	274	val8 = 0xf9;
	275	i2c_write(0x26, 0x2, 1, &val8, 1);
	276	val8 = 0xff;
	277	i2c_write(0x26, 0x3, 1, &val8, 1);
	278
	279	val8 = 0x00;
	280	i2c_write(0x27, 0x6, 1, &val8, 1);
	281	i2c_write(0x27, 0x7, 1, &val8, 1);
	282	val8 = 0xff;
	283	i2c_write(0x27, 0x2, 1, &val8, 1);
	284	val8 = 0xef;
	285	i2c_write(0x27, 0x3, 1, &val8, 1);
	286
	287	asm("eieio");
502dd36b	288	i2c_set_bus_num(orig_i2c_bus);
c59e4091 HW	289	}
c59e4091 HW	290
1563f56e	291	#ifdef CONFIG_PCI
4681457e	292	void pci_init_board(void)
67431059	293	{
6d0f6bcf	294	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
3f6f9d76 KG	295	int first_free_busno = 0;
	296	#ifdef CONFIG_PCI1
	297	struct fsl_pci_info pci_info;
4681457e KG	298	u32 devdisr, pordevsr, io_sel;
4681457e KG	299	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
1563f56e	300
4681457e KG	301	devdisr = in_be32(&gur->devdisr);
	302	pordevsr = in_be32(&gur->pordevsr);
	303	porpllsr = in_be32(&gur->porpllsr);
	304	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
1563f56e	305
4681457e	306	debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
1563f56e	307
4681457e KG	308	pci_speed = 66666000;
	309	pci_32 = 1;
	310	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	311	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
	312
	313	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
3f6f9d76 KG	314	SET_STD_PCI_INFO(pci_info, 1);
	315	set_next_law(pci_info.mem_phys,
	316	law_size_bits(pci_info.mem_size), pci_info.law);
	317	set_next_law(pci_info.io_phys,
	318	law_size_bits(pci_info.io_size), pci_info.law);
	319
	320	pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
8ca78f2c	321	printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
1563f56e HW	322	(pci_32) ? 32 : 64,
	323	(pci_speed == 33333000) ? "33" :
	324	(pci_speed == 66666000) ? "66" : "unknown",
	325	pci_clk_sel ? "sync" : "async",
	326	pci_agent ? "agent" : "host",
4681457e	327	pci_arb ? "arbiter" : "external-arbiter",
3f6f9d76	328	pci_info.regs);
4681457e	329
b092072e ZC	330	#ifndef CONFIG_PCI_PNP
	331	pci1_hose.config_table = pci_mpc8568mds_config_table;
	332	#endif
3f6f9d76	333	first_free_busno = fsl_pci_init_port(&pci_info,
4681457e	334	&pci1_hose, first_free_busno);
1563f56e	335	} else {
8ca78f2c	336	printf("PCI: disabled\n");
1563f56e	337	}
4681457e KG	338
4681457e KG	339	puts("\n");
1563f56e	340	#else
4681457e	341	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
1563f56e HW	342	#endif
1563f56e HW	343
3f6f9d76	344	fsl_pcie_init_board(first_free_busno);
67431059	345	}
1563f56e HW	346	#endif /* CONFIG_PCI */
1563f56e HW	347
c480861b	348	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	349	int ft_board_setup(void blob, bd_t bd)
2dba0dea	350	{
1563f56e	351	ft_cpu_setup(blob, bd);
1563f56e	352
6525d51f	353	FT_FSL_PCI_SETUP;
e895a4b0 SG	354
e895a4b0 SG	355	return 0;
1563f56e HW	356	}
1563f56e HW	357	#endif