[J-u-boot.git] / board / toradex / colibri_imx7 / colibri_imx7.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016-2018 Toradex AG
 */

#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fdt_support.h>
#include <fsl_esdhc_imx.h>
#include <jffs2/load_kernel.h>
#include <linux/delay.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/rn5t567_pmic.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include "../common/tdx-common.h"

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)

#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
	PAD_CTL_DSE_3P3V_49OHM)

#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)

#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)

#define USB_CDET_GPIO	IMX_GPIO_NR(7, 14)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());

	return 0;
}

static iomux_v3_cfg_t const uart1_pads[] = {
	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
};

#ifdef CONFIG_USB_EHCI_MX7
static iomux_v3_cfg_t const usb_cdet_pads[] = {
	MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#endif

#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
static iomux_v3_cfg_t const gpmi_pads[] = {
	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_CLK__NAND_CLE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_CMD__NAND_ALE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_STROBE__NAND_RE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SD3_RESET_B__NAND_WE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
};

static void setup_gpmi_nand(void)
{
	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));

	/* NAND_USDHC_BUS_CLK is set in rom */
	set_clk_nand();
}
#endif

#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
};

static iomux_v3_cfg_t const backlight_pads[] = {
	/* Backlight On */
	MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
	/* Backlight PWM<A> (multiplexed pin) */
	MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
#define GPIO_PWM_A IMX_GPIO_NR(1, 8)

static int setup_lcd(void)
{
	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));

	/* Set BL_ON */
	gpio_request(GPIO_BL_ON, "BL_ON");
	gpio_direction_output(GPIO_BL_ON, 1);

	/* Set PWM<A> to full brightness (assuming inversed polarity) */
	gpio_request(GPIO_PWM_A, "PWM<A>");
	gpio_direction_output(GPIO_PWM_A, 0);

	return 0;
}
#endif

/*
 * Backlight off before OS handover
 */
void board_preboot_os(void)
{
	gpio_direction_output(GPIO_PWM_A, 1);
	gpio_direction_output(GPIO_BL_ON, 0);
}

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;

#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
	/*
	 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
	 * and output it on the pin
	 */
	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
#else
	/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
#endif

	return set_clk_enet(ENET_50MHZ);
}

#endif

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_FEC_MXC
	setup_fec();
#endif

#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
	setup_gpmi_nand();
#endif

#ifdef CONFIG_VIDEO_MXS
	setup_lcd();
#endif

#ifdef CONFIG_USB_EHCI_MX7
	imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
#endif

	return 0;
}

#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
	struct udevice *dev;
	int reg, ver;
	int ret;


	ret = pmic_get("rn5t567@33", &dev);
	if (ret)
		return ret;
	ver = pmic_reg_read(dev, RN5T567_LSIVER);
	reg = pmic_reg_read(dev, RN5T567_OTPVER);

	printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);

	/* set judge and press timer of N_OE to minimal values */
	pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);

	/* configure sleep slot for 3.3V Ethernet */
	reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
	reg = (reg & 0xf0) | reg >> 4;
	pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);

	/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
	pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);

	/* configure sleep slot for ARM rail */
	reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
	reg = (reg & 0xf0) | reg >> 4;
	pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);

	/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
	pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);

	return 0;
}

void reset_cpu(ulong addr)
{
	struct udevice *dev;

	pmic_get("rn5t567@33", &dev);

	/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
	pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
	pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);

	/*
	 * Re-power factor detection on PMIC side is not instant. 1ms
	 * proved to be enough time until reset takes effect.
	 */
	mdelay(1);
}
#endif

int checkboard(void)
{
	printf("Model: Toradex Colibri iMX7%c\n",
	       is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');

	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
	int up;

	up = arch_auxiliary_core_check_up(0);
	if (up) {
		int ret;
		int areas = 1;
		u64 start[2], size[2];

		/*
		 * Reserve 1MB of memory for M4 (1MiB is also the minimum
		 * alignment for Linux due to MMU section size restrictions).
		 */
		start[0] = gd->bd->bi_dram[0].start;
		size[0] = SZ_256M - SZ_1M;

		/* If needed, create a second entry for memory beyond 256M */
		if (gd->bd->bi_dram[0].size > SZ_256M) {
			start[1] = gd->bd->bi_dram[0].start + SZ_256M;
			size[1] = gd->bd->bi_dram[0].size - SZ_256M;
			areas = 2;
		}

		ret = fdt_set_usable_memory(blob, start, size, areas);
		if (ret) {
			eprintf("Cannot set usable memory\n");
			return ret;
		}
	} else {
		int off;

		off = fdt_node_offset_by_compatible(blob, -1,
						    "fsl,imx7d-rpmsg");
		if (off > 0)
			fdt_status_disabled(blob, off);
	}
#endif
#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
	static const struct node_info nodes[] = {
		{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
		{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
	};

	/* Update partition nodes using info from mtdparts env var */
	puts("   Updating MTD partitions...\n");
	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif

	return ft_common_board_setup(blob, bd);
}
#endif

#ifdef CONFIG_USB_EHCI_MX7
static iomux_v3_cfg_t const usb_otg2_pads[] = {
	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};

int board_ehci_hcd_init(int port)
{
	switch (port) {
	case 0:
		break;
	case 1:
		if (is_cpu_type(MXC_CPU_MX7S))
			return -ENODEV;

		imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
						 ARRAY_SIZE(usb_otg2_pads));
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

int board_usb_phy_mode(int port)
{
	switch (port) {
	case 0:
		if (gpio_get_value(USB_CDET_GPIO))
			return USB_INIT_DEVICE;
		else
			return USB_INIT_HOST;
	case 1:
	default:
		return USB_INIT_HOST;
	}
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
ae440ab0	2	/*
a62c6061	3	* Copyright (C) 2016-2018 Toradex AG
ae440ab0 SA	4	*/
ae440ab0 SA	5
9b4a205f	6	#include <common.h>
9a3b4ceb	7	#include <cpu_func.h>
9b4a205f	8	#include <init.h>
90526e9f	9	#include <net.h>
ae440ab0 SA	10	#include <asm/arch/clock.h>
	11	#include <asm/arch/crm_regs.h>
	12	#include <asm/arch/imx-regs.h>
	13	#include <asm/arch/mx7-pins.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/gpio.h>
552a848e	16	#include <asm/mach-imx/iomux-v3.h>
ae440ab0 SA	17	#include <asm/io.h>
	18	#include <common.h>
	19	#include <dm.h>
	20	#include <dm/platform_data/serial_mxc.h>
64095704	21	#include <fdt_support.h>
e37ac717	22	#include <fsl_esdhc_imx.h>
64095704	23	#include <jffs2/load_kernel.h>
c05ed00a	24	#include <linux/delay.h>
ae440ab0 SA	25	#include <linux/sizes.h>
	26	#include <mmc.h>
	27	#include <miiphy.h>
64095704	28	#include <mtd_node.h>
ae440ab0	29	#include <netdev.h>
02ad90ec SA	30	#include <power/pmic.h>
02ad90ec SA	31	#include <power/rn5t567_pmic.h>
5a986dfe	32	#include <usb.h>
ae440ab0	33	#include <usb/ehci-ci.h>
37fa4125	34	#include "../common/tdx-common.h"
ae440ab0 SA	35
	36	DECLARE_GLOBAL_DATA_PTR;
	37
	38	#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM \| \
	39	PAD_CTL_PUS_PU100KOHM \| PAD_CTL_HYS)
	40
ae440ab0 SA	41	#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM \| PAD_CTL_DSE_3P3V_49OHM)
	42	#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
	43
	44	#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM \| PAD_CTL_DSE_3P3V_49OHM)
	45
ae440ab0 SA	46	#define LCD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_PU100KOHM \| \
	47	PAD_CTL_DSE_3P3V_49OHM)
	48
	49	#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM \| PAD_CTL_SRE_SLOW \| PAD_CTL_HYS)
	50
	51	#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM \| PAD_CTL_PUS_PU5KOHM)
	52
5a986dfe SA	53	#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
5a986dfe SA	54
ae440ab0 SA	55	int dram_init(void)
ae440ab0 SA	56	{
787075e0	57	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
ae440ab0 SA	58
	59	return 0;
	60	}
	61
	62	static iomux_v3_cfg_t const uart1_pads[] = {
	63	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	64	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	65	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS \| MUX_PAD_CTRL(UART_PAD_CTRL),
	66	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS \| MUX_PAD_CTRL(UART_PAD_CTRL),
	67	};
	68
5a986dfe SA	69	#ifdef CONFIG_USB_EHCI_MX7
	70	static iomux_v3_cfg_t const usb_cdet_pads[] = {
	71	MX7D_PAD_ENET1_CRS__GPIO7_IO14 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	72	};
	73	#endif
	74
a62c6061	75	#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
ae440ab0 SA	76	static iomux_v3_cfg_t const gpmi_pads[] = {
	77	MX7D_PAD_SD3_DATA0__NAND_DATA00 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	78	MX7D_PAD_SD3_DATA1__NAND_DATA01 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	79	MX7D_PAD_SD3_DATA2__NAND_DATA02 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	80	MX7D_PAD_SD3_DATA3__NAND_DATA03 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	81	MX7D_PAD_SD3_DATA4__NAND_DATA04 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	82	MX7D_PAD_SD3_DATA5__NAND_DATA05 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	83	MX7D_PAD_SD3_DATA6__NAND_DATA06 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	84	MX7D_PAD_SD3_DATA7__NAND_DATA07 \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	85	MX7D_PAD_SD3_CLK__NAND_CLE \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	86	MX7D_PAD_SD3_CMD__NAND_ALE \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	87	MX7D_PAD_SD3_STROBE__NAND_RE_B \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	88	MX7D_PAD_SD3_RESET_B__NAND_WE_B \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	89	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	90	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B \| MUX_PAD_CTRL(NAND_PAD_CTRL),
	91	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B \| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
	92	};
	93
	94	static void setup_gpmi_nand(void)
	95	{
	96	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
	97
	98	/* NAND_USDHC_BUS_CLK is set in rom */
	99	set_clk_nand();
	100	}
	101	#endif
	102
ae440ab0 SA	103	#ifdef CONFIG_VIDEO_MXS
	104	static iomux_v3_cfg_t const lcd_pads[] = {
	105	MX7D_PAD_LCD_CLK__LCD_CLK \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	106	MX7D_PAD_LCD_ENABLE__LCD_ENABLE \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	107	MX7D_PAD_LCD_HSYNC__LCD_HSYNC \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	108	MX7D_PAD_LCD_VSYNC__LCD_VSYNC \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	109	MX7D_PAD_LCD_DATA00__LCD_DATA0 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	110	MX7D_PAD_LCD_DATA01__LCD_DATA1 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	111	MX7D_PAD_LCD_DATA02__LCD_DATA2 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	112	MX7D_PAD_LCD_DATA03__LCD_DATA3 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	113	MX7D_PAD_LCD_DATA04__LCD_DATA4 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	114	MX7D_PAD_LCD_DATA05__LCD_DATA5 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	115	MX7D_PAD_LCD_DATA06__LCD_DATA6 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	116	MX7D_PAD_LCD_DATA07__LCD_DATA7 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	117	MX7D_PAD_LCD_DATA08__LCD_DATA8 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	118	MX7D_PAD_LCD_DATA09__LCD_DATA9 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	119	MX7D_PAD_LCD_DATA10__LCD_DATA10 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	120	MX7D_PAD_LCD_DATA11__LCD_DATA11 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	121	MX7D_PAD_LCD_DATA12__LCD_DATA12 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	122	MX7D_PAD_LCD_DATA13__LCD_DATA13 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	123	MX7D_PAD_LCD_DATA14__LCD_DATA14 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	124	MX7D_PAD_LCD_DATA15__LCD_DATA15 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	125	MX7D_PAD_LCD_DATA16__LCD_DATA16 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	126	MX7D_PAD_LCD_DATA17__LCD_DATA17 \| MUX_PAD_CTRL(LCD_PAD_CTRL),
	127	};
	128
	129	static iomux_v3_cfg_t const backlight_pads[] = {
	130	/* Backlight On */
	131	MX7D_PAD_SD1_WP__GPIO5_IO1 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	132	/* Backlight PWM<A> (multiplexed pin) */
	133	MX7D_PAD_GPIO1_IO08__GPIO1_IO8 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	134	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	135	};
	136
	137	#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
	138	#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
	139
	140	static int setup_lcd(void)
	141	{
	142	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
	143
	144	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
	145
	146	/* Set BL_ON */
	147	gpio_request(GPIO_BL_ON, "BL_ON");
	148	gpio_direction_output(GPIO_BL_ON, 1);
	149
	150	/* Set PWM<A> to full brightness (assuming inversed polarity) */
	151	gpio_request(GPIO_PWM_A, "PWM<A>");
	152	gpio_direction_output(GPIO_PWM_A, 0);
	153
	154	return 0;
	155	}
	156	#endif
	157
a3c90217 GS	158	/*
	159	* Backlight off before OS handover
	160	*/
	161	void board_preboot_os(void)
	162	{
	163	gpio_direction_output(GPIO_PWM_A, 1);
	164	gpio_direction_output(GPIO_BL_ON, 0);
	165	}
	166
ae440ab0 SA	167	static void setup_iomux_uart(void)
	168	{
	169	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	170	}
	171
ae440ab0	172	#ifdef CONFIG_FEC_MXC
ae440ab0 SA	173	static int setup_fec(void)
	174	{
	175	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
	176	= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	177
	178	#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
	179	/*
	180	* Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
	181	* and output it on the pin
	182	*/
	183	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
	184	IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
	185	IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
	186	#else
	187	/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
	188	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
	189	IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
	190	IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
	191	#endif
	192
8590786a	193	return set_clk_enet(ENET_50MHZ);
ae440ab0 SA	194	}
ae440ab0 SA	195
ae440ab0 SA	196	#endif
	197
	198	int board_early_init_f(void)
	199	{
	200	setup_iomux_uart();
	201
ae440ab0 SA	202	return 0;
	203	}
	204
	205	int board_init(void)
	206	{
	207	/* address of boot parameters */
	208	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	209
	210	#ifdef CONFIG_FEC_MXC
	211	setup_fec();
	212	#endif
	213
a62c6061	214	#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
ae440ab0 SA	215	setup_gpmi_nand();
	216	#endif
	217
	218	#ifdef CONFIG_VIDEO_MXS
	219	setup_lcd();
	220	#endif
	221
5a986dfe SA	222	#ifdef CONFIG_USB_EHCI_MX7
	223	imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
	224	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
	225	#endif
	226
ae440ab0 SA	227	return 0;
	228	}
	229
02ad90ec SA	230	#ifdef CONFIG_DM_PMIC
	231	int power_init_board(void)
	232	{
	233	struct udevice *dev;
	234	int reg, ver;
	235	int ret;
	236
	237
792b2536	238	ret = pmic_get("rn5t567@33", &dev);
02ad90ec SA	239	if (ret)
	240	return ret;
	241	ver = pmic_reg_read(dev, RN5T567_LSIVER);
	242	reg = pmic_reg_read(dev, RN5T567_OTPVER);
	243
	244	printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
	245
	246	/* set judge and press timer of N_OE to minimal values */
	247	pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
	248
05ed964d SA	249	/* configure sleep slot for 3.3V Ethernet */
	250	reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
	251	reg = (reg & 0xf0) \| reg >> 4;
	252	pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
	253
	254	/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
	255	pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
	256
	257	/* configure sleep slot for ARM rail */
	258	reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
	259	reg = (reg & 0xf0) \| reg >> 4;
	260	pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
	261
	262	/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
	263	pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
	264
02ad90ec SA	265	return 0;
	266	}
	267
	268	void reset_cpu(ulong addr)
	269	{
	270	struct udevice *dev;
	271
792b2536	272	pmic_get("rn5t567@33", &dev);
02ad90ec SA	273
	274	/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
	275	pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
	276	pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
	277
	278	/*
	279	* Re-power factor detection on PMIC side is not instant. 1ms
	280	* proved to be enough time until reset takes effect.
	281	*/
	282	mdelay(1);
	283	}
	284	#endif
	285
ae440ab0 SA	286	int checkboard(void)
	287	{
	288	printf("Model: Toradex Colibri iMX7%c\n",
	289	is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
	290
	291	return 0;
	292	}
	293
37fa4125	294	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
b75d8dc5	295	int ft_board_setup(void blob, struct bd_info bd)
37fa4125	296	{
c671d8af IO	297	#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
	298	int up;
	299
	300	up = arch_auxiliary_core_check_up(0);
	301	if (up) {
	302	int ret;
	303	int areas = 1;
	304	u64 start[2], size[2];
	305
	306	/*
	307	* Reserve 1MB of memory for M4 (1MiB is also the minimum
	308	* alignment for Linux due to MMU section size restrictions).
	309	*/
	310	start[0] = gd->bd->bi_dram[0].start;
	311	size[0] = SZ_256M - SZ_1M;
	312
	313	/* If needed, create a second entry for memory beyond 256M */
	314	if (gd->bd->bi_dram[0].size > SZ_256M) {
	315	start[1] = gd->bd->bi_dram[0].start + SZ_256M;
	316	size[1] = gd->bd->bi_dram[0].size - SZ_256M;
	317	areas = 2;
	318	}
	319
	320	ret = fdt_set_usable_memory(blob, start, size, areas);
	321	if (ret) {
	322	eprintf("Cannot set usable memory\n");
	323	return ret;
	324	}
	325	} else {
	326	int off;
	327
	328	off = fdt_node_offset_by_compatible(blob, -1,
	329	"fsl,imx7d-rpmsg");
	330	if (off > 0)
	331	fdt_status_disabled(blob, off);
	332	}
	333	#endif
64095704	334	#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
b35fb6ac	335	static const struct node_info nodes[] = {
64095704	336	{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
e38adcec	337	{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
64095704 SA	338	};
	339
	340	/* Update partition nodes using info from mtdparts env var */
	341	puts(" Updating MTD partitions...\n");
	342	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
	343	#endif
	344
37fa4125 SA	345	return ft_common_board_setup(blob, bd);
	346	}
	347	#endif
	348
ae440ab0 SA	349	#ifdef CONFIG_USB_EHCI_MX7
	350	static iomux_v3_cfg_t const usb_otg2_pads[] = {
	351	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL),
	352	};
	353
	354	int board_ehci_hcd_init(int port)
	355	{
	356	switch (port) {
	357	case 0:
	358	break;
	359	case 1:
	360	if (is_cpu_type(MXC_CPU_MX7S))
	361	return -ENODEV;
	362
	363	imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
	364	ARRAY_SIZE(usb_otg2_pads));
	365	break;
	366	default:
	367	return -EINVAL;
	368	}
	369	return 0;
	370	}
5a986dfe SA	371
	372	int board_usb_phy_mode(int port)
	373	{
	374	switch (port) {
	375	case 0:
	376	if (gpio_get_value(USB_CDET_GPIO))
	377	return USB_INIT_DEVICE;
	378	else
	379	return USB_INIT_HOST;
	380	case 1:
	381	default:
	382	return USB_INIT_HOST;
	383	}
	384	}
ae440ab0	385	#endif