[J-u-boot.git] / board / freescale / mpc8569mds / mpc8569mds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2009-2010 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <[email protected]>
 */

#include <common.h>
#include <console.h>
#include <flash.h>
#include <hwconfig.h>
#include <init.h>
#include <log.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <phy.h>

#include "bcsr.h"
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* QE_MUX_MDC */
	{2,  31, 1, 0, 1}, /* QE_MUX_MDC               */

	/* QE_MUX_MDIO */
	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */

#if defined(CONFIG_SYS_UCC_RGMII_MODE)
	/* UCC_1_RGMII */
	{2, 11, 2, 0, 1}, /* CLK12 */
	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
	{0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
	{0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
	{0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
	{0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
	{2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */

	/* UCC_2_RGMII */
	{2, 16, 2, 0, 3}, /* CLK17 */
	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */

	/* UCC_3_RGMII */
	{2, 11, 2, 0, 1}, /* CLK12 */
	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */

	/* UCC_4_RGMII */
	{2, 16, 2, 0, 3}, /* CLK17 */
	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */

#elif defined(CONFIG_SYS_UCC_RMII_MODE)
	/* UCC_1_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */

	/* UCC_2_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */

	/* UCC_3_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */

	/* UCC_4_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
#endif

	/* UART1 is muxed with QE PortF bit [9-12].*/
	{5, 12, 2, 0, 3}, /* UART1_SIN */
	{5, 9,  1, 0, 3}, /* UART1_SOUT */
	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
	{5, 11, 1, 0, 2}, /* UART1_RTS_B */

	/* QE UART                                     */
	{0, 19, 1, 0, 2}, /* QEUART_TX                 */
	{1, 17, 2, 0, 3}, /* QEUART_RX                 */
	{0, 25, 1, 0, 1}, /* QEUART_RTS                */
	{1, 23, 2, 0, 1}, /* QEUART_CTS                */

	/* QE USB                                      */
	{5,  3, 1, 0, 1}, /* USB_OE                    */
	{5,  4, 1, 0, 2}, /* USB_TP                    */
	{5,  5, 1, 0, 2}, /* USB_TN                    */
	{5,  6, 2, 0, 2}, /* USB_RP                    */
	{5,  7, 2, 0, 1}, /* USB_RX                    */
	{5,  8, 2, 0, 1}, /* USB_RN                    */
	{2,  4, 2, 0, 2}, /* CLK5                      */

	/* SPI Flash, M25P40                           */
	{4, 27, 3, 0, 1}, /* SPI_MOSI                  */
	{4, 28, 3, 0, 1}, /* SPI_MISO                  */
	{4, 29, 3, 0, 1}, /* SPI_CLK                   */
	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */

	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
};

void local_bus_init(void);

int board_early_init_f (void)
{
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	enable_8569mds_flash_write();

#ifdef CONFIG_QE
	enable_8569mds_qe_uec();
#endif

#if CONFIG_SYS_I2C2_OFFSET
	/* Enable I2C2 signals instead of SD signals */
	volatile struct ccsr_gur *gur;
	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
	gur->plppar1 |= PLPPAR1_I2C2_VAL;
	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
	gur->plpdir1 |= PLPDIR1_I2C2_VAL;

	disable_8569mds_brd_eeprom_write_protect();
#endif

	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
	const u8 flash_esel = 0;

	/*
	 * Remap Boot flash to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,	/* tlb, epn, rpn */
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
		0, flash_esel,				/* ts, esel */
		BOOKE_PAGESZ_64M, 1);			/* tsize, iprot */

	return 0;
}

int checkboard (void)
{
	printf ("Board: 8569 MDS\n");

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
	struct ccsr_ddr __iomem *ddr =
		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
	uint d_init;

	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
#if defined (CONFIG_DDR_ECC)
	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
#endif
	udelay(500);

	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
		udelay(1000);
	}
	debug("DDR: memory initialized\n\n");
	udelay(500);
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;

	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	if (clkdiv == 16)
		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	else if (clkdiv == 8)
		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	else if (clkdiv == 4)
		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);

	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
}

static void fdt_board_disable_serial(void *blob, struct bd_info *bd,
				     const char *alias)
{
	const char *status = "disabled";
	int off;
	int err;

	off = fdt_path_offset(blob, alias);
	if (off < 0) {
		printf("WARNING: could not find %s alias: %s.\n", alias,
			fdt_strerror(off));
		return;
	}

	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
	if (err) {
		printf("WARNING: could not set status for serial0: %s.\n",
			fdt_strerror(err));
		return;
	}
}

/*
 * Because of an erratum in prototype boards it is impossible to use eSDHC
 * without disabling UART0 (which makes it quite easy to 'brick' the board
 * by simply issung 'setenv hwconfig esdhc', and not able to interact with
 * U-Boot anylonger).
 *
 * So, but default we assume that the board is a prototype, which is a most
 * safe assumption. There is no way to determine board revision from a
 * register, so we use hwconfig.
 */

static int prototype_board(void)
{
	if (hwconfig_subarg("board", "rev", NULL))
		return hwconfig_subarg_cmp("board", "rev", "prototype");
	return 1;
}

static int esdhc_disables_uart0(void)
{
	return prototype_board() ||
	       hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
}

static void fdt_board_fixup_qe_uart(void *blob, struct bd_info *bd)
{
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
	const char *devtype = "serial";
	const char *compat = "ucc_uart";
	const char *clk = "brg9";
	u32 portnum = 0;
	int off = -1;

	if (!hwconfig("qe_uart"))
		return;

	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
		printf("QE UART: won't enable with esdhc.\n");
		return;
	}

	fdt_board_disable_serial(blob, bd, "serial1");

	while (1) {
		const u32 *idx;
		int len;

		off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
		if (off < 0) {
			printf("WARNING: unable to fixup device tree for "
				"QE UART\n");
			return;
		}

		idx = fdt_getprop(blob, off, "cell-index", &len);
		if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
			continue;
		break;
	}

	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));

	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
}

#ifdef CONFIG_FSL_ESDHC

int board_mmc_init(struct bd_info *bd)
{
	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
	u8 bcsr6 = BCSR6_SD_CARD_1BIT;

	if (!hwconfig("esdhc"))
		return 0;

	printf("Enabling eSDHC...\n"
	       "  For eSDHC to function, I2C2 ");
	if (esdhc_disables_uart0()) {
		printf("and UART0 should be disabled.\n");
		printf("  Redirecting stderr, stdout and stdin to UART1...\n");
		console_assign(stderr, "eserial1");
		console_assign(stdout, "eserial1");
		console_assign(stdin, "eserial1");
		printf("Switched to UART1 (initial log has been printed to "
		       "UART0).\n");

		clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
					       PLPPAR1_ESDHC_4BITS_VAL);
		clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
					       PLPDIR1_ESDHC_4BITS_VAL);
		bcsr6 |= BCSR6_SD_CARD_4BITS;
	} else {
		printf("should be disabled.\n");
	}

	/* Assign I2C2 signals to eSDHC. */
	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
				       PLPPAR1_ESDHC_VAL);
	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
				       PLPDIR1_ESDHC_VAL);

	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
	setbits_8(&bcsr[6], bcsr6);

	return fsl_esdhc_mmc_init(bd);
}

static void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd)
{
	const char *status = "disabled";
	int off = -1;

	if (!hwconfig("esdhc"))
		return;

	if (esdhc_disables_uart0())
		fdt_board_disable_serial(blob, bd, "serial0");

	while (1) {
		const u32 *idx;
		int len;

		off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
		if (off < 0)
			break;

		idx = fdt_getprop(blob, off, "cell-index", &len);
		if (!idx || len != sizeof(*idx))
			continue;

		if (*idx == 1) {
			fdt_setprop(blob, off, "status", status,
				    strlen(status) + 1);
			break;
		}
	}

	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
		off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
		if (off < 0) {
			printf("WARNING: could not find esdhc node\n");
			return;
		}
		fdt_delprop(blob, off, "sdhci,1-bit-only");
	}
}
#else
static inline void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd) {}
#endif

static void fdt_board_fixup_qe_usb(void *blob, struct bd_info *bd)
{
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;

	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
		clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
	else
		setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);

	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
		clrbits_8(&bcsr[17], BCSR17_USBVCC);
		clrbits_8(&bcsr[17], BCSR17_USBMODE);
		do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
				   "peripheral", sizeof("peripheral"), 1);
	} else {
		setbits_8(&bcsr[17], BCSR17_USBVCC);
		setbits_8(&bcsr[17], BCSR17_USBMODE);
	}

	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
#if defined(CONFIG_PQ_MDS_PIB)
	pib_init();
#endif

	fsl_pcie_init_board(0);
}
#endif /* CONFIG_PCI */

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
#if defined(CONFIG_SYS_UCC_RMII_MODE)
	int nodeoff, off, err;
	unsigned int val;
	const u32 *ph;
	const u32 *index;

	/* fixup device tree for supporting rmii mode */
	nodeoff = -1;
	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
				"ucc_geth")) >= 0) {
		err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
						"clk16");
		if (err < 0) {
			printf("WARNING: could not set tx-clock-name %s.\n",
				fdt_strerror(err));
			break;
		}

		err = fdt_fixup_phy_connection(blob, nodeoff,
				PHY_INTERFACE_MODE_RMII);

		if (err < 0) {
			printf("WARNING: could not set phy-connection-type "
				"%s.\n", fdt_strerror(err));
			break;
		}

		index = fdt_getprop(blob, nodeoff, "cell-index", 0);
		if (index == NULL) {
			printf("WARNING: could not get cell-index of ucc\n");
			break;
		}

		ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
		if (ph == NULL) {
			printf("WARNING: could not get phy-handle of ucc\n");
			break;
		}

		off = fdt_node_offset_by_phandle(blob, *ph);
		if (off < 0) {
			printf("WARNING: could not get phy node	%s.\n",
				fdt_strerror(err));
			break;
		}

		val = 0x7 + *index; /* RMII phy address starts from 0x8 */

		err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
		if (err < 0) {
			printf("WARNING: could not set reg for phy-handle "
				"%s.\n", fdt_strerror(err));
			break;
		}
	}
#endif
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

	fdt_board_fixup_esdhc(blob, bd);
	fdt_board_fixup_qe_uart(blob, bd);
	fdt_board_fixup_qe_usb(blob, bd);

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
765547dc	2	/*
6525d51f	3	* Copyright 2009-2010 Freescale Semiconductor.
765547dc HW	4	*
765547dc HW	5	* (C) Copyright 2002 Scott McNutt <[email protected]>
765547dc HW	6	*/
	7
	8	#include <common.h>
24b852a7	9	#include <console.h>
b79fdc76	10	#include <flash.h>
7f52ed5e	11	#include <hwconfig.h>
5255932f	12	#include <init.h>
f7ae49fc	13	#include <log.h>
765547dc HW	14	#include <pci.h>
	15	#include <asm/processor.h>
	16	#include <asm/mmu.h>
3aed5507	17	#include <asm/cache.h>
765547dc	18	#include <asm/immap_85xx.h>
c8514622	19	#include <asm/fsl_pci.h>
5614e71b	20	#include <fsl_ddr_sdram.h>
5d27e02c	21	#include <asm/fsl_serdes.h>
765547dc HW	22	#include <asm/io.h>
	23	#include <spd_sdram.h>
	24	#include <i2c.h>
	25	#include <ioports.h>
c05ed00a	26	#include <linux/delay.h>
b08c8c48	27	#include <linux/libfdt.h>
765547dc	28	#include <fdt_support.h>
7f52ed5e	29	#include <fsl_esdhc.h>
865ff856	30	#include <phy.h>
765547dc HW	31
765547dc HW	32	#include "bcsr.h"
d9180382 LY	33	#if defined(CONFIG_PQ_MDS_PIB)
	34	#include "../common/pq-mds-pib.h"
	35	#endif
765547dc	36
765547dc HW	37	const qe_iop_conf_t qe_iop_conf_tab[] = {
	38	/* QE_MUX_MDC */
	39	{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
	40
	41	/* QE_MUX_MDIO */
	42	{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
	43
f82107f6	44	#if defined(CONFIG_SYS_UCC_RGMII_MODE)
765547dc HW	45	/* UCC_1_RGMII */
	46	{2, 11, 2, 0, 1}, /* CLK12 */
	47	{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
	48	{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
	49	{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
	50	{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
	51	{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
	52	{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
	53	{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
	54	{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
	55	{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
	56	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
	57	{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
	58	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
	59
	60	/* UCC_2_RGMII */
	61	{2, 16, 2, 0, 3}, /* CLK17 */
	62	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
	63	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
	64	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
	65	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
	66	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
	67	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
	68	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
	69	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
	70	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
	71	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
	72	{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
	73	{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
	74
750098d3 HW	75	/* UCC_3_RGMII */
	76	{2, 11, 2, 0, 1}, /* CLK12 */
	77	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
	78	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
	79	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
	80	{1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
	81	{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
	82	{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
	83	{1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
	84	{1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
	85	{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
	86	{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
	87	{2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
	88	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
	89
	90	/* UCC_4_RGMII */
	91	{2, 16, 2, 0, 3}, /* CLK17 */
	92	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
	93	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
	94	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
	95	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
	96	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
	97	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
	98	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
	99	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
	100	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
	101	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
	102	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
	103	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
	104
f82107f6 HW	105	#elif defined(CONFIG_SYS_UCC_RMII_MODE)
	106	/* UCC_1_RMII */
	107	{2, 15, 2, 0, 1}, /* CLK16 */
	108	{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
	109	{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
	110	{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
	111	{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
	112	{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
	113	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
	114
	115	/* UCC_2_RMII */
	116	{2, 15, 2, 0, 1}, /* CLK16 */
	117	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
	118	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
	119	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
	120	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
	121	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
	122	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
	123
	124	/* UCC_3_RMII */
	125	{2, 15, 2, 0, 1}, /* CLK16 */
	126	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
	127	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
	128	{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
	129	{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
	130	{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
	131	{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
	132
	133	/* UCC_4_RMII */
	134	{2, 15, 2, 0, 1}, /* CLK16 */
	135	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
	136	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
	137	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
	138	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
	139	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
	140	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
	141	#endif
	142
b2aab386 HW	143	/* UART1 is muxed with QE PortF bit [9-12].*/
	144	{5, 12, 2, 0, 3}, /* UART1_SIN */
	145	{5, 9, 1, 0, 3}, /* UART1_SOUT */
	146	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
	147	{5, 11, 1, 0, 2}, /* UART1_RTS_B */
	148
14809b6c AV	149	/* QE UART */
	150	{0, 19, 1, 0, 2}, /* QEUART_TX */
	151	{1, 17, 2, 0, 3}, /* QEUART_RX */
	152	{0, 25, 1, 0, 1}, /* QEUART_RTS */
	153	{1, 23, 2, 0, 1}, /* QEUART_CTS */
	154
3fca8037 AV	155	/* QE USB */
	156	{5, 3, 1, 0, 1}, /* USB_OE */
	157	{5, 4, 1, 0, 2}, /* USB_TP */
	158	{5, 5, 1, 0, 2}, /* USB_TN */
	159	{5, 6, 2, 0, 2}, /* USB_RP */
	160	{5, 7, 2, 0, 1}, /* USB_RX */
	161	{5, 8, 2, 0, 1}, /* USB_RN */
	162	{2, 4, 2, 0, 2}, /* CLK5 */
	163
70d665b1 AV	164	/* SPI Flash, M25P40 */
	165	{4, 27, 3, 0, 1}, /* SPI_MOSI */
	166	{4, 28, 3, 0, 1}, /* SPI_MISO */
	167	{4, 29, 3, 0, 1}, /* SPI_CLK */
	168	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
	169
765547dc HW	170	{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
	171	};
	172
	173	void local_bus_init(void);
	174
	175	int board_early_init_f (void)
	176	{
	177	/*
	178	* Initialize local bus.
	179	*/
	180	local_bus_init ();
	181
	182	enable_8569mds_flash_write();
	183
	184	#ifdef CONFIG_QE
f82107f6	185	enable_8569mds_qe_uec();
765547dc HW	186	#endif
	187
	188	#if CONFIG_SYS_I2C2_OFFSET
	189	/* Enable I2C2 signals instead of SD signals */
	190	volatile struct ccsr_gur *gur;
	191	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
	192	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
	193	gur->plppar1 \|= PLPPAR1_I2C2_VAL;
	194	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
	195	gur->plpdir1 \|= PLPDIR1_I2C2_VAL;
	196
	197	disable_8569mds_brd_eeprom_write_protect();
	198	#endif
	199
	200	return 0;
	201	}
	202
3aed5507 HW	203	int board_early_init_r(void)
	204	{
	205	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
	206	const u8 flash_esel = 0;
	207
	208	/*
	209	* Remap Boot flash to caching-inhibited
	210	* so that flash can be erased properly.
	211	*/
	212
	213	/* Flush d-cache and invalidate i-cache of any FLASH data */
	214	flush_dcache();
	215	invalidate_icache();
	216
	217	/* invalidate existing TLB entry for flash */
	218	disable_tlb(flash_esel);
	219
	220	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
	221	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G, /* perms, wimge */
	222	0, flash_esel, /* ts, esel */
	223	BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
	224
	225	return 0;
	226	}
	227
765547dc HW	228	int checkboard (void)
	229	{
	230	printf ("Board: 8569 MDS\n");
	231
	232	return 0;
	233	}
	234
765547dc HW	235	#if !defined(CONFIG_SPD_EEPROM)
	236	phys_size_t fixed_sdram(void)
	237	{
9a17eb5b YS	238	struct ccsr_ddr __iomem *ddr =
9a17eb5b YS	239	(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
765547dc HW	240	uint d_init;
	241
	242	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
	243	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
	244	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
	245	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
	246	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
	247	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
	248	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
	249	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
	250	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
	251	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
	252	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
	253	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
	254	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
	255	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
	256	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
	257	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
	258	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
	259	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
	260	#if defined (CONFIG_DDR_ECC)
	261	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
	262	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
	263	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
	264	#endif
	265	udelay(500);
	266
	267	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
	268	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	269	d_init = 1;
	270	debug("DDR - 1st controller: memory initializing\n");
	271	/*
	272	* Poll until memory is initialized.
	273	* 512 Meg at 400 might hit this 200 times or so.
	274	*/
	275	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
	276	udelay(1000);
	277	}
	278	debug("DDR: memory initialized\n\n");
	279	udelay(500);
	280	#endif
	281	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	282	}
	283	#endif
	284
	285	/*
	286	* Initialize Local Bus
	287	*/
	288	void
	289	local_bus_init(void)
	290	{
	291	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	292	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
765547dc HW	293
765547dc HW	294	uint clkdiv;
765547dc HW	295	sys_info_t sysinfo;
	296
	297	get_sys_info(&sysinfo);
	298	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
765547dc HW	299
	300	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	301	if (clkdiv == 16)
	302	out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	303	else if (clkdiv == 8)
	304	out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	305	else if (clkdiv == 4)
	306	out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
	307
	308	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)\| 0x00030000);
	309	}
	310
b75d8dc5 MY	311	static void fdt_board_disable_serial(void blob, struct bd_info bd,
b75d8dc5 MY	312	const char *alias)
14809b6c AV	313	{
	314	const char *status = "disabled";
	315	int off;
	316	int err;
	317
	318	off = fdt_path_offset(blob, alias);
	319	if (off < 0) {
	320	printf("WARNING: could not find %s alias: %s.\n", alias,
	321	fdt_strerror(off));
	322	return;
	323	}
	324
	325	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
	326	if (err) {
	327	printf("WARNING: could not set status for serial0: %s.\n",
	328	fdt_strerror(err));
	329	return;
	330	}
	331	}
7f52ed5e AV	332
	333	/*
	334	* Because of an erratum in prototype boards it is impossible to use eSDHC
	335	* without disabling UART0 (which makes it quite easy to 'brick' the board
	336	* by simply issung 'setenv hwconfig esdhc', and not able to interact with
	337	* U-Boot anylonger).
	338	*
	339	* So, but default we assume that the board is a prototype, which is a most
	340	* safe assumption. There is no way to determine board revision from a
	341	* register, so we use hwconfig.
	342	*/
	343
	344	static int prototype_board(void)
	345	{
	346	if (hwconfig_subarg("board", "rev", NULL))
	347	return hwconfig_subarg_cmp("board", "rev", "prototype");
	348	return 1;
	349	}
	350
	351	static int esdhc_disables_uart0(void)
	352	{
	353	return prototype_board() \|\|
	354	hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
	355	}
	356
b75d8dc5	357	static void fdt_board_fixup_qe_uart(void blob, struct bd_info bd)
14809b6c AV	358	{
	359	u8 bcsr = (u8 )CONFIG_SYS_BCSR_BASE;
	360	const char *devtype = "serial";
	361	const char *compat = "ucc_uart";
	362	const char *clk = "brg9";
	363	u32 portnum = 0;
	364	int off = -1;
	365
	366	if (!hwconfig("qe_uart"))
	367	return;
	368
	369	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
	370	printf("QE UART: won't enable with esdhc.\n");
	371	return;
	372	}
	373
	374	fdt_board_disable_serial(blob, bd, "serial1");
	375
	376	while (1) {
	377	const u32 *idx;
	378	int len;
	379
	380	off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
	381	if (off < 0) {
	382	printf("WARNING: unable to fixup device tree for "
	383	"QE UART\n");
	384	return;
	385	}
	386
	387	idx = fdt_getprop(blob, off, "cell-index", &len);
	388	if (!idx \|\| len != sizeof(idx) \|\| idx != fdt32_to_cpu(2))
	389	continue;
	390	break;
	391	}
	392
	393	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
	394	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
	395	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
	396	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
	397	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
	398
	399	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
	400	}
	401
	402	#ifdef CONFIG_FSL_ESDHC
	403
b75d8dc5	404	int board_mmc_init(struct bd_info *bd)
7f52ed5e AV	405	{
	406	struct ccsr_gur gur = (struct ccsr_gur )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	407	u8 bcsr = (u8 )CONFIG_SYS_BCSR_BASE;
	408	u8 bcsr6 = BCSR6_SD_CARD_1BIT;
	409
	410	if (!hwconfig("esdhc"))
	411	return 0;
	412
	413	printf("Enabling eSDHC...\n"
	414	" For eSDHC to function, I2C2 ");
	415	if (esdhc_disables_uart0()) {
	416	printf("and UART0 should be disabled.\n");
	417	printf(" Redirecting stderr, stdout and stdin to UART1...\n");
	418	console_assign(stderr, "eserial1");
	419	console_assign(stdout, "eserial1");
	420	console_assign(stdin, "eserial1");
	421	printf("Switched to UART1 (initial log has been printed to "
	422	"UART0).\n");
c4ca10f1 AV	423
	424	clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
	425	PLPPAR1_ESDHC_4BITS_VAL);
	426	clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
	427	PLPDIR1_ESDHC_4BITS_VAL);
7f52ed5e AV	428	bcsr6 \|= BCSR6_SD_CARD_4BITS;
	429	} else {
	430	printf("should be disabled.\n");
	431	}
	432
	433	/* Assign I2C2 signals to eSDHC. */
	434	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
	435	PLPPAR1_ESDHC_VAL);
	436	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
	437	PLPDIR1_ESDHC_VAL);
	438
	439	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
	440	setbits_8(&bcsr[6], bcsr6);
	441
	442	return fsl_esdhc_mmc_init(bd);
	443	}
	444
b75d8dc5	445	static void fdt_board_fixup_esdhc(void blob, struct bd_info bd)
7f52ed5e AV	446	{
7f52ed5e AV	447	const char *status = "disabled";
14809b6c	448	int off = -1;
7f52ed5e AV	449
	450	if (!hwconfig("esdhc"))
	451	return;
	452
14809b6c AV	453	if (esdhc_disables_uart0())
14809b6c AV	454	fdt_board_disable_serial(blob, bd, "serial0");
7f52ed5e	455
7f52ed5e AV	456	while (1) {
	457	const u32 *idx;
	458	int len;
	459
	460	off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
	461	if (off < 0)
	462	break;
	463
	464	idx = fdt_getprop(blob, off, "cell-index", &len);
	465	if (!idx \|\| len != sizeof(*idx))
	466	continue;
	467
	468	if (*idx == 1) {
	469	fdt_setprop(blob, off, "status", status,
	470	strlen(status) + 1);
	471	break;
	472	}
	473	}
c4ca10f1 AV	474
	475	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
	476	off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
	477	if (off < 0) {
	478	printf("WARNING: could not find esdhc node\n");
	479	return;
	480	}
	481	fdt_delprop(blob, off, "sdhci,1-bit-only");
	482	}
7f52ed5e AV	483	}
7f52ed5e AV	484	#else
b75d8dc5	485	static inline void fdt_board_fixup_esdhc(void blob, struct bd_info bd) {}
7f52ed5e AV	486	#endif
7f52ed5e AV	487
b75d8dc5	488	static void fdt_board_fixup_qe_usb(void blob, struct bd_info bd)
3fca8037 AV	489	{
	490	u8 bcsr = (u8 )CONFIG_SYS_BCSR_BASE;
	491
	492	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
	493	clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
	494	else
	495	setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
	496
	497	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
	498	clrbits_8(&bcsr[17], BCSR17_USBVCC);
	499	clrbits_8(&bcsr[17], BCSR17_USBMODE);
	500	do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
	501	"peripheral", sizeof("peripheral"), 1);
	502	} else {
	503	setbits_8(&bcsr[17], BCSR17_USBVCC);
	504	setbits_8(&bcsr[17], BCSR17_USBMODE);
	505	}
	506
	507	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
	508	}
	509
765547dc	510	#ifdef CONFIG_PCI
c847e98b	511	void pci_init_board(void)
765547dc	512	{
d9180382 LY	513	#if defined(CONFIG_PQ_MDS_PIB)
	514	pib_init();
	515	#endif
	516
94f2bc48	517	fsl_pcie_init_board(0);
765547dc HW	518	}
	519	#endif /* CONFIG_PCI */
	520
	521	#if defined(CONFIG_OF_BOARD_SETUP)
b75d8dc5	522	int ft_board_setup(void blob, struct bd_info bd)
765547dc	523	{
f82107f6 HW	524	#if defined(CONFIG_SYS_UCC_RMII_MODE)
	525	int nodeoff, off, err;
	526	unsigned int val;
	527	const u32 *ph;
	528	const u32 *index;
	529
	530	/* fixup device tree for supporting rmii mode */
	531	nodeoff = -1;
	532	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
	533	"ucc_geth")) >= 0) {
	534	err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
	535	"clk16");
	536	if (err < 0) {
	537	printf("WARNING: could not set tx-clock-name %s.\n",
	538	fdt_strerror(err));
	539	break;
	540	}
	541
865ff856 AF	542	err = fdt_fixup_phy_connection(blob, nodeoff,
865ff856 AF	543	PHY_INTERFACE_MODE_RMII);
a1964ea5	544
f82107f6 HW	545	if (err < 0) {
	546	printf("WARNING: could not set phy-connection-type "
	547	"%s.\n", fdt_strerror(err));
	548	break;
	549	}
	550
	551	index = fdt_getprop(blob, nodeoff, "cell-index", 0);
	552	if (index == NULL) {
	553	printf("WARNING: could not get cell-index of ucc\n");
	554	break;
	555	}
	556
	557	ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
	558	if (ph == NULL) {
	559	printf("WARNING: could not get phy-handle of ucc\n");
	560	break;
	561	}
	562
	563	off = fdt_node_offset_by_phandle(blob, *ph);
	564	if (off < 0) {
	565	printf("WARNING: could not get phy node %s.\n",
	566	fdt_strerror(err));
	567	break;
	568	}
	569
	570	val = 0x7 + index; / RMII phy address starts from 0x8 */
	571
	572	err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
	573	if (err < 0) {
	574	printf("WARNING: could not set reg for phy-handle "
	575	"%s.\n", fdt_strerror(err));
	576	break;
	577	}
	578	}
	579	#endif
765547dc HW	580	ft_cpu_setup(blob, bd);
765547dc HW	581
6525d51f KG	582	FT_FSL_PCI_SETUP;
6525d51f KG	583
7f52ed5e	584	fdt_board_fixup_esdhc(blob, bd);
14809b6c	585	fdt_board_fixup_qe_uart(blob, bd);
3fca8037	586	fdt_board_fixup_qe_usb(blob, bd);
e895a4b0 SG	587
e895a4b0 SG	588	return 0;
765547dc HW	589	}
765547dc HW	590	#endif