[J-u-boot.git] / board / freescale / mpc837xemds / pci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
 */

#include <init.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <env.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <fdt_support.h>
#include <asm/fsl_i2c.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <linux/delay.h>

static struct pci_region pci_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI_MEM_BASE,
		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
		size: CONFIG_SYS_PCI_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
		size: CONFIG_SYS_PCI_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
	{
		bus_start: CONFIG_SYS_PCI_IO_BASE,
		phys_start: CONFIG_SYS_PCI_IO_PHYS,
		size: CONFIG_SYS_PCI_IO_SIZE,
		flags: PCI_REGION_IO
	}
};

static struct pci_region pcie_regions_0[] = {
	{
		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
		.flags = PCI_REGION_MEM,
	},
	{
		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
		.size = CONFIG_SYS_PCIE1_IO_SIZE,
		.flags = PCI_REGION_IO,
	},
};

static struct pci_region pcie_regions_1[] = {
	{
		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
		.flags = PCI_REGION_MEM,
	},
	{
		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
		.size = CONFIG_SYS_PCIE2_IO_SIZE,
		.flags = PCI_REGION_IO,
	},
};

static int is_pex_x2(void)
{
	const char *pex_x2 = env_get("pex_x2");

	if (pex_x2 && !strcmp(pex_x2, "yes"))
		return 1;
	return 0;
}

void pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile sysconf83xx_t *sysconf = &immr->sysconf;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	volatile law83xx_t *pcie_law = sysconf->pcielaw;
	struct pci_region *reg[] = { pci_regions };
	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
	u32 spridr = in_be32(&immr->sysconf.spridr);
	int pex2 = is_pex_x2();

	if (board_pci_host_broken())
		goto skip_pci;

	/* Enable all 5 PCI_CLK_OUTPUTS */
	clk->occr |= 0xf8000000;
	udelay(2000);

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;

	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;

	udelay(2000);

	mpc83xx_pci_init(1, reg);
skip_pci:
	/* There is no PEX in MPC8379 parts. */
	if (PARTID_NO_E(spridr) == SPR_8379)
		return;

	if (pex2)
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	else
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);

	/* Configure the clock for PCIE controller */
	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);

	/* Deassert the resets in the control register */
	out_be32(&sysconf->pecr1, 0xE0008000);
	if (!pex2)
		out_be32(&sysconf->pecr2, 0xE0008000);
	udelay(2000);

	/* Configure PCI Express Local Access Windows */
	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);

	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);

	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
}

void ft_pcie_fixup(void *blob, struct bd_info *bd)
{
	const char *status = "disabled (PCIE1 is x2)";

	if (!is_pex_x2())
		return;

	do_fixup_by_path(blob, "pci2", "status", status,
			 strlen(status) + 1, 1);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
19580e66	2	/*
9993e196	3	* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
19580e66 DL	4	*/
19580e66 DL	5
2cf431c2	6	#include <init.h>
19580e66 DL	7	#include <asm/mmu.h>
	8	#include <asm/io.h>
	9	#include <common.h>
7b51b576	10	#include <env.h>
19580e66 DL	11	#include <mpc83xx.h>
	12	#include <pci.h>
	13	#include <i2c.h>
8b34557c	14	#include <fdt_support.h>
19580e66	15	#include <asm/fsl_i2c.h>
7e1afb62	16	#include <asm/fsl_mpc83xx_serdes.h>
c05ed00a	17	#include <linux/delay.h>
19580e66	18
19580e66 DL	19	static struct pci_region pci_regions[] = {
19580e66 DL	20	{
6d0f6bcf JCPV	21	bus_start: CONFIG_SYS_PCI_MEM_BASE,
	22	phys_start: CONFIG_SYS_PCI_MEM_PHYS,
	23	size: CONFIG_SYS_PCI_MEM_SIZE,
19580e66 DL	24	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	25	},
	26	{
6d0f6bcf JCPV	27	bus_start: CONFIG_SYS_PCI_MMIO_BASE,
	28	phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
	29	size: CONFIG_SYS_PCI_MMIO_SIZE,
19580e66 DL	30	flags: PCI_REGION_MEM
	31	},
	32	{
6d0f6bcf JCPV	33	bus_start: CONFIG_SYS_PCI_IO_BASE,
	34	phys_start: CONFIG_SYS_PCI_IO_PHYS,
	35	size: CONFIG_SYS_PCI_IO_SIZE,
19580e66 DL	36	flags: PCI_REGION_IO
	37	}
	38	};
	39
8b34557c AV	40	static struct pci_region pcie_regions_0[] = {
	41	{
	42	.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
	43	.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
	44	.size = CONFIG_SYS_PCIE1_MEM_SIZE,
	45	.flags = PCI_REGION_MEM,
	46	},
	47	{
	48	.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
	49	.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
	50	.size = CONFIG_SYS_PCIE1_IO_SIZE,
	51	.flags = PCI_REGION_IO,
	52	},
	53	};
	54
	55	static struct pci_region pcie_regions_1[] = {
	56	{
	57	.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
	58	.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
	59	.size = CONFIG_SYS_PCIE2_MEM_SIZE,
	60	.flags = PCI_REGION_MEM,
	61	},
	62	{
	63	.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
	64	.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
	65	.size = CONFIG_SYS_PCIE2_IO_SIZE,
	66	.flags = PCI_REGION_IO,
	67	},
	68	};
	69
	70	static int is_pex_x2(void)
	71	{
00caae6d	72	const char *pex_x2 = env_get("pex_x2");
8b34557c AV	73
	74	if (pex_x2 && !strcmp(pex_x2, "yes"))
	75	return 1;
	76	return 0;
	77	}
	78
19580e66 DL	79	void pci_init_board(void)
19580e66 DL	80	{
6d0f6bcf	81	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
8b34557c	82	volatile sysconf83xx_t *sysconf = &immr->sysconf;
19580e66 DL	83	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
19580e66 DL	84	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
8b34557c	85	volatile law83xx_t *pcie_law = sysconf->pcielaw;
19580e66	86	struct pci_region *reg[] = { pci_regions };
8b34557c AV	87	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
	88	u32 spridr = in_be32(&immr->sysconf.spridr);
	89	int pex2 = is_pex_x2();
19580e66	90
00f7bbae	91	if (board_pci_host_broken())
8b34557c	92	goto skip_pci;
00f7bbae	93
19580e66 DL	94	/* Enable all 5 PCI_CLK_OUTPUTS */
	95	clk->occr \|= 0xf8000000;
	96	udelay(2000);
	97
	98	/* Configure PCI Local Access Windows */
6d0f6bcf	99	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
19580e66 DL	100	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_512MB;
19580e66 DL	101
6d0f6bcf	102	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
19580e66 DL	103	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
	104
	105	udelay(2000);
	106
6aa3d3bf	107	mpc83xx_pci_init(1, reg);
8b34557c AV	108	skip_pci:
	109	/* There is no PEX in MPC8379 parts. */
	110	if (PARTID_NO_E(spridr) == SPR_8379)
	111	return;
	112
7e2ec1de AV	113	if (pex2)
	114	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
	115	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	116	else
	117	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
	118	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	119
8b34557c AV	120	/* Configure the clock for PCIE controller */
	121	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM \| SCCR_PCIEXP2CM,
	122	SCCR_PCIEXP1CM_1 \| SCCR_PCIEXP2CM_1);
	123
	124	/* Deassert the resets in the control register */
	125	out_be32(&sysconf->pecr1, 0xE0008000);
	126	if (!pex2)
	127	out_be32(&sysconf->pecr2, 0xE0008000);
	128	udelay(2000);
	129
	130	/* Configure PCI Express Local Access Windows */
	131	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	132	out_be32(&pcie_law[0].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	133
	134	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
	135	out_be32(&pcie_law[1].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	136
e2229352	137	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
8b34557c AV	138	}
8b34557c AV	139
b75d8dc5	140	void ft_pcie_fixup(void blob, struct bd_info bd)
8b34557c AV	141	{
	142	const char *status = "disabled (PCIE1 is x2)";
	143
	144	if (!is_pex_x2())
	145	return;
	146
	147	do_fixup_by_path(blob, "pci2", "status", status,
	148	strlen(status) + 1, 1);
19580e66	149	}