[J-u-boot.git] / include / linux / usb / dwc3.h

/* include/linux/usb/dwc3.h
 *
 * Copyright (c) 2012 Samsung Electronics Co. Ltd
 *
 * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __DWC3_H_
#define __DWC3_H_

/* Global constants */
#define DWC3_ENDPOINTS_NUM			32

#define DWC3_EVENT_BUFFERS_SIZE			PAGE_SIZE
#define DWC3_EVENT_TYPE_MASK			0xfe

#define DWC3_EVENT_TYPE_DEV			0
#define DWC3_EVENT_TYPE_CARKIT			3
#define DWC3_EVENT_TYPE_I2C			4

#define DWC3_DEVICE_EVENT_DISCONNECT		0
#define DWC3_DEVICE_EVENT_RESET			1
#define DWC3_DEVICE_EVENT_CONNECT_DONE		2
#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
#define DWC3_DEVICE_EVENT_WAKEUP		4
#define DWC3_DEVICE_EVENT_EOPF			6
#define DWC3_DEVICE_EVENT_SOF			7
#define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
#define DWC3_DEVICE_EVENT_CMD_CMPL		10
#define DWC3_DEVICE_EVENT_OVERFLOW		11

#define DWC3_GEVNTCOUNT_MASK			0xfffc
#define DWC3_GSNPSID_MASK			0xffff0000
#define DWC3_GSNPSID_SHIFT			16
#define DWC3_GSNPSREV_MASK			0xffff

#define DWC3_REVISION_MASK			0xffff

#define DWC3_REG_OFFSET				0xC100

struct g_event_buffer {
	u32 g_evntadrlo;
	u32 g_evntadrhi;
	u32 g_evntsiz;
	u32 g_evntcount;
};

struct d_physical_endpoint {
	u32 d_depcmdpar2;
	u32 d_depcmdpar1;
	u32 d_depcmdpar0;
	u32 d_depcmd;
};

struct dwc3 {					/* offset: 0xC100 */
	u32 g_sbuscfg0;
	u32 g_sbuscfg1;
	u32 g_txthrcfg;
	u32 g_rxthrcfg;
	u32 g_ctl;

	u32 reserved1;

	u32 g_sts;

	u32 reserved2;

	u32 g_snpsid;
	u32 g_gpio;
	u32 g_uid;
	u32 g_uctl;
	u64 g_buserraddr;
	u64 g_prtbimap;

	u32 g_hwparams0;
	u32 g_hwparams1;
	u32 g_hwparams2;
	u32 g_hwparams3;
	u32 g_hwparams4;
	u32 g_hwparams5;
	u32 g_hwparams6;
	u32 g_hwparams7;

	u32 g_dbgfifospace;
	u32 g_dbgltssm;
	u32 g_dbglnmcc;
	u32 g_dbgbmu;
	u32 g_dbglspmux;
	u32 g_dbglsp;
	u32 g_dbgepinfo0;
	u32 g_dbgepinfo1;

	u64 g_prtbimap_hs;
	u64 g_prtbimap_fs;

	u32 reserved3[28];

	u32 g_usb2phycfg[16];
	u32 g_usb2i2cctl[16];
	u32 g_usb2phyacc[16];
	u32 g_usb3pipectl[16];

	u32 g_txfifosiz[32];
	u32 g_rxfifosiz[32];

	struct g_event_buffer g_evnt_buf[32];

	u32 g_hwparams8;

	u32 reserved4[11];

	u32 g_fladj;

	u32 reserved5[51];

	u32 d_cfg;
	u32 d_ctl;
	u32 d_evten;
	u32 d_sts;
	u32 d_gcmdpar;
	u32 d_gcmd;

	u32 reserved6[2];

	u32 d_alepena;

	u32 reserved7[55];

	struct d_physical_endpoint d_phy_ep_cmd[32];

	u32 reserved8[128];

	u32 o_cfg;
	u32 o_ctl;
	u32 o_evt;
	u32 o_evten;
	u32 o_sts;

	u32 reserved9[3];

	u32 adp_cfg;
	u32 adp_ctl;
	u32 adp_evt;
	u32 adp_evten;

	u32 bc_cfg;

	u32 reserved10;

	u32 bc_evt;
	u32 bc_evten;
};

/* Global Configuration Register */
#define DWC3_GCTL_PWRDNSCALE(n)			((n) << 19)
#define DWC3_GCTL_U2RSTECN			(1 << 16)
#define DWC3_GCTL_RAMCLKSEL(x)			\
		(((x) & DWC3_GCTL_CLK_MASK) << 6)
#define DWC3_GCTL_CLK_BUS			(0)
#define DWC3_GCTL_CLK_PIPE			(1)
#define DWC3_GCTL_CLK_PIPEHALF			(2)
#define DWC3_GCTL_CLK_MASK			(3)
#define DWC3_GCTL_PRTCAP(n)			(((n) & (3 << 12)) >> 12)
#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
#define DWC3_GCTL_PRTCAP_HOST			1
#define DWC3_GCTL_PRTCAP_DEVICE			2
#define DWC3_GCTL_PRTCAP_OTG			3
#define DWC3_GCTL_CORESOFTRESET			(1 << 11)
#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)

/* Global HWPARAMS1 Register */
#define DWC3_GHWPARAMS1_EN_PWROPT(n)		(((n) & (3 << 24)) >> 24)
#define DWC3_GHWPARAMS1_EN_PWROPT_NO		0
#define DWC3_GHWPARAMS1_EN_PWROPT_CLK		1

/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST		(1 << 31)
#define DWC3_GUSB2PHYCFG_SUSPHY			(1 << 6)

/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST		(1 << 31)
#define DWC3_GUSB3PIPECTL_SUSPHY		(1 << 17)

/* Global TX Fifo Size Register */
#define DWC3_GTXFIFOSIZ_TXFDEF(n)		((n) & 0xffff)
#define DWC3_GTXFIFOSIZ_TXFSTADDR(n)		((n) & 0xffff0000)

/* Device Control Register */
#define DWC3_DCTL_RUN_STOP			(1 << 31)
#define DWC3_DCTL_CSFTRST			(1 << 30)
#define DWC3_DCTL_LSFTRST			(1 << 29)

/* Global Frame Length Adjustment Register */
#define GFLADJ_30MHZ_REG_SEL			(1 << 7)
#define GFLADJ_30MHZ(n)				((n) & 0x3f)
#define GFLADJ_30MHZ_DEFAULT			0x20

#ifdef CONFIG_USB_XHCI_DWC3
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
int dwc3_core_init(struct dwc3 *dwc3_reg);
void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
#endif
#endif /* __DWC3_H_ */
Commit	Line	Data
13194f3b VG	1	/* include/linux/usb/dwc3.h
	2	*
	3	* Copyright (c) 2012 Samsung Electronics Co. Ltd
	4	*
	5	* Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __DWC3_H_
	11	#define __DWC3_H_
	12
	13	/* Global constants */
	14	#define DWC3_ENDPOINTS_NUM 32
	15
	16	#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
	17	#define DWC3_EVENT_TYPE_MASK 0xfe
	18
	19	#define DWC3_EVENT_TYPE_DEV 0
	20	#define DWC3_EVENT_TYPE_CARKIT 3
	21	#define DWC3_EVENT_TYPE_I2C 4
	22
	23	#define DWC3_DEVICE_EVENT_DISCONNECT 0
	24	#define DWC3_DEVICE_EVENT_RESET 1
	25	#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
	26	#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
	27	#define DWC3_DEVICE_EVENT_WAKEUP 4
	28	#define DWC3_DEVICE_EVENT_EOPF 6
	29	#define DWC3_DEVICE_EVENT_SOF 7
	30	#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
	31	#define DWC3_DEVICE_EVENT_CMD_CMPL 10
	32	#define DWC3_DEVICE_EVENT_OVERFLOW 11
	33
	34	#define DWC3_GEVNTCOUNT_MASK 0xfffc
	35	#define DWC3_GSNPSID_MASK 0xffff0000
	36	#define DWC3_GSNPSID_SHIFT 16
	37	#define DWC3_GSNPSREV_MASK 0xffff
	38
	39	#define DWC3_REVISION_MASK 0xffff
	40
	41	#define DWC3_REG_OFFSET 0xC100
	42
	43	struct g_event_buffer {
bc0e8d7c WK	44	u32 g_evntadrlo;
bc0e8d7c WK	45	u32 g_evntadrhi;
13194f3b VG	46	u32 g_evntsiz;
	47	u32 g_evntcount;
	48	};
	49
	50	struct d_physical_endpoint {
	51	u32 d_depcmdpar2;
	52	u32 d_depcmdpar1;
	53	u32 d_depcmdpar0;
	54	u32 d_depcmd;
	55	};
	56
	57	struct dwc3 { /* offset: 0xC100 */
	58	u32 g_sbuscfg0;
	59	u32 g_sbuscfg1;
	60	u32 g_txthrcfg;
	61	u32 g_rxthrcfg;
	62	u32 g_ctl;
	63
	64	u32 reserved1;
	65
	66	u32 g_sts;
	67
	68	u32 reserved2;
	69
	70	u32 g_snpsid;
	71	u32 g_gpio;
	72	u32 g_uid;
	73	u32 g_uctl;
	74	u64 g_buserraddr;
	75	u64 g_prtbimap;
	76
	77	u32 g_hwparams0;
	78	u32 g_hwparams1;
	79	u32 g_hwparams2;
	80	u32 g_hwparams3;
	81	u32 g_hwparams4;
	82	u32 g_hwparams5;
	83	u32 g_hwparams6;
	84	u32 g_hwparams7;
	85
	86	u32 g_dbgfifospace;
	87	u32 g_dbgltssm;
	88	u32 g_dbglnmcc;
	89	u32 g_dbgbmu;
	90	u32 g_dbglspmux;
	91	u32 g_dbglsp;
	92	u32 g_dbgepinfo0;
	93	u32 g_dbgepinfo1;
	94
	95	u64 g_prtbimap_hs;
	96	u64 g_prtbimap_fs;
	97
	98	u32 reserved3[28];
	99
	100	u32 g_usb2phycfg[16];
	101	u32 g_usb2i2cctl[16];
	102	u32 g_usb2phyacc[16];
	103	u32 g_usb3pipectl[16];
	104
	105	u32 g_txfifosiz[32];
	106	u32 g_rxfifosiz[32];
	107
	108	struct g_event_buffer g_evnt_buf[32];
	109
110	u32 g_hwparams8;
111
667f4dd9 NB	112	u32 reserved4[11];
	113
	114	u32 g_fladj;
	115
	116	u32 reserved5[51];
13194f3b VG	117
	118	u32 d_cfg;
	119	u32 d_ctl;
	120	u32 d_evten;
	121	u32 d_sts;
	122	u32 d_gcmdpar;
	123	u32 d_gcmd;
	124
667f4dd9	125	u32 reserved6[2];
13194f3b VG	126
	127	u32 d_alepena;
	128
667f4dd9	129	u32 reserved7[55];
13194f3b VG	130
	131	struct d_physical_endpoint d_phy_ep_cmd[32];
	132
667f4dd9	133	u32 reserved8[128];
13194f3b VG	134
	135	u32 o_cfg;
	136	u32 o_ctl;
	137	u32 o_evt;
	138	u32 o_evten;
	139	u32 o_sts;
	140
667f4dd9	141	u32 reserved9[3];
13194f3b VG	142
	143	u32 adp_cfg;
	144	u32 adp_ctl;
	145	u32 adp_evt;
	146	u32 adp_evten;
	147
	148	u32 bc_cfg;
	149
667f4dd9	150	u32 reserved10;
13194f3b VG	151
	152	u32 bc_evt;
	153	u32 bc_evten;
	154	};
	155
	156	/* Global Configuration Register */
	157	#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
	158	#define DWC3_GCTL_U2RSTECN (1 << 16)
	159	#define DWC3_GCTL_RAMCLKSEL(x) \
	160	(((x) & DWC3_GCTL_CLK_MASK) << 6)
	161	#define DWC3_GCTL_CLK_BUS (0)
	162	#define DWC3_GCTL_CLK_PIPE (1)
	163	#define DWC3_GCTL_CLK_PIPEHALF (2)
	164	#define DWC3_GCTL_CLK_MASK (3)
	165	#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
	166	#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
	167	#define DWC3_GCTL_PRTCAP_HOST 1
	168	#define DWC3_GCTL_PRTCAP_DEVICE 2
	169	#define DWC3_GCTL_PRTCAP_OTG 3
	170	#define DWC3_GCTL_CORESOFTRESET (1 << 11)
	171	#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
	172	#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
	173	#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
	174	#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
	175
	176	/* Global HWPARAMS1 Register */
	177	#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
	178	#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
	179	#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
	180
	181	/* Global USB2 PHY Configuration Register */
	182	#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
	183	#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
	184
	185	/* Global USB3 PIPE Control Register */
	186	#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
	187	#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
	188
	189	/* Global TX Fifo Size Register */
	190	#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
	191	#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
	192
bc0e8d7c WK	193	/* Device Control Register */
	194	#define DWC3_DCTL_RUN_STOP (1 << 31)
	195	#define DWC3_DCTL_CSFTRST (1 << 30)
	196	#define DWC3_DCTL_LSFTRST (1 << 29)
	197
667f4dd9 NB	198	/* Global Frame Length Adjustment Register */
	199	#define GFLADJ_30MHZ_REG_SEL (1 << 7)
	200	#define GFLADJ_30MHZ(n) ((n) & 0x3f)
	201	#define GFLADJ_30MHZ_DEFAULT 0x20
	202
dc9cdf85 RM	203	#ifdef CONFIG_USB_XHCI_DWC3
	204	void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
	205	void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
	206	int dwc3_core_init(struct dwc3 *dwc3_reg);
667f4dd9	207	void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
dc9cdf85	208	#endif
13194f3b	209	#endif /* __DWC3_H_ */