[J-u-boot.git] / arch / arm / mach-omap2 / am33xx / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * board.c
 *
 * Common board functions for AM33XX based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
 */

#include <config.h>
#include <dm.h>
#include <debug_uart.h>
#include <errno.h>
#include <event.h>
#include <init.h>
#include <net.h>
#include <ns16550.h>
#include <omap3_spi.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/i2c.h>
#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
#include <asm/arch/mem-guardian.h>
#else
#include <asm/arch/mem.h>
#endif
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/compiler.h>
#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
#include <asm/davinci_rtc.h>

#define AM43XX_EMIF_BASE				0x4C000000
#define AM43XX_SDRAM_CONFIG_OFFSET			0x8
#define AM43XX_SDRAM_TYPE_MASK				0xE0000000
#define AM43XX_SDRAM_TYPE_SHIFT				29
#define AM43XX_SDRAM_TYPE_DDR3				3
#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET		0xDC
#define AM43XX_RDWRLVLFULL_START			0x80000000

/* SPI flash. */
#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
#define AM33XX_SPI0_BASE	0x48030000
#define AM33XX_SPI0_OFFSET	(AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
#endif

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
	sdram_init();
#endif

	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size(
			(void *)CFG_SYS_SDRAM_BASE,
			CFG_MAX_RAM_BANK_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = gd->ram_size;

	return 0;
}

#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_plat am33xx_serial[] = {
	{ .base = CFG_SYS_NS16550_COM1, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# ifdef CFG_SYS_NS16550_COM2
	{ .base = CFG_SYS_NS16550_COM2, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
#  ifdef CFG_SYS_NS16550_COM3
	{ .base = CFG_SYS_NS16550_COM3, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	{ .base = CFG_SYS_NS16550_COM4, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	{ .base = CFG_SYS_NS16550_COM5, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	{ .base = CFG_SYS_NS16550_COM6, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
#  endif
# endif
};

U_BOOT_DRVINFOS(am33xx_uarts) = {
	{ "ns16550_serial", &am33xx_serial[0] },
#  ifdef CFG_SYS_NS16550_COM2
	{ "ns16550_serial", &am33xx_serial[1] },
#   ifdef CFG_SYS_NS16550_COM3
	{ "ns16550_serial", &am33xx_serial[2] },
	{ "ns16550_serial", &am33xx_serial[3] },
	{ "ns16550_serial", &am33xx_serial[4] },
	{ "ns16550_serial", &am33xx_serial[5] },
#   endif
#  endif
};

#if CONFIG_IS_ENABLED(DM_I2C)
static const struct omap_i2c_plat am33xx_i2c[] = {
	{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
	{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
	{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
};

U_BOOT_DRVINFOS(am33xx_i2c) = {
	{ "i2c_omap", &am33xx_i2c[0] },
	{ "i2c_omap", &am33xx_i2c[1] },
	{ "i2c_omap", &am33xx_i2c[2] },
};
#endif

#if CONFIG_IS_ENABLED(DM_GPIO)
static const struct omap_gpio_plat am33xx_gpio[] = {
	{ 0, AM33XX_GPIO0_BASE },
	{ 1, AM33XX_GPIO1_BASE },
	{ 2, AM33XX_GPIO2_BASE },
	{ 3, AM33XX_GPIO3_BASE },
#ifdef CONFIG_AM43XX
	{ 4, AM33XX_GPIO4_BASE },
	{ 5, AM33XX_GPIO5_BASE },
#endif
};

U_BOOT_DRVINFOS(am33xx_gpios) = {
	{ "gpio_omap", &am33xx_gpio[0] },
	{ "gpio_omap", &am33xx_gpio[1] },
	{ "gpio_omap", &am33xx_gpio[2] },
	{ "gpio_omap", &am33xx_gpio[3] },
#ifdef CONFIG_AM43XX
	{ "gpio_omap", &am33xx_gpio[4] },
	{ "gpio_omap", &am33xx_gpio[5] },
#endif
};
#endif
#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct omap3_spi_plat omap3_spi_pdata = {
	.regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
	.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
};

U_BOOT_DRVINFO(am33xx_spi) = {
	.name = "omap3_spi",
	.plat = &omap3_spi_pdata,
};
#endif
#endif

#if !CONFIG_IS_ENABLED(DM_GPIO)
static const struct gpio_bank gpio_bank_am33xx[] = {
	{ (void *)AM33XX_GPIO0_BASE },
	{ (void *)AM33XX_GPIO1_BASE },
	{ (void *)AM33XX_GPIO2_BASE },
	{ (void *)AM33XX_GPIO3_BASE },
#ifdef CONFIG_AM43XX
	{ (void *)AM33XX_GPIO4_BASE },
	{ (void *)AM33XX_GPIO5_BASE },
#endif
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
#endif

#if defined(CONFIG_MMC_OMAP_HS)
int cpu_mmc_init(struct bd_info *bis)
{
	int ret;

	ret = omap_mmc_init(0, 0, 0, -1, -1);
	if (ret)
		return ret;

	return omap_mmc_init(1, 0, 0, -1, -1);
}
#endif

/*
 * RTC only with DDR in self-refresh mode magic value, checked against during
 * boot to see if we have a valid config. This should be in sync with the value
 * that will be in drivers/soc/ti/pm33xx.c.
 */
#define RTC_MAGIC_VAL		0x8cd0

/* Board type field bit shift for RTC only with DDR in self-refresh mode */
#define RTC_BOARD_TYPE_SHIFT	16

/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
	defined(CONFIG_SPL_BUILD)

static struct musb_hdrc_config musb_config = {
	.multipoint     = 1,
	.dyn_fifo       = 1,
	.num_eps        = 16,
	.ram_bits       = 12,
};

#ifdef CONFIG_AM335X_USB0
static struct ti_musb_plat usb0 = {
	.base = (void *)USB0_OTG_BASE,
	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
	.plat = {
		.config         = &musb_config,
		.power          = 50,
		.platform_ops	= &musb_dsps_ops,
		},
};
#endif

#ifdef CONFIG_AM335X_USB1
static struct ti_musb_plat usb1 = {
	.base = (void *)USB1_OTG_BASE,
	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
	.plat = {
		.config         = &musb_config,
		.power          = 50,
		.platform_ops	= &musb_dsps_ops,
		},
};
#endif

U_BOOT_DRVINFOS(am33xx_usbs) = {
#ifdef CONFIG_AM335X_USB0_PERIPHERAL
	{ "ti-musb-peripheral", &usb0 },
#elif defined(CONFIG_AM335X_USB0_HOST)
	{ "ti-musb-host", &usb0 },
#endif
#ifdef CONFIG_AM335X_USB1_PERIPHERAL
	{ "ti-musb-peripheral", &usb1 },
#elif defined(CONFIG_AM335X_USB1_HOST)
	{ "ti-musb-host", &usb1 },
#endif
};

int arch_misc_init(void)
{
	return 0;
}
#else	/* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */

int arch_misc_init(void)
{
	struct udevice *dev;
	int ret;

	ret = uclass_first_device_err(UCLASS_MISC, &dev);
	if (ret)
		return ret;

#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
	usb_ether_init();
#endif

	return 0;
}

#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */

#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)

#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
static void rtc32k_unlock(struct davinci_rtc *rtc)
{
	/*
	 * Unlock the RTC's registers.  For more details please see the
	 * RTC_SS section of the TRM.  In order to unlock we need to
	 * write these specific values (keys) in this order.
	 */
	writel(RTC_KICK0R_WE, &rtc->kick0r);
	writel(RTC_KICK1R_WE, &rtc->kick1r);
}
#endif

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
/*
 * Write contents of the RTC_SCRATCH1 register based on board type
 * Two things are passed
 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
 * control gets to kernel, kernel reads the scratchpad register and gets to
 * know that bootloader has rtc_only support.
 *
 * Second important thing is the board type  (16:31). This is needed in the
 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
 * identify the board type and we go ahead and copy the board strings to
 * am43xx_board_name.
 */
void update_rtc_magic(void)
{
	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
	u32 magic = RTC_MAGIC_VAL;

	magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);

	rtc32k_unlock(rtc);

	/* write magic */
	writel(magic, &rtc->scratch1);
}
#endif

/*
 * In the case of non-SPL based booting we'll want to call these
 * functions a tiny bit later as it will require gd to be set and cleared
 * and that's not true in s_init in this case so we cannot do it there.
 */
int board_early_init_f(void)
{
	set_mux_conf_regs();
	prcm_init();
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
	update_rtc_magic();
#endif
	return 0;
}

#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
static void rtc32k_enable(void)
{
	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;

	rtc32k_unlock(rtc);

	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
	writel((1 << 3) | (1 << 6), &rtc->osc);
}
#endif

static void uart_soft_reset(void)
{
	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
	u32 regval;

	regval = readl(&uart_base->uartsyscfg);
	regval |= UART_RESET;
	writel(regval, &uart_base->uartsyscfg);
	while ((readl(&uart_base->uartsyssts) &
		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
		;

	/* Disable smart idle */
	regval = readl(&uart_base->uartsyscfg);
	regval |= UART_SMART_IDLE_EN;
	writel(regval, &uart_base->uartsyscfg);
}

static void watchdog_disable(void)
{
	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;

	writel(0xAAAA, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;
	writel(0x5555, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;
}

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
/*
 * Check if we are executing rtc-only + DDR mode, and resume from it if needed
 */
static void rtc_only(void)
{
	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
	struct prm_device_inst *prm_device =
				(struct prm_device_inst *)PRM_DEVICE_INST;

	u32 scratch1, sdrc;
	void (*resume_func)(void);

	scratch1 = readl(&rtc->scratch1);

	/*
	 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
	 * written to this register when we want to wake up from RTC only
	 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
	 * bits 0-15:  RTC_MAGIC_VAL
	 * bits 16-31: board type (needed for sdram_init)
	 */
	if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
		return;

	rtc32k_unlock(rtc);

	/* Clear RTC magic */
	writel(0, &rtc->scratch1);

	/*
	 * Update board type based on value stored on RTC_SCRATCH1, this
	 * is done so that we don't need to read the board type from eeprom
	 * over i2c bus which is expensive
	 */
	rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);

	/*
	 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
	 * are resuming from self-refresh. This avoids an unnecessary re-init
	 * of the DDR. The re-init takes time and we would need to wait for
	 * it to complete before accessing DDR to avoid L3 NOC errors.
	 */
	writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);

	rtc_only_prcm_init();
	sdram_init();

	/* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
	/* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
	sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);

	sdrc &= AM43XX_SDRAM_TYPE_MASK;
	sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;

	if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
		writel(AM43XX_RDWRLVLFULL_START,
		       AM43XX_EMIF_BASE +
		       AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
		mdelay(1);

am43xx_wait:
		sdrc = readl(AM43XX_EMIF_BASE +
			     AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
		if (sdrc == AM43XX_RDWRLVLFULL_START)
			goto am43xx_wait;
	}

	resume_func = (void *)readl(&rtc->scratch0);
	if (resume_func)
		resume_func();
}
#endif

void s_init(void)
{
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
	rtc_only();
#endif
}

void early_system_init(void)
{
	/*
	 * The ROM will only have set up sufficient pinmux to allow for the
	 * first 4KiB NOR to be read, we must finish doing what we know of
	 * the NOR mux in this space in order to continue.
	 */
#ifdef CONFIG_NOR_BOOT
	enable_norboot_pin_mux();
#endif
	watchdog_disable();
	set_uart_mux_conf();
	setup_early_clocks();
	uart_soft_reset();
#ifdef CONFIG_SPL_BUILD
	/*
	 * Save the boot parameters passed from romcode.
	 * We cannot delay the saving further than this,
	 * to prevent overwrites.
	 */
	save_omap_boot_params();
#endif

#ifdef CONFIG_SPL_BUILD
	spl_early_init();
#endif

#ifdef CONFIG_TI_I2C_BOARD_DETECT
	do_board_detect();
#endif

#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
	/* Enable RTC32K clock */
	rtc32k_enable();
#endif
}

#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
	hw_data_init();
	early_system_init();
	board_early_init_f();
	sdram_init();
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size(
			(void *)CFG_SYS_SDRAM_BASE,
			CFG_MAX_RAM_BANK_SIZE);
}
#endif

#endif

static int am33xx_dm_post_init(void)
{
	hw_data_init();
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
	early_system_init();
#endif
	return 0;
}
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init);

#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
	if (u_boot_first_phase()) {
		hw_data_init();
		set_uart_mux_conf();
		setup_early_clocks();
		uart_soft_reset();

		/* avoid uart gibberish by allowing the clocks to settle */
		mdelay(50);
	}
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5289e83a CN	2	/*
	3	* board.c
	4	*
	5	* Common board functions for AM33XX based boards
	6	*
a94a4071	7	* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
5289e83a CN	8	*/
5289e83a CN	9
03de305e	10	#include <config.h>
d12010b0	11	#include <dm.h>
878d8856	12	#include <debug_uart.h>
973b6638	13	#include <errno.h>
7fe32b34	14	#include <event.h>
9b4a205f	15	#include <init.h>
90526e9f	16	#include <net.h>
4119e06d	17	#include <ns16550.h>
41cf3cb3	18	#include <omap3_spi.h>
47f7bcae	19	#include <spl.h>
5289e83a CN	20	#include <asm/arch/cpu.h>
5289e83a CN	21	#include <asm/arch/hardware.h>
8a8f084e	22	#include <asm/arch/omap.h>
5289e83a CN	23	#include <asm/arch/ddr_defs.h>
5289e83a CN	24	#include <asm/arch/clock.h>
3b97152b	25	#include <asm/arch/gpio.h>
0e6e67c6	26	#include <asm/arch/i2c.h>
050531db MC	27	#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
	28	#include <asm/arch/mem-guardian.h>
	29	#else
8eb16b7f	30	#include <asm/arch/mem.h>
050531db	31	#endif
8a8f084e	32	#include <asm/arch/mmc_host_def.h>
db7dd810	33	#include <asm/arch/sys_proto.h>
401d1c4f	34	#include <asm/global_data.h>
5289e83a	35	#include <asm/io.h>
fda35eb9	36	#include <asm/emif.h>
65d750be	37	#include <asm/gpio.h>
00bbe96e	38	#include <asm/omap_common.h>
973b6638 TR	39	#include <i2c.h>
	40	#include <miiphy.h>
	41	#include <cpsw.h>
c05ed00a	42	#include <linux/delay.h>
1221ce45	43	#include <linux/errno.h>
6a0d803c	44	#include <linux/compiler.h>
1e94b46f	45	#include <linux/printk.h>
7df5cf35 IY	46	#include <linux/usb/ch9.h>
	47	#include <linux/usb/gadget.h>
	48	#include <linux/usb/musb.h>
	49	#include <asm/omap_musb.h>
155d424a	50	#include <asm/davinci_rtc.h>
5289e83a	51
6fe3e5ba BG	52	#define AM43XX_EMIF_BASE 0x4C000000
	53	#define AM43XX_SDRAM_CONFIG_OFFSET 0x8
	54	#define AM43XX_SDRAM_TYPE_MASK 0xE0000000
	55	#define AM43XX_SDRAM_TYPE_SHIFT 29
	56	#define AM43XX_SDRAM_TYPE_DDR3 3
	57	#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
	58	#define AM43XX_RDWRLVLFULL_START 0x80000000
	59
41cf3cb3 FA	60	/* SPI flash. */
	61	#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
	62	#define AM33XX_SPI0_BASE 0x48030000
	63	#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
	64	#endif
	65
5289e83a CN	66	DECLARE_GLOBAL_DATA_PTR;
5289e83a CN	67
86277339 TR	68	int dram_init(void)
86277339 TR	69	{
a2ac2b96	70	#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
86277339 TR	71	sdram_init();
	72	#endif
	73
	74	/* dram_init must store complete ramsize in gd->ram_size */
	75	gd->ram_size = get_ram_size(
aa6e94de	76	(void *)CFG_SYS_SDRAM_BASE,
8a897c4f	77	CFG_MAX_RAM_BANK_SIZE);
86277339 TR	78	return 0;
	79	}
	80
	81	int dram_init_banksize(void)
	82	{
aa6e94de	83	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
86277339 TR	84	gd->bd->bi_dram[0].size = gd->ram_size;
	85
	86	return 0;
	87	}
	88
75507d5d	89	#if !CONFIG_IS_ENABLED(OF_CONTROL)
8a8d24bd	90	static const struct ns16550_plat am33xx_serial[] = {
91092132 TR	91	{ .base = CFG_SYS_NS16550_COM1, .reg_shift = 2,
	92	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	93	# ifdef CFG_SYS_NS16550_COM2
	94	{ .base = CFG_SYS_NS16550_COM2, .reg_shift = 2,
	95	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	96	# ifdef CFG_SYS_NS16550_COM3
	97	{ .base = CFG_SYS_NS16550_COM3, .reg_shift = 2,
	98	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	99	{ .base = CFG_SYS_NS16550_COM4, .reg_shift = 2,
	100	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	101	{ .base = CFG_SYS_NS16550_COM5, .reg_shift = 2,
	102	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	103	{ .base = CFG_SYS_NS16550_COM6, .reg_shift = 2,
	104	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
4119e06d	105	# endif
1480fdf8	106	# endif
4119e06d SG	107	};
4119e06d SG	108
20e442ab	109	U_BOOT_DRVINFOS(am33xx_uarts) = {
75507d5d	110	{ "ns16550_serial", &am33xx_serial[0] },
91092132	111	# ifdef CFG_SYS_NS16550_COM2
75507d5d	112	{ "ns16550_serial", &am33xx_serial[1] },
91092132	113	# ifdef CFG_SYS_NS16550_COM3
75507d5d TR	114	{ "ns16550_serial", &am33xx_serial[2] },
	115	{ "ns16550_serial", &am33xx_serial[3] },
	116	{ "ns16550_serial", &am33xx_serial[4] },
	117	{ "ns16550_serial", &am33xx_serial[5] },
4119e06d SG	118	# endif
	119	# endif
	120	};
90345c92	121
2147a169	122	#if CONFIG_IS_ENABLED(DM_I2C)
8a8d24bd	123	static const struct omap_i2c_plat am33xx_i2c[] = {
0e6e67c6 JJH	124	{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
	125	{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
	126	{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
	127	};
	128
20e442ab	129	U_BOOT_DRVINFOS(am33xx_i2c) = {
0e6e67c6 JJH	130	{ "i2c_omap", &am33xx_i2c[0] },
	131	{ "i2c_omap", &am33xx_i2c[1] },
	132	{ "i2c_omap", &am33xx_i2c[2] },
	133	};
	134	#endif
	135
bcee8d67	136	#if CONFIG_IS_ENABLED(DM_GPIO)
8a8d24bd	137	static const struct omap_gpio_plat am33xx_gpio[] = {
90345c92 TR	138	{ 0, AM33XX_GPIO0_BASE },
	139	{ 1, AM33XX_GPIO1_BASE },
	140	{ 2, AM33XX_GPIO2_BASE },
	141	{ 3, AM33XX_GPIO3_BASE },
	142	#ifdef CONFIG_AM43XX
	143	{ 4, AM33XX_GPIO4_BASE },
	144	{ 5, AM33XX_GPIO5_BASE },
1480fdf8	145	#endif
90345c92	146	};
4119e06d	147
20e442ab	148	U_BOOT_DRVINFOS(am33xx_gpios) = {
90345c92 TR	149	{ "gpio_omap", &am33xx_gpio[0] },
	150	{ "gpio_omap", &am33xx_gpio[1] },
	151	{ "gpio_omap", &am33xx_gpio[2] },
	152	{ "gpio_omap", &am33xx_gpio[3] },
	153	#ifdef CONFIG_AM43XX
	154	{ "gpio_omap", &am33xx_gpio[4] },
	155	{ "gpio_omap", &am33xx_gpio[5] },
	156	#endif
	157	};
	158	#endif
41cf3cb3 FA	159	#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
	160	static const struct omap3_spi_plat omap3_spi_pdata = {
	161	.regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
	162	.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
	163	};
	164
20e442ab	165	U_BOOT_DRVINFO(am33xx_spi) = {
41cf3cb3	166	.name = "omap3_spi",
caa4daa2	167	.plat = &omap3_spi_pdata,
41cf3cb3 FA	168	};
41cf3cb3 FA	169	#endif
90345c92	170	#endif
d12010b0	171
bcee8d67	172	#if !CONFIG_IS_ENABLED(DM_GPIO)
cd8341b7	173	static const struct gpio_bank gpio_bank_am33xx[] = {
0a9e3405 TR	174	{ (void *)AM33XX_GPIO0_BASE },
	175	{ (void *)AM33XX_GPIO1_BASE },
	176	{ (void *)AM33XX_GPIO2_BASE },
	177	{ (void *)AM33XX_GPIO3_BASE },
cd8341b7	178	#ifdef CONFIG_AM43XX
0a9e3405 TR	179	{ (void *)AM33XX_GPIO4_BASE },
0a9e3405 TR	180	{ (void *)AM33XX_GPIO5_BASE },
cd8341b7	181	#endif
3b97152b SS	182	};
	183
	184	const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
d12010b0 SG	185	#endif
d12010b0 SG	186
d5abcf94	187	#if defined(CONFIG_MMC_OMAP_HS)
b75d8dc5	188	int cpu_mmc_init(struct bd_info *bis)
876bdd6d	189	{
0689a2ef	190	int ret;
75a23880	191
e3913f56	192	ret = omap_mmc_init(0, 0, 0, -1, -1);
0689a2ef TR	193	if (ret)
	194	return ret;
	195
e3913f56	196	return omap_mmc_init(1, 0, 0, -1, -1);
876bdd6d CN	197	}
876bdd6d CN	198	#endif
8a8f084e	199
7619badb TK	200	/*
	201	* RTC only with DDR in self-refresh mode magic value, checked against during
	202	* boot to see if we have a valid config. This should be in sync with the value
	203	* that will be in drivers/soc/ti/pm33xx.c.
	204	*/
	205	#define RTC_MAGIC_VAL 0x8cd0
	206
	207	/* Board type field bit shift for RTC only with DDR in self-refresh mode */
	208	#define RTC_BOARD_TYPE_SHIFT 16
	209
7df5cf35	210	/* AM33XX has two MUSB controllers which can be host or gadget */
6815a66a TR	211	#if (defined(CONFIG_AM335X_USB0) \|\| defined(CONFIG_AM335X_USB1)) && \
6815a66a TR	212	defined(CONFIG_SPL_BUILD)
7a43dd7a JJH	213
	214	static struct musb_hdrc_config musb_config = {
	215	.multipoint = 1,
	216	.dyn_fifo = 1,
	217	.num_eps = 16,
	218	.ram_bits = 12,
	219	};
	220
6815a66a	221	#ifdef CONFIG_AM335X_USB0
8a8d24bd	222	static struct ti_musb_plat usb0 = {
7a43dd7a JJH	223	.base = (void *)USB0_OTG_BASE,
	224	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
	225	.plat = {
	226	.config = &musb_config,
	227	.power = 50,
	228	.platform_ops = &musb_dsps_ops,
	229	},
	230	};
6815a66a	231	#endif
7a43dd7a	232
6815a66a	233	#ifdef CONFIG_AM335X_USB1
8a8d24bd	234	static struct ti_musb_plat usb1 = {
7a43dd7a JJH	235	.base = (void *)USB1_OTG_BASE,
	236	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
	237	.plat = {
	238	.config = &musb_config,
	239	.power = 50,
	240	.platform_ops = &musb_dsps_ops,
	241	},
	242	};
6815a66a	243	#endif
7a43dd7a	244
20e442ab	245	U_BOOT_DRVINFOS(am33xx_usbs) = {
ae3f467e	246	#ifdef CONFIG_AM335X_USB0_PERIPHERAL
7a43dd7a	247	{ "ti-musb-peripheral", &usb0 },
ae3f467e	248	#elif defined(CONFIG_AM335X_USB0_HOST)
7a43dd7a JJH	249	{ "ti-musb-host", &usb0 },
7a43dd7a JJH	250	#endif
ae3f467e	251	#ifdef CONFIG_AM335X_USB1_PERIPHERAL
7a43dd7a	252	{ "ti-musb-peripheral", &usb1 },
ae3f467e	253	#elif defined(CONFIG_AM335X_USB1_HOST)
7a43dd7a JJH	254	{ "ti-musb-host", &usb1 },
	255	#endif
	256	};
	257
	258	int arch_misc_init(void)
	259	{
	260	return 0;
	261	}
409a81dd AG	262	#else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
	263
	264	int arch_misc_init(void)
	265	{
3aec2648 M	266	struct udevice *dev;
	267	int ret;
	268
c726fc01 MS	269	ret = uclass_first_device_err(UCLASS_MISC, &dev);
c726fc01 MS	270	if (ret)
3aec2648	271	return ret;
ba7916c7 M	272
ba7916c7 M	273	#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
dc38fe2c	274	usb_ether_init();
ba7916c7	275	#endif
409a81dd	276
7df5cf35 IY	277	return 0;
7df5cf35 IY	278	}
49f78365	279
409a81dd AG	280	#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
409a81dd AG	281
a2ac2b96	282	#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
7619badb TK	283
	284	#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) \|\| \
	285	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
	286	static void rtc32k_unlock(struct davinci_rtc *rtc)
	287	{
	288	/*
	289	* Unlock the RTC's registers. For more details please see the
	290	* RTC_SS section of the TRM. In order to unlock we need to
	291	* write these specific values (keys) in this order.
	292	*/
	293	writel(RTC_KICK0R_WE, &rtc->kick0r);
	294	writel(RTC_KICK1R_WE, &rtc->kick1r);
	295	}
	296	#endif
	297
	298	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
	299	/*
	300	* Write contents of the RTC_SCRATCH1 register based on board type
	301	* Two things are passed
	302	* on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
	303	* control gets to kernel, kernel reads the scratchpad register and gets to
	304	* know that bootloader has rtc_only support.
	305	*
	306	* Second important thing is the board type (16:31). This is needed in the
	307	* rtc_only boot where in we want to avoid costly i2c reads to eeprom to
	308	* identify the board type and we go ahead and copy the board strings to
	309	* am43xx_board_name.
	310	*/
	311	void update_rtc_magic(void)
	312	{
	313	struct davinci_rtc rtc = (struct davinci_rtc )RTC_BASE;
	314	u32 magic = RTC_MAGIC_VAL;
	315
	316	magic \|= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
	317
	318	rtc32k_unlock(rtc);
	319
	320	/* write magic */
	321	writel(magic, &rtc->scratch1);
	322	}
	323	#endif
	324
196311dc TR	325	/*
	326	* In the case of non-SPL based booting we'll want to call these
	327	* functions a tiny bit later as it will require gd to be set and cleared
	328	* and that's not true in s_init in this case so we cannot do it there.
	329	*/
	330	int board_early_init_f(void)
	331	{
196311dc	332	set_mux_conf_regs();
b2a2bf41	333	prcm_init();
7619badb TK	334	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
	335	update_rtc_magic();
	336	#endif
196311dc TR	337	return 0;
	338	}
	339
16678eb4	340	#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
0660481a	341	static void rtc32k_enable(void)
49f78365	342	{
155d424a	343	struct davinci_rtc rtc = (struct davinci_rtc )RTC_BASE;
49f78365	344
7619badb	345	rtc32k_unlock(rtc);
49f78365 HS	346
	347	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
	348	writel((1 << 3) \| (1 << 6), &rtc->osc);
	349	}
16678eb4	350	#endif
7ea7f689	351
0660481a	352	static void uart_soft_reset(void)
7ea7f689 HS	353	{
	354	struct uart_sys uart_base = (struct uart_sys )DEFAULT_UART_BASE;
	355	u32 regval;
	356
	357	regval = readl(&uart_base->uartsyscfg);
	358	regval \|= UART_RESET;
	359	writel(regval, &uart_base->uartsyscfg);
	360	while ((readl(&uart_base->uartsyssts) &
	361	UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
	362	;
	363
	364	/* Disable smart idle */
	365	regval = readl(&uart_base->uartsyscfg);
	366	regval \|= UART_SMART_IDLE_EN;
	367	writel(regval, &uart_base->uartsyscfg);
	368	}
0660481a HS	369
	370	static void watchdog_disable(void)
	371	{
	372	struct wd_timer wdtimer = (struct wd_timer )WDT_BASE;
	373
	374	writel(0xAAAA, &wdtimer->wdtwspr);
	375	while (readl(&wdtimer->wdtwwps) != 0x0)
	376	;
	377	writel(0x5555, &wdtimer->wdtwspr);
	378	while (readl(&wdtimer->wdtwwps) != 0x0)
	379	;
	380	}
0660481a	381
7619badb TK	382	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
	383	/*
	384	* Check if we are executing rtc-only + DDR mode, and resume from it if needed
	385	*/
	386	static void rtc_only(void)
	387	{
	388	struct davinci_rtc rtc = (struct davinci_rtc )RTC_BASE;
025a0d40 RD	389	struct prm_device_inst *prm_device =
	390	(struct prm_device_inst *)PRM_DEVICE_INST;
	391
6fe3e5ba	392	u32 scratch1, sdrc;
7619badb TK	393	void (*resume_func)(void);
	394
	395	scratch1 = readl(&rtc->scratch1);
	396
	397	/*
	398	* Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
	399	* written to this register when we want to wake up from RTC only
	400	* with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
	401	* bits 0-15: RTC_MAGIC_VAL
	402	* bits 16-31: board type (needed for sdram_init)
	403	*/
	404	if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
	405	return;
	406
	407	rtc32k_unlock(rtc);
	408
	409	/* Clear RTC magic */
	410	writel(0, &rtc->scratch1);
	411
	412	/*
	413	* Update board type based on value stored on RTC_SCRATCH1, this
	414	* is done so that we don't need to read the board type from eeprom
	415	* over i2c bus which is expensive
	416	*/
	417	rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
	418
025a0d40 RD	419	/*
	420	* Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
	421	* are resuming from self-refresh. This avoids an unnecessary re-init
	422	* of the DDR. The re-init takes time and we would need to wait for
	423	* it to complete before accessing DDR to avoid L3 NOC errors.
	424	*/
	425	writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
	426
7619badb TK	427	rtc_only_prcm_init();
	428	sdram_init();
	429
6fe3e5ba BG	430	/* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
	431	/* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
	432	sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
	433
	434	sdrc &= AM43XX_SDRAM_TYPE_MASK;
	435	sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
	436
	437	if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
	438	writel(AM43XX_RDWRLVLFULL_START,
	439	AM43XX_EMIF_BASE +
	440	AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
	441	mdelay(1);
	442
	443	am43xx_wait:
	444	sdrc = readl(AM43XX_EMIF_BASE +
	445	AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
	446	if (sdrc == AM43XX_RDWRLVLFULL_START)
	447	goto am43xx_wait;
	448	}
	449
7619badb TK	450	resume_func = (void *)readl(&rtc->scratch0);
	451	if (resume_func)
	452	resume_func();
	453	}
	454	#endif
	455
c704a99d	456	void s_init(void)
7ae8350f	457	{
7619badb TK	458	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
	459	rtc_only();
	460	#endif
7ae8350f	461	}
7ae8350f	462
c704a99d	463	void early_system_init(void)
0660481a HS	464	{
	465	/*
	466	* The ROM will only have set up sufficient pinmux to allow for the
	467	* first 4KiB NOR to be read, we must finish doing what we know of
	468	* the NOR mux in this space in order to continue.
	469	*/
	470	#ifdef CONFIG_NOR_BOOT
	471	enable_norboot_pin_mux();
0660481a	472	#endif
0660481a	473	watchdog_disable();
0660481a	474	set_uart_mux_conf();
b64a7cb9	475	setup_early_clocks();
0660481a	476	uart_soft_reset();
4bd754d8 LV	477	#ifdef CONFIG_SPL_BUILD
	478	/*
	479	* Save the boot parameters passed from romcode.
	480	* We cannot delay the saving further than this,
	481	* to prevent overwrites.
	482	*/
	483	save_omap_boot_params();
	484	#endif
2b30b38b	485
b442e16b FA	486	#ifdef CONFIG_SPL_BUILD
	487	spl_early_init();
	488	#endif
2b30b38b JJH	489
	490	#ifdef CONFIG_TI_I2C_BOARD_DETECT
	491	do_board_detect();
	492	#endif
	493
16678eb4	494	#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
0660481a HS	495	/* Enable RTC32K clock */
0660481a HS	496	rtc32k_enable();
16678eb4	497	#endif
0660481a	498	}
c704a99d LV	499
	500	#ifdef CONFIG_SPL_BUILD
	501	void board_init_f(ulong dummy)
	502	{
00bbe96e	503	hw_data_init();
c704a99d LV	504	early_system_init();
	505	board_early_init_f();
	506	sdram_init();
86282798 LV	507	/* dram_init must store complete ramsize in gd->ram_size */
86282798 LV	508	gd->ram_size = get_ram_size(
aa6e94de	509	(void *)CFG_SYS_SDRAM_BASE,
8a897c4f	510	CFG_MAX_RAM_BANK_SIZE);
c704a99d	511	}
d73f38f7	512	#endif
c704a99d LV	513
	514	#endif
	515
f72d0d4a	516	static int am33xx_dm_post_init(void)
c704a99d	517	{
00bbe96e	518	hw_data_init();
a2ac2b96	519	#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
c704a99d LV	520	early_system_init();
	521	#endif
	522	return 0;
	523	}
f72d0d4a	524	EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
0fd4120f SG	525
	526	#ifdef CONFIG_DEBUG_UART_BOARD_INIT
	527	void board_debug_uart_init(void)
	528	{
	529	if (u_boot_first_phase()) {
	530	hw_data_init();
	531	set_uart_mux_conf();
	532	setup_early_clocks();
	533	uart_soft_reset();
	534
	535	/* avoid uart gibberish by allowing the clocks to settle */
	536	mdelay(50);
	537	}
	538	}
	539	#endif