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driver: clk: tegra: init basic clocks on probe
[J-u-boot.git] / drivers / mmc / mmc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 2/*
3 * Copyright 2008, Freescale Semiconductor, Inc
39913ace 4 * Copyright 2020 NXP
272cc70b
AF		 5 * Andy Fleming
6 *
7 * Based vaguely on the Linux code
272cc70b
AF		 8 */
9
10#include <config.h>
e6f6f9e6 11#include <blk.h>
272cc70b 12#include <command.h>
8e3332e2 13#include <dm.h>
f7ae49fc 14#include <log.h>
8e3332e2 15#include <dm/device-internal.h>
d4622df3 16#include <errno.h>
272cc70b
AF		 17#include <mmc.h>
18#include <part.h>
03de305e 19#include <time.h>
cd93d625 20#include <linux/bitops.h>
c05ed00a 21#include <linux/delay.h>
1e94b46f 22#include <linux/printk.h>
2051aefe 23#include <power/regulator.h>
272cc70b 24#include <malloc.h>
cf92e05c 25#include <memalign.h>
272cc70b 26#include <linux/list.h>
03de305e 27#include <linux/printk.h>
9b1f942c 28#include <div64.h>
da61fa5f 29#include "mmc_private.h"
272cc70b 30
39320c53
JJH		 31#define DEFAULT_CMD6_TIMEOUT_MS 500
32
150481e5
TH		 33/**
34 * names of emmc BOOT_PARTITION_ENABLE values
35 *
36 * Boot Area Partitions - name consistent with Linux
37 */
38const char *emmc_boot_part_names[] = {
39 "default", /* EMMC_BOOT_PART_DEFAULT */
40 "boot0", /* EMMC_BOOT_PART_BOOT1 */
41 "boot1", /* EMMC_BOOT_PART_BOOT2 */
42 "",
43 "",
44 "",
45 "",
46 "user", /* EMMC_BOOT_PART_USER */
47};
48
49/**
50 * names of emmc 'hardware partitions' consistent with:
51 * - value used in mmc_switch()
52 * - value used by PARTITION_CONFIG PARTITION_ACCESS field
53 *
54 * Boot Area Partitions - name consistent with Linux
55 * General Perpose Partitions - name consistent with 'mmc hwpartition' usage
56 */
57const char *emmc_hwpart_names[] = {
58 "user", /* EMMC_HWPART_DEFAULT */
59 "boot0", /* EMMC_HWPART_BOOT1 */
60 "boot1", /* EMMC_HWPART_BOOT2 */
61 "rpmb", /* EMMC_HWPART_RPMB */
62 "gp1", /* EMMC_HWPART_GP1 */
63 "gp2", /* EMMC_HWPART_GP2 */
64 "gp3", /* EMMC_HWPART_GP3 */
65 "gp4", /* EMMC_HWPART_GP4 */
66};
67
aff5d3c8 68static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
b5b838f1 69
e7881d85 70#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6 71
6cf8a903 72static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
c10b85d6 73{
d6ad5a0a
LP		 74 if (mmc->cfg->ops->wait_dat0)
75 return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us);
76
c10b85d6
JJH		 77 return -ENOSYS;
78}
79
750121c3 80__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 81{
82 return -1;
83}
84
85int mmc_getwp(struct mmc *mmc)
86{
87 int wp;
88
89 wp = board_mmc_getwp(mmc);
90
d4e1da4e 91 if (wp < 0) {
93bfd616
PA		 92 if (mmc->cfg->ops->getwp)
93 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 94 else
95 wp = 0;
96 }
d23d8d7e
NK		 97
98 return wp;
99}
100
cee9ab7c
JH		 101__weak int board_mmc_getcd(struct mmc *mmc)
102{
11fdade2
SB		 103 return -1;
104}
8ca51e51 105#endif
11fdade2 106
c0c76eba
SG		 107#ifdef CONFIG_MMC_TRACE
108void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 109{
c0c76eba 110 printf("CMD_SEND:%d\n", cmd->cmdidx);
7d5ccb1a 111 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
c0c76eba 112}
8635ff9e 113
c0c76eba
SG		 114void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
115{
5db2fe3a
RR		 116 int i;
117 u8 *ptr;
118
7863ce58
BM		 119 if (ret) {
120 printf("\t\tRET\t\t\t %d\n", ret);
121 } else {
122 switch (cmd->resp_type) {
123 case MMC_RSP_NONE:
124 printf("\t\tMMC_RSP_NONE\n");
125 break;
126 case MMC_RSP_R1:
7d5ccb1a 127 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
7863ce58
BM		 128 cmd->response[0]);
129 break;
130 case MMC_RSP_R1b:
7d5ccb1a 131 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
7863ce58
BM		 132 cmd->response[0]);
133 break;
134 case MMC_RSP_R2:
7d5ccb1a 135 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
7863ce58 136 cmd->response[0]);
7d5ccb1a 137 printf("\t\t \t\t 0x%08x \n",
7863ce58 138 cmd->response[1]);
7d5ccb1a 139 printf("\t\t \t\t 0x%08x \n",
7863ce58 140 cmd->response[2]);
7d5ccb1a 141 printf("\t\t \t\t 0x%08x \n",
7863ce58 142 cmd->response[3]);
5db2fe3a 143 printf("\n");
7863ce58
BM		 144 printf("\t\t\t\t\tDUMPING DATA\n");
145 for (i = 0; i < 4; i++) {
146 int j;
147 printf("\t\t\t\t\t%03d - ", i*4);
148 ptr = (u8 *)&cmd->response[i];
149 ptr += 3;
150 for (j = 0; j < 4; j++)
7d5ccb1a 151 printf("%02x ", *ptr--);
7863ce58
BM		 152 printf("\n");
153 }
154 break;
155 case MMC_RSP_R3:
7d5ccb1a 156 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
7863ce58
BM		 157 cmd->response[0]);
158 break;
159 default:
160 printf("\t\tERROR MMC rsp not supported\n");
161 break;
53e8e40b 162 }
5db2fe3a 163 }
c0c76eba
SG		 164}
165
166void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
167{
168 int status;
169
170 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
171 printf("CURR STATE:%d\n", status);
172}
5db2fe3a 173#endif
c0c76eba 174
48467e47 175#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG
35f9e196
JJH		 176const char *mmc_mode_name(enum bus_mode mode)
177{
178 static const char *const names[] = {
179 [MMC_LEGACY] = "MMC legacy",
35f9e196
JJH		 180 [MMC_HS] = "MMC High Speed (26MHz)",
181 [SD_HS] = "SD High Speed (50MHz)",
182 [UHS_SDR12] = "UHS SDR12 (25MHz)",
183 [UHS_SDR25] = "UHS SDR25 (50MHz)",
184 [UHS_SDR50] = "UHS SDR50 (100MHz)",
185 [UHS_SDR104] = "UHS SDR104 (208MHz)",
186 [UHS_DDR50] = "UHS DDR50 (50MHz)",
187 [MMC_HS_52] = "MMC High Speed (52MHz)",
188 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
189 [MMC_HS_200] = "HS200 (200MHz)",
3dd2626f 190 [MMC_HS_400] = "HS400 (200MHz)",
44acd492 191 [MMC_HS_400_ES] = "HS400ES (200MHz)",
35f9e196
JJH		 192 };
193
194 if (mode >= MMC_MODES_END)
195 return "Unknown mode";
196 else
197 return names[mode];
198}
199#endif
200
05038576
JJH		 201static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
202{
203 static const int freqs[] = {
1b313aa3 204 [MMC_LEGACY] = 25000000,
05038576
JJH		 205 [MMC_HS] = 26000000,
206 [SD_HS] = 50000000,
1b313aa3
JC		 207 [MMC_HS_52] = 52000000,
208 [MMC_DDR_52] = 52000000,
05038576
JJH		 209 [UHS_SDR12] = 25000000,
210 [UHS_SDR25] = 50000000,
211 [UHS_SDR50] = 100000000,
05038576 212 [UHS_DDR50] = 50000000,
f99c2efe 213 [UHS_SDR104] = 208000000,
05038576 214 [MMC_HS_200] = 200000000,
3dd2626f 215 [MMC_HS_400] = 200000000,
44acd492 216 [MMC_HS_400_ES] = 200000000,
05038576
JJH		 217 };
218
219 if (mode == MMC_LEGACY)
220 return mmc->legacy_speed;
221 else if (mode >= MMC_MODES_END)
222 return 0;
223 else
224 return freqs[mode];
225}
226
35f9e196
JJH		 227static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
228{
229 mmc->selected_mode = mode;
05038576 230 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 231 mmc->ddr_mode = mmc_is_mode_ddr(mode);
d4d64889
MY		 232 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
233 mmc->tran_speed / 1000000);
35f9e196
JJH		 234 return 0;
235}
236
e7881d85 237#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 238int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
239{
240 int ret;
241
242 mmmc_trace_before_send(mmc, cmd);
243 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
244 mmmc_trace_after_send(mmc, cmd, ret);
245
8635ff9e 246 return ret;
272cc70b 247}
8ca51e51 248#endif
272cc70b 249
da129170
SA		 250/**
251 * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error
252 *
253 * @dev: device to receive the command
254 * @cmd: command to send
255 * @data: additional data to send/receive
256 * @retries: how many times to retry; mmc_send_cmd is always called at least
257 * once
185f812c 258 * Return: 0 if ok, -ve on error
da129170
SA		 259 */
260static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd,
261 struct mmc_data *data, uint retries)
262{
263 int ret;
264
265 do {
266 ret = mmc_send_cmd(mmc, cmd, data);
267 } while (ret && retries--);
268
269 return ret;
270}
271
272/**
273 * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a
274 * specific quirk is enabled
275 *
276 * @dev: device to receive the command
277 * @cmd: command to send
278 * @data: additional data to send/receive
279 * @quirk: retry only if this quirk is enabled
280 * @retries: how many times to retry; mmc_send_cmd is always called at least
281 * once
185f812c 282 * Return: 0 if ok, -ve on error
da129170
SA		 283 */
284static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd,
285 struct mmc_data *data, u32 quirk, uint retries)
286{
497b7c6b 287 if (IS_ENABLED(CONFIG_MMC_QUIRKS) && mmc->quirks & quirk)
da129170
SA		 288 return mmc_send_cmd_retry(mmc, cmd, data, retries);
289 else
290 return mmc_send_cmd(mmc, cmd, data);
291}
292
863d1004 293int mmc_send_status(struct mmc *mmc, unsigned int *status)
5d4fc8d9
RR		 294{
295 struct mmc_cmd cmd;
da129170 296 int ret;
5d4fc8d9
RR		 297
298 cmd.cmdidx = MMC_CMD_SEND_STATUS;
299 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 300 if (!mmc_host_is_spi(mmc))
301 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 302
da129170 303 ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4);
863d1004 304 mmc_trace_state(mmc, &cmd);
da129170
SA		 305 if (!ret)
306 *status = cmd.response[0];
307
308 return ret;
863d1004
JJH		 309}
310
6cf8a903 311int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
863d1004
JJH		 312{
313 unsigned int status;
314 int err;
d0c221fe 315
6cf8a903 316 err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
cd0b80ec
JJH		 317 if (err != -ENOSYS)
318 return err;
319
863d1004
JJH		 320 while (1) {
321 err = mmc_send_status(mmc, &status);
322 if (err)
323 return err;
324
325 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
326 (status & MMC_STATUS_CURR_STATE) !=
327 MMC_STATE_PRG)
328 break;
329
330 if (status & MMC_STATUS_MASK) {
371dc068 331#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
99b23d45 332 log_err("Status Error: %#08x\n", status);
56196826 333#endif
863d1004
JJH		 334 return -ECOMM;
335 }
5d4fc8d9 336
6cf8a903 337 if (timeout_ms-- <= 0)
1677eef4 338 break;
5d4fc8d9 339
1677eef4
AG		 340 udelay(1000);
341 }
5d4fc8d9 342
6cf8a903 343 if (timeout_ms <= 0) {
371dc068 344#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
99b23d45 345 log_err("Timeout waiting card ready\n");
56196826 346#endif
915ffa52 347 return -ETIMEDOUT;
5d4fc8d9
RR		 348 }
349
350 return 0;
351}
352
da61fa5f 353int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 354{
355 struct mmc_cmd cmd;
356
786e8f81 357 if (mmc->ddr_mode)
d22e3d46
JC		 358 return 0;
359
272cc70b
AF		 360 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
361 cmd.resp_type = MMC_RSP_R1;
362 cmd.cmdarg = len;
272cc70b 363
da129170
SA		 364 return mmc_send_cmd_quirks(mmc, &cmd, NULL,
365 MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
272cc70b
AF		 366}
367
03de305e 368#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
9815e3ba
JJH		 369static const u8 tuning_blk_pattern_4bit[] = {
370 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
371 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
372 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
373 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
374 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
375 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
376 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
377 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
378};
379
380static const u8 tuning_blk_pattern_8bit[] = {
381 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
382 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
383 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
384 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
385 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
386 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
387 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
388 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
389 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
390 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
391 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
392 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
393 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
394 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
395 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
396 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
397};
398
a3b27866 399int mmc_send_tuning(struct mmc *mmc, u32 opcode)
9815e3ba
JJH		 400{
401 struct mmc_cmd cmd;
402 struct mmc_data data;
403 const u8 *tuning_block_pattern;
404 int size, err;
405
406 if (mmc->bus_width == 8) {
407 tuning_block_pattern = tuning_blk_pattern_8bit;
408 size = sizeof(tuning_blk_pattern_8bit);
409 } else if (mmc->bus_width == 4) {
410 tuning_block_pattern = tuning_blk_pattern_4bit;
411 size = sizeof(tuning_blk_pattern_4bit);
412 } else {
413 return -EINVAL;
414 }
415
416 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
417
418 cmd.cmdidx = opcode;
419 cmd.cmdarg = 0;
420 cmd.resp_type = MMC_RSP_R1;
421
422 data.dest = (void *)data_buf;
423 data.blocks = 1;
424 data.blocksize = size;
425 data.flags = MMC_DATA_READ;
426
427 err = mmc_send_cmd(mmc, &cmd, &data);
428 if (err)
429 return err;
430
431 if (memcmp(data_buf, tuning_block_pattern, size))
432 return -EIO;
433
434 return 0;
435}
f99c2efe 436#endif
9815e3ba 437
0ac2cca3
HP		 438int mmc_send_stop_transmission(struct mmc *mmc, bool write)
439{
440 struct mmc_cmd cmd;
441
442 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
443 cmd.cmdarg = 0;
444 /*
445 * JEDEC Standard No. 84-B51 Page 126
446 * CMD12 STOP_TRANSMISSION R1/R1b[3]
447 * NOTE 3 R1 for read cases and R1b for write cases.
448 *
449 * Physical Layer Simplified Specification Version 9.00
450 * 7.3.1.3 Detailed Command Description
451 * CMD12 R1b
452 */
453 cmd.resp_type = (IS_SD(mmc) || write) ? MMC_RSP_R1b : MMC_RSP_R1;
454
455 return mmc_send_cmd(mmc, &cmd, NULL);
456}
457
ff8fef56 458static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 459 lbaint_t blkcnt)
272cc70b
AF		 460{
461 struct mmc_cmd cmd;
462 struct mmc_data data;
463
4a1a06bc
AS		 464 if (blkcnt > 1)
465 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
466 else
467 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 468
469 if (mmc->high_capacity)
4a1a06bc 470 cmd.cmdarg = start;
272cc70b 471 else
4a1a06bc 472 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 473
474 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 475
476 data.dest = dst;
4a1a06bc 477 data.blocks = blkcnt;
272cc70b
AF		 478 data.blocksize = mmc->read_bl_len;
479 data.flags = MMC_DATA_READ;
480
4a1a06bc
AS		 481 if (mmc_send_cmd(mmc, &cmd, &data))
482 return 0;
272cc70b 483
4a1a06bc 484 if (blkcnt > 1) {
0ac2cca3 485 if (mmc_send_stop_transmission(mmc, false)) {
371dc068 486#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
99b23d45 487 log_err("mmc fail to send stop cmd\n");
56196826 488#endif
4a1a06bc
AS		 489 return 0;
490 }
272cc70b
AF		 491 }
492
4a1a06bc 493 return blkcnt;
272cc70b
AF		 494}
495
145429aa
MV		 496#if !CONFIG_IS_ENABLED(DM_MMC)
497static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
498{
499 if (mmc->cfg->ops->get_b_max)
500 return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
501 else
502 return mmc->cfg->b_max;
503}
504#endif
505
c4d660d4 506#if CONFIG_IS_ENABLED(BLK)
7dba0b93 507ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 508#else
7dba0b93
SG		 509ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
510 void *dst)
33fb211d 511#endif
272cc70b 512{
c4d660d4 513#if CONFIG_IS_ENABLED(BLK)
caa4daa2 514 struct blk_desc *block_dev = dev_get_uclass_plat(dev);
33fb211d 515#endif
bcce53d0 516 int dev_num = block_dev->devnum;
873cc1d7 517 int err;
4a1a06bc 518 lbaint_t cur, blocks_todo = blkcnt;
145429aa 519 uint b_max;
4a1a06bc
AS		 520
521 if (blkcnt == 0)
522 return 0;
272cc70b 523
4a1a06bc 524 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 525 if (!mmc)
526 return 0;
527
b5b838f1
MV		 528 if (CONFIG_IS_ENABLED(MMC_TINY))
529 err = mmc_switch_part(mmc, block_dev->hwpart);
530 else
531 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
532
873cc1d7
SW		 533 if (err < 0)
534 return 0;
535
c40fdca6 536 if ((start + blkcnt) > block_dev->lba) {
371dc068 537#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
99b23d45
SG		 538 log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
539 start + blkcnt, block_dev->lba);
56196826 540#endif
d2bf29e3
LW		 541 return 0;
542 }
272cc70b 543
11692991 544 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
d4d64889 545 pr_debug("%s: Failed to set blocklen\n", __func__);
272cc70b 546 return 0;
11692991 547 }
272cc70b 548
145429aa
MV		 549 b_max = mmc_get_b_max(mmc, dst, blkcnt);
550
4a1a06bc 551 do {
145429aa 552 cur = (blocks_todo > b_max) ? b_max : blocks_todo;
11692991 553 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
d4d64889 554 pr_debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 555 return 0;
11692991 556 }
4a1a06bc
AS		 557 blocks_todo -= cur;
558 start += cur;
559 dst += cur * mmc->read_bl_len;
560 } while (blocks_todo > 0);
272cc70b
AF		 561
562 return blkcnt;
563}
564
fdbb873e 565static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 566{
567 struct mmc_cmd cmd;
568 int err;
569
570 udelay(1000);
571
572 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
573 cmd.cmdarg = 0;
574 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 575
576 err = mmc_send_cmd(mmc, &cmd, NULL);
577
578 if (err)
579 return err;
580
581 udelay(2000);
582
583 return 0;
584}
585
f99c2efe 586#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 587static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
588{
589 struct mmc_cmd cmd;
590 int err = 0;
591
592 /*
593 * Send CMD11 only if the request is to switch the card to
594 * 1.8V signalling.
595 */
596 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
597 return mmc_set_signal_voltage(mmc, signal_voltage);
598
599 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
600 cmd.cmdarg = 0;
601 cmd.resp_type = MMC_RSP_R1;
602
603 err = mmc_send_cmd(mmc, &cmd, NULL);
604 if (err)
605 return err;
606
607 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
608 return -EIO;
609
610 /*
611 * The card should drive cmd and dat[0:3] low immediately
612 * after the response of cmd11, but wait 100 us to be sure
613 */
614 err = mmc_wait_dat0(mmc, 0, 100);
615 if (err == -ENOSYS)
616 udelay(100);
617 else if (err)
618 return -ETIMEDOUT;
619
620 /*
621 * During a signal voltage level switch, the clock must be gated
622 * for 5 ms according to the SD spec
623 */
65117182 624 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
c10b85d6
JJH		 625
626 err = mmc_set_signal_voltage(mmc, signal_voltage);
627 if (err)
628 return err;
629
630 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
631 mdelay(10);
65117182 632 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
c10b85d6
JJH		 633
634 /*
635 * Failure to switch is indicated by the card holding
636 * dat[0:3] low. Wait for at least 1 ms according to spec
637 */
638 err = mmc_wait_dat0(mmc, 1, 1000);
639 if (err == -ENOSYS)
640 udelay(1000);
641 else if (err)
642 return -ETIMEDOUT;
643
644 return 0;
645}
f99c2efe 646#endif
c10b85d6
JJH		 647
648static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 649{
650 int timeout = 1000;
651 int err;
652 struct mmc_cmd cmd;
653
1677eef4 654 while (1) {
272cc70b
AF		 655 cmd.cmdidx = MMC_CMD_APP_CMD;
656 cmd.resp_type = MMC_RSP_R1;
657 cmd.cmdarg = 0;
272cc70b
AF		 658
659 err = mmc_send_cmd(mmc, &cmd, NULL);
660
661 if (err)
662 return err;
663
664 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
665 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 666
667 /*
668 * Most cards do not answer if some reserved bits
669 * in the ocr are set. However, Some controller
670 * can set bit 7 (reserved for low voltages), but
671 * how to manage low voltages SD card is not yet
672 * specified.
673 */
d52ebf10 674 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 675 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 676
677 if (mmc->version == SD_VERSION_2)
678 cmd.cmdarg |= OCR_HCS;
679
c10b85d6
JJH		 680 if (uhs_en)
681 cmd.cmdarg |= OCR_S18R;
682
272cc70b
AF		 683 err = mmc_send_cmd(mmc, &cmd, NULL);
684
685 if (err)
686 return err;
687
1677eef4
AG		 688 if (cmd.response[0] & OCR_BUSY)
689 break;
690
691 if (timeout-- <= 0)
915ffa52 692 return -EOPNOTSUPP;
272cc70b 693
1677eef4
AG		 694 udelay(1000);
695 }
272cc70b
AF		 696
697 if (mmc->version != SD_VERSION_2)
698 mmc->version = SD_VERSION_1_0;
699
d52ebf10
TC		 700 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
701 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
702 cmd.resp_type = MMC_RSP_R3;
703 cmd.cmdarg = 0;
d52ebf10
TC		 704
705 err = mmc_send_cmd(mmc, &cmd, NULL);
706
707 if (err)
708 return err;
709 }
710
998be3dd 711 mmc->ocr = cmd.response[0];
272cc70b 712
f99c2efe 713#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 714 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
715 == 0x41000000) {
716 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
717 if (err)
718 return err;
719 }
f99c2efe 720#endif
c10b85d6 721
272cc70b
AF		 722 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
723 mmc->rca = 0;
724
725 return 0;
726}
727
5289b535 728static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 729{
5289b535 730 struct mmc_cmd cmd;
272cc70b
AF		 731 int err;
732
5289b535
AG		 733 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
734 cmd.resp_type = MMC_RSP_R3;
735 cmd.cmdarg = 0;
5a20397b
RH		 736 if (use_arg && !mmc_host_is_spi(mmc))
737 cmd.cmdarg = OCR_HCS |
93bfd616 738 (mmc->cfg->voltages &
a626c8d4
AG		 739 (mmc->ocr & OCR_VOLTAGE_MASK)) |
740 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 741
5289b535 742 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 743 if (err)
744 return err;
5289b535 745 mmc->ocr = cmd.response[0];
e9550449
CLC		 746 return 0;
747}
748
750121c3 749static int mmc_send_op_cond(struct mmc *mmc)
e9550449 750{
e9550449 751 int err, i;
fe95905f 752 int timeout = 1000;
822afeb7 753 ulong start;
e9550449 754
272cc70b
AF		 755 /* Some cards seem to need this */
756 mmc_go_idle(mmc);
757
fe95905f 758 start = get_timer(0);
0cf207ec 759 /* Asking to the card its capabilities */
fe95905f 760 for (i = 0; ; i++) {
5289b535 761 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 762 if (err)
763 return err;
cd6881b5 764
e9550449 765 /* exit if not busy (flag seems to be inverted) */
a626c8d4 766 if (mmc->ocr & OCR_BUSY)
bd47c135 767 break;
fe95905f
HC		 768
769 if (get_timer(start) > timeout)
770 return -ETIMEDOUT;
771 udelay(100);
e9550449 772 }
bd47c135
AG		 773 mmc->op_cond_pending = 1;
774 return 0;
e9550449 775}
cd6881b5 776
750121c3 777static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 778{
779 struct mmc_cmd cmd;
780 int timeout = 1000;
36332b6e 781 ulong start;
e9550449 782 int err;
cd6881b5 783
e9550449 784 mmc->op_cond_pending = 0;
cc17c01f 785 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 786 /* Some cards seem to need this */
787 mmc_go_idle(mmc);
788
cc17c01f 789 start = get_timer(0);
1677eef4 790 while (1) {
cc17c01f
AG		 791 err = mmc_send_op_cond_iter(mmc, 1);
792 if (err)
793 return err;
1677eef4
AG		 794 if (mmc->ocr & OCR_BUSY)
795 break;
cc17c01f 796 if (get_timer(start) > timeout)
915ffa52 797 return -EOPNOTSUPP;
cc17c01f 798 udelay(100);
1677eef4 799 }
cc17c01f 800 }
272cc70b 801
d52ebf10
TC		 802 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
803 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
804 cmd.resp_type = MMC_RSP_R3;
805 cmd.cmdarg = 0;
d52ebf10
TC		 806
807 err = mmc_send_cmd(mmc, &cmd, NULL);
808
809 if (err)
810 return err;
a626c8d4
AG		 811
812 mmc->ocr = cmd.response[0];
d52ebf10
TC		 813 }
814
272cc70b 815 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 816
817 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 818 mmc->rca = 1;
272cc70b
AF		 819
820 return 0;
821}
822
1601ea21 823int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 824{
825 struct mmc_cmd cmd;
826 struct mmc_data data;
827 int err;
828
829 /* Get the Card Status Register */
830 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
831 cmd.resp_type = MMC_RSP_R1;
832 cmd.cmdarg = 0;
272cc70b 833
cdfd1ac6 834 data.dest = (char *)ext_csd;
272cc70b 835 data.blocks = 1;
8bfa195e 836 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 837 data.flags = MMC_DATA_READ;
838
839 err = mmc_send_cmd(mmc, &cmd, &data);
840
841 return err;
842}
843
6892550c
MV		 844static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
845 bool send_status)
272cc70b 846{
822afeb7
RW		 847 ulong start;
848 unsigned int status;
272cc70b 849 struct mmc_cmd cmd;
6cf8a903 850 int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
513e00b6
JJH		 851 bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
852 (index == EXT_CSD_PART_CONF);
5d4fc8d9 853 int ret;
272cc70b 854
39320c53 855 if (mmc->gen_cmd6_time)
6cf8a903 856 timeout_ms = mmc->gen_cmd6_time * 10;
39320c53 857
513e00b6 858 if (is_part_switch && mmc->part_switch_time)
6cf8a903 859 timeout_ms = mmc->part_switch_time * 10;
513e00b6 860
272cc70b
AF		 861 cmd.cmdidx = MMC_CMD_SWITCH;
862 cmd.resp_type = MMC_RSP_R1b;
863 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 864 (index << 16) |
865 (value << 8);
272cc70b 866
da129170 867 ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3);
bb98b8c5
JJH		 868 if (ret)
869 return ret;
6892550c 870
bb98b8c5 871 start = get_timer(0);
a9003dc6 872
bb98b8c5 873 /* poll dat0 for rdy/buys status */
6cf8a903 874 ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
bb98b8c5
JJH		 875 if (ret && ret != -ENOSYS)
876 return ret;
5d4fc8d9 877
bb98b8c5 878 /*
44645f87 879 * In cases when neiter allowed to poll by using CMD13 nor we are
bb98b8c5
JJH		 880 * capable of polling by using mmc_wait_dat0, then rely on waiting the
881 * stated timeout to be sufficient.
882 */
44645f87 883 if (ret == -ENOSYS && !send_status) {
6cf8a903 884 mdelay(timeout_ms);
ef5ab0d1
HC		 885 return 0;
886 }
bb98b8c5 887
2349ecff
MV		 888 if (!send_status)
889 return 0;
890
bb98b8c5
JJH		 891 /* Finally wait until the card is ready or indicates a failure
892 * to switch. It doesn't hurt to use CMD13 here even if send_status
6cf8a903 893 * is false, because by now (after 'timeout_ms' ms) the bus should be
bb98b8c5
JJH		 894 * reliable.
895 */
896 do {
897 ret = mmc_send_status(mmc, &status);
898
899 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
900 pr_debug("switch failed %d/%d/0x%x !\n", set, index,
901 value);
902 return -EIO;
903 }
8e2b0af7
SB		 904 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA) &&
905 (status & MMC_STATUS_CURR_STATE) == MMC_STATE_TRANS)
bb98b8c5
JJH		 906 return 0;
907 udelay(100);
6cf8a903 908 } while (get_timer(start) < timeout_ms);
5d4fc8d9 909
bb98b8c5 910 return -ETIMEDOUT;
272cc70b
AF		 911}
912
6892550c
MV		 913int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
914{
915 return __mmc_switch(mmc, set, index, value, true);
916}
917
0469d846
HS		 918int mmc_boot_wp(struct mmc *mmc)
919{
920 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
921}
922
19a29ff3
YCLP		 923int mmc_boot_wp_single_partition(struct mmc *mmc, int partition)
924{
925 u8 value;
926 int ret;
927
928 value = EXT_CSD_BOOT_WP_B_PWR_WP_EN;
929
930 if (partition == 0) {
931 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
932 ret = mmc_switch(mmc,
933 EXT_CSD_CMD_SET_NORMAL,
934 EXT_CSD_BOOT_WP,
935 value);
936 } else if (partition == 1) {
937 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
938 value |= EXT_CSD_BOOT_WP_B_PWR_WP_SEC_SEL;
939 ret = mmc_switch(mmc,
940 EXT_CSD_CMD_SET_NORMAL,
941 EXT_CSD_BOOT_WP,
942 value);
943 } else {
944 ret = mmc_boot_wp(mmc);
945 }
946
947 return ret;
948}
949
62d77cea 950#if !CONFIG_IS_ENABLED(MMC_TINY)
b9a2a0e2
MV		 951static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
952 bool hsdowngrade)
272cc70b 953{
272cc70b 954 int err;
3862b854
JJH		 955 int speed_bits;
956
957 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
958
959 switch (mode) {
960 case MMC_HS:
961 case MMC_HS_52:
962 case MMC_DDR_52:
963 speed_bits = EXT_CSD_TIMING_HS;
634d4849 964 break;
baef2070 965#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 966 case MMC_HS_200:
967 speed_bits = EXT_CSD_TIMING_HS200;
968 break;
3dd2626f
PF		 969#endif
970#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
971 case MMC_HS_400:
972 speed_bits = EXT_CSD_TIMING_HS400;
973 break;
44acd492
PF		 974#endif
975#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
976 case MMC_HS_400_ES:
977 speed_bits = EXT_CSD_TIMING_HS400;
978 break;
baef2070 979#endif
3862b854
JJH		 980 case MMC_LEGACY:
981 speed_bits = EXT_CSD_TIMING_LEGACY;
982 break;
983 default:
984 return -EINVAL;
985 }
6892550c
MV		 986
987 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
988 speed_bits, !hsdowngrade);
3862b854
JJH		 989 if (err)
990 return err;
991
b9a2a0e2
MV		 992#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
993 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
994 /*
995 * In case the eMMC is in HS200/HS400 mode and we are downgrading
996 * to HS mode, the card clock are still running much faster than
997 * the supported HS mode clock, so we can not reliably read out
998 * Extended CSD. Reconfigure the controller to run at HS mode.
999 */
1000 if (hsdowngrade) {
efddda8f
VYA		 1001 mmc_select_mode(mmc, MMC_HS_52);
1002 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS_52), false);
b9a2a0e2
MV		 1003 }
1004#endif
1005
3862b854
JJH		 1006 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
1007 /* Now check to see that it worked */
1008 err = mmc_send_ext_csd(mmc, test_csd);
1009 if (err)
1010 return err;
1011
1012 /* No high-speed support */
1013 if (!test_csd[EXT_CSD_HS_TIMING])
1014 return -ENOTSUPP;
1015 }
1016
1017 return 0;
1018}
1019
1020static int mmc_get_capabilities(struct mmc *mmc)
1021{
1022 u8 *ext_csd = mmc->ext_csd;
1023 char cardtype;
272cc70b 1024
00e446fa 1025 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 1026
d52ebf10
TC		 1027 if (mmc_host_is_spi(mmc))
1028 return 0;
1029
272cc70b
AF		 1030 /* Only version 4 supports high-speed */
1031 if (mmc->version < MMC_VERSION_4)
1032 return 0;
1033
3862b854 1034 if (!ext_csd) {
99b23d45 1035 log_err("No ext_csd found!\n"); /* this should never happen */
3862b854
JJH		 1036 return -ENOTSUPP;
1037 }
272cc70b 1038
3862b854 1039 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 1040
3dd2626f 1041 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
bc1e3272 1042 mmc->cardtype = cardtype;
272cc70b 1043
baef2070 1044#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 1045 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1046 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
1047 mmc->card_caps |= MMC_MODE_HS200;
1048 }
3dd2626f 1049#endif
44acd492
PF		 1050#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
1051 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
3dd2626f
PF		 1052 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
1053 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
1054 mmc->card_caps |= MMC_MODE_HS400;
1055 }
baef2070 1056#endif
d22e3d46 1057 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 1058 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 1059 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 1060 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 1061 }
3862b854
JJH		 1062 if (cardtype & EXT_CSD_CARD_TYPE_26)
1063 mmc->card_caps |= MMC_MODE_HS;
272cc70b 1064
44acd492
PF		 1065#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1066 if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
1067 (mmc->card_caps & MMC_MODE_HS400)) {
1068 mmc->card_caps |= MMC_MODE_HS400_ES;
1069 }
1070#endif
1071
272cc70b
AF		 1072 return 0;
1073}
62d77cea 1074#endif
272cc70b 1075
f866a46d
SW		 1076static int mmc_set_capacity(struct mmc *mmc, int part_num)
1077{
1078 switch (part_num) {
1079 case 0:
1080 mmc->capacity = mmc->capacity_user;
1081 break;
1082 case 1:
1083 case 2:
1084 mmc->capacity = mmc->capacity_boot;
1085 break;
1086 case 3:
1087 mmc->capacity = mmc->capacity_rpmb;
1088 break;
1089 case 4:
1090 case 5:
1091 case 6:
1092 case 7:
1093 mmc->capacity = mmc->capacity_gp[part_num - 4];
1094 break;
1095 default:
1096 return -1;
1097 }
1098
c40fdca6 1099 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 1100
1101 return 0;
1102}
1103
7dba0b93 1104int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 1105{
f866a46d 1106 int ret;
0538477c 1107 int retry = 3;
bc897b1d 1108
0538477c
JJH		 1109 do {
1110 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1111 EXT_CSD_PART_CONF,
1112 (mmc->part_config & ~PART_ACCESS_MASK)
1113 | (part_num & PART_ACCESS_MASK));
1114 } while (ret && retry--);
f866a46d 1115
6dc93e70
PB		 1116 /*
1117 * Set the capacity if the switch succeeded or was intended
1118 * to return to representing the raw device.
1119 */
873cc1d7 1120 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 1121 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 1122 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 1123 }
6dc93e70
PB		 1124
1125 return ret;
bc897b1d
LW		 1126}
1127
cf17789e 1128#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
ac9da0e0
DSC		 1129int mmc_hwpart_config(struct mmc *mmc,
1130 const struct mmc_hwpart_conf *conf,
1131 enum mmc_hwpart_conf_mode mode)
1132{
1133 u8 part_attrs = 0;
1134 u32 enh_size_mult;
1135 u32 enh_start_addr;
1136 u32 gp_size_mult[4];
1137 u32 max_enh_size_mult;
1138 u32 tot_enh_size_mult = 0;
8dda5b0e 1139 u8 wr_rel_set;
ac9da0e0
DSC		 1140 int i, pidx, err;
1141 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1142
1143 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1144 return -EINVAL;
1145
1146 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
99b23d45 1147 log_err("eMMC >= 4.4 required for enhanced user data area\n");
ac9da0e0
DSC		 1148 return -EMEDIUMTYPE;
1149 }
1150
1151 if (!(mmc->part_support & PART_SUPPORT)) {
99b23d45 1152 log_err("Card does not support partitioning\n");
ac9da0e0
DSC		 1153 return -EMEDIUMTYPE;
1154 }
1155
1156 if (!mmc->hc_wp_grp_size) {
99b23d45 1157 log_err("Card does not define HC WP group size\n");
ac9da0e0
DSC		 1158 return -EMEDIUMTYPE;
1159 }
1160
1161 /* check partition alignment and total enhanced size */
1162 if (conf->user.enh_size) {
1163 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1164 conf->user.enh_start % mmc->hc_wp_grp_size) {
99b23d45 1165 log_err("User data enhanced area not HC WP group size aligned\n");
ac9da0e0
DSC		 1166 return -EINVAL;
1167 }
1168 part_attrs |= EXT_CSD_ENH_USR;
1169 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1170 if (mmc->high_capacity) {
1171 enh_start_addr = conf->user.enh_start;
1172 } else {
1173 enh_start_addr = (conf->user.enh_start << 9);
1174 }
1175 } else {
1176 enh_size_mult = 0;
1177 enh_start_addr = 0;
1178 }
1179 tot_enh_size_mult += enh_size_mult;
1180
1181 for (pidx = 0; pidx < 4; pidx++) {
1182 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
99b23d45
SG		 1183 log_err("GP%i partition not HC WP group-size aligned\n",
1184 pidx + 1);
ac9da0e0
DSC		 1185 return -EINVAL;
1186 }
1187 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1188 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1189 part_attrs |= EXT_CSD_ENH_GP(pidx);
1190 tot_enh_size_mult += gp_size_mult[pidx];
1191 }
1192 }
1193
1194 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
99b23d45 1195 log_err("Card does not support enhanced attribute\n");
ac9da0e0
DSC		 1196 return -EMEDIUMTYPE;
1197 }
1198
1199 err = mmc_send_ext_csd(mmc, ext_csd);
1200 if (err)
1201 return err;
1202
1203 max_enh_size_mult =
1204 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1205 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1206 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1207 if (tot_enh_size_mult > max_enh_size_mult) {
99b23d45
SG		 1208 log_err("Total enhanced size exceeds maximum (%#x > %#x)\n",
1209 tot_enh_size_mult, max_enh_size_mult);
ac9da0e0
DSC		 1210 return -EMEDIUMTYPE;
1211 }
1212
8dda5b0e
DSC		 1213 /* The default value of EXT_CSD_WR_REL_SET is device
1214 * dependent, the values can only be changed if the
1215 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1216 * changed only once and before partitioning is completed. */
1217 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1218 if (conf->user.wr_rel_change) {
1219 if (conf->user.wr_rel_set)
1220 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1221 else
1222 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1223 }
1224 for (pidx = 0; pidx < 4; pidx++) {
1225 if (conf->gp_part[pidx].wr_rel_change) {
1226 if (conf->gp_part[pidx].wr_rel_set)
1227 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1228 else
1229 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1230 }
1231 }
1232
1233 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1234 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1235 puts("Card does not support host controlled partition write "
1236 "reliability settings\n");
1237 return -EMEDIUMTYPE;
1238 }
1239
ac9da0e0
DSC		 1240 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1241 EXT_CSD_PARTITION_SETTING_COMPLETED) {
99b23d45 1242 log_err("Card already partitioned\n");
ac9da0e0
DSC		 1243 return -EPERM;
1244 }
1245
1246 if (mode == MMC_HWPART_CONF_CHECK)
1247 return 0;
1248
1249 /* Partitioning requires high-capacity size definitions */
1250 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1251 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1252 EXT_CSD_ERASE_GROUP_DEF, 1);
1253
1254 if (err)
1255 return err;
1256
1257 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1258
4af66596 1259#if CONFIG_IS_ENABLED(MMC_WRITE)
ac9da0e0
DSC		 1260 /* update erase group size to be high-capacity */
1261 mmc->erase_grp_size =
1262 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
4af66596 1263#endif
ac9da0e0
DSC		 1264
1265 }
1266
1267 /* all OK, write the configuration */
1268 for (i = 0; i < 4; i++) {
1269 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1270 EXT_CSD_ENH_START_ADDR+i,
1271 (enh_start_addr >> (i*8)) & 0xFF);
1272 if (err)
1273 return err;
1274 }
1275 for (i = 0; i < 3; i++) {
1276 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1277 EXT_CSD_ENH_SIZE_MULT+i,
1278 (enh_size_mult >> (i*8)) & 0xFF);
1279 if (err)
1280 return err;
1281 }
1282 for (pidx = 0; pidx < 4; pidx++) {
1283 for (i = 0; i < 3; i++) {
1284 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1285 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1286 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1287 if (err)
1288 return err;
1289 }
1290 }
1291 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1292 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1293 if (err)
1294 return err;
1295
1296 if (mode == MMC_HWPART_CONF_SET)
1297 return 0;
1298
8dda5b0e
DSC		 1299 /* The WR_REL_SET is a write-once register but shall be
1300 * written before setting PART_SETTING_COMPLETED. As it is
1301 * write-once we can only write it when completing the
1302 * partitioning. */
1303 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1304 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1305 EXT_CSD_WR_REL_SET, wr_rel_set);
1306 if (err)
1307 return err;
1308 }
1309
ac9da0e0
DSC		 1310 /* Setting PART_SETTING_COMPLETED confirms the partition
1311 * configuration but it only becomes effective after power
1312 * cycle, so we do not adjust the partition related settings
1313 * in the mmc struct. */
1314
1315 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1316 EXT_CSD_PARTITION_SETTING,
1317 EXT_CSD_PARTITION_SETTING_COMPLETED);
1318 if (err)
1319 return err;
1320
1321 return 0;
1322}
cf17789e 1323#endif
ac9da0e0 1324
e7881d85 1325#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1326int mmc_getcd(struct mmc *mmc)
1327{
1328 int cd;
1329
1330 cd = board_mmc_getcd(mmc);
1331
d4e1da4e 1332 if (cd < 0) {
93bfd616
PA		 1333 if (mmc->cfg->ops->getcd)
1334 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1335 else
1336 cd = 1;
1337 }
48972d90
TR		 1338
1339 return cd;
1340}
8ca51e51 1341#endif
48972d90 1342
62d77cea 1343#if !CONFIG_IS_ENABLED(MMC_TINY)
fdbb873e 1344static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1345{
1346 struct mmc_cmd cmd;
1347 struct mmc_data data;
1348
1349 /* Switch the frequency */
1350 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1351 cmd.resp_type = MMC_RSP_R1;
1352 cmd.cmdarg = (mode << 31) | 0xffffff;
1353 cmd.cmdarg &= ~(0xf << (group * 4));
1354 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1355
1356 data.dest = (char *)resp;
1357 data.blocksize = 64;
1358 data.blocks = 1;
1359 data.flags = MMC_DATA_READ;
1360
1361 return mmc_send_cmd(mmc, &cmd, &data);
1362}
1363
d0c221fe 1364static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1365{
1366 int err;
1367 struct mmc_cmd cmd;
18e7c8f6
SM		 1368 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1369 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1370 struct mmc_data data;
1371 int timeout;
f99c2efe 1372#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1373 u32 sd3_bus_mode;
f99c2efe 1374#endif
272cc70b 1375
e8d5dde4 1376 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 1377
d52ebf10
TC		 1378 if (mmc_host_is_spi(mmc))
1379 return 0;
1380
272cc70b
AF		 1381 /* Read the SCR to find out if this card supports higher speeds */
1382 cmd.cmdidx = MMC_CMD_APP_CMD;
1383 cmd.resp_type = MMC_RSP_R1;
1384 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1385
1386 err = mmc_send_cmd(mmc, &cmd, NULL);
1387
1388 if (err)
1389 return err;
1390
1391 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1392 cmd.resp_type = MMC_RSP_R1;
1393 cmd.cmdarg = 0;
272cc70b 1394
f781dd38 1395 data.dest = (char *)scr;
272cc70b
AF		 1396 data.blocksize = 8;
1397 data.blocks = 1;
1398 data.flags = MMC_DATA_READ;
1399
da129170 1400 err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
272cc70b 1401
da129170 1402 if (err)
272cc70b 1403 return err;
272cc70b 1404
4e3d89ba
YK		 1405 mmc->scr[0] = __be32_to_cpu(scr[0]);
1406 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1407
1408 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1409 case 0:
1410 mmc->version = SD_VERSION_1_0;
1411 break;
1412 case 1:
1413 mmc->version = SD_VERSION_1_10;
1414 break;
1415 case 2:
1416 mmc->version = SD_VERSION_2;
1417 if ((mmc->scr[0] >> 15) & 0x1)
1418 mmc->version = SD_VERSION_3;
1419 break;
1420 default:
1421 mmc->version = SD_VERSION_1_0;
1422 break;
272cc70b
AF		 1423 }
1424
b44c7083
AS		 1425 if (mmc->scr[0] & SD_DATA_4BIT)
1426 mmc->card_caps |= MMC_MODE_4BIT;
1427
272cc70b
AF		 1428 /* Version 1.0 doesn't support switching */
1429 if (mmc->version == SD_VERSION_1_0)
1430 return 0;
1431
1432 timeout = 4;
1433 while (timeout--) {
1434 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1435 (u8 *)switch_status);
272cc70b
AF		 1436
1437 if (err)
1438 return err;
1439
1440 /* The high-speed function is busy. Try again */
4e3d89ba 1441 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1442 break;
1443 }
1444
272cc70b 1445 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1446 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1447 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1448
f99c2efe 1449#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1450 /* Version before 3.0 don't support UHS modes */
1451 if (mmc->version < SD_VERSION_3)
1452 return 0;
1453
1454 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1455 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1456 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1457 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1458 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1459 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1460 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1461 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1462 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1463 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1464 mmc->card_caps |= MMC_CAP(UHS_DDR50);
f99c2efe 1465#endif
c10b85d6 1466
d0c221fe
JJH		 1467 return 0;
1468}
1469
1470static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1471{
1472 int err;
1473
1474 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1475 int speed;
2c3fbf4c 1476
cf345760
MV		 1477 /* SD version 1.00 and 1.01 does not support CMD 6 */
1478 if (mmc->version == SD_VERSION_1_0)
1479 return 0;
1480
c10b85d6 1481 switch (mode) {
e8d5dde4 1482 case MMC_LEGACY:
c10b85d6
JJH		 1483 speed = UHS_SDR12_BUS_SPEED;
1484 break;
1485 case SD_HS:
baef2070
JJH		 1486 speed = HIGH_SPEED_BUS_SPEED;
1487 break;
1488#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1489 case UHS_SDR12:
1490 speed = UHS_SDR12_BUS_SPEED;
1491 break;
c10b85d6
JJH		 1492 case UHS_SDR25:
1493 speed = UHS_SDR25_BUS_SPEED;
1494 break;
1495 case UHS_SDR50:
1496 speed = UHS_SDR50_BUS_SPEED;
1497 break;
1498 case UHS_DDR50:
1499 speed = UHS_DDR50_BUS_SPEED;
1500 break;
1501 case UHS_SDR104:
1502 speed = UHS_SDR104_BUS_SPEED;
1503 break;
baef2070 1504#endif
c10b85d6
JJH		 1505 default:
1506 return -EINVAL;
1507 }
1508
1509 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1510 if (err)
1511 return err;
1512
a0276f3e 1513 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
d0c221fe 1514 return -ENOTSUPP;
272cc70b 1515
d0c221fe
JJH		 1516 return 0;
1517}
1518
ec360e64 1519static int sd_select_bus_width(struct mmc *mmc, int w)
d0c221fe
JJH		 1520{
1521 int err;
1522 struct mmc_cmd cmd;
1523
1524 if ((w != 4) && (w != 1))
1525 return -EINVAL;
1526
1527 cmd.cmdidx = MMC_CMD_APP_CMD;
1528 cmd.resp_type = MMC_RSP_R1;
1529 cmd.cmdarg = mmc->rca << 16;
1530
1531 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1532 if (err)
1533 return err;
1534
d0c221fe
JJH		 1535 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1536 cmd.resp_type = MMC_RSP_R1;
1537 if (w == 4)
1538 cmd.cmdarg = 2;
1539 else if (w == 1)
1540 cmd.cmdarg = 0;
1541 err = mmc_send_cmd(mmc, &cmd, NULL);
1542 if (err)
1543 return err;
272cc70b
AF		 1544
1545 return 0;
1546}
62d77cea 1547#endif
272cc70b 1548
5b2e72f3 1549#if CONFIG_IS_ENABLED(MMC_WRITE)
3697e599
PF		 1550static int sd_read_ssr(struct mmc *mmc)
1551{
5b2e72f3
JJH		 1552 static const unsigned int sd_au_size[] = {
1553 0, SZ_16K / 512, SZ_32K / 512,
1554 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1555 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1556 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1557 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1558 SZ_64M / 512,
1559 };
3697e599
PF		 1560 int err, i;
1561 struct mmc_cmd cmd;
1562 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1563 struct mmc_data data;
3697e599
PF		 1564 unsigned int au, eo, et, es;
1565
1566 cmd.cmdidx = MMC_CMD_APP_CMD;
1567 cmd.resp_type = MMC_RSP_R1;
1568 cmd.cmdarg = mmc->rca << 16;
1569
da129170 1570 err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4);
3697e599
PF		 1571 if (err)
1572 return err;
1573
1574 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1575 cmd.resp_type = MMC_RSP_R1;
1576 cmd.cmdarg = 0;
1577
3697e599
PF		 1578 data.dest = (char *)ssr;
1579 data.blocksize = 64;
1580 data.blocks = 1;
1581 data.flags = MMC_DATA_READ;
1582
da129170
SA		 1583 err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
1584 if (err)
3697e599 1585 return err;
3697e599
PF		 1586
1587 for (i = 0; i < 16; i++)
1588 ssr[i] = be32_to_cpu(ssr[i]);
1589
1590 au = (ssr[2] >> 12) & 0xF;
1591 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1592 mmc->ssr.au = sd_au_size[au];
1593 es = (ssr[3] >> 24) & 0xFF;
1594 es |= (ssr[2] & 0xFF) << 8;
1595 et = (ssr[3] >> 18) & 0x3F;
1596 if (es && et) {
1597 eo = (ssr[3] >> 16) & 0x3;
1598 mmc->ssr.erase_timeout = (et * 1000) / es;
1599 mmc->ssr.erase_offset = eo * 1000;
1600 }
1601 } else {
d4d64889 1602 pr_debug("Invalid Allocation Unit Size.\n");
3697e599
PF		 1603 }
1604
1605 return 0;
1606}
5b2e72f3 1607#endif
f9a86fb1
HS		 1608/*
1609 * TRAN_SPEED bits 0:2 encode the frequency unit:
1610 * 0 = 100KHz, 1 = 1MHz, 2 = 10MHz, 3 = 100MHz, values 4 - 7 are reserved.
1611 * The values in fbase[] are divided by 10 to avoid floats in multiplier[].
1612 */
5f837c2c 1613static const int fbase[] = {
272cc70b
AF		 1614 10000,
1615 100000,
1616 1000000,
1617 10000000,
f9a86fb1
HS		 1618 0, /* reserved */
1619 0, /* reserved */
1620 0, /* reserved */
1621 0, /* reserved */
272cc70b
AF		 1622};
1623
1624/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1625 * to platforms without floating point.
1626 */
61fe076f 1627static const u8 multipliers[] = {
272cc70b
AF		 1628 0, /* reserved */
1629 10,
1630 12,
1631 13,
1632 15,
1633 20,
1634 25,
1635 30,
1636 35,
1637 40,
1638 45,
1639 50,
1640 55,
1641 60,
1642 70,
1643 80,
1644};
1645
d0c221fe
JJH		 1646static inline int bus_width(uint cap)
1647{
1648 if (cap == MMC_MODE_8BIT)
1649 return 8;
1650 if (cap == MMC_MODE_4BIT)
1651 return 4;
1652 if (cap == MMC_MODE_1BIT)
1653 return 1;
d8e3d420 1654 pr_warn("invalid bus witdh capability 0x%x\n", cap);
d0c221fe
JJH		 1655 return 0;
1656}
1657
e7881d85 1658#if !CONFIG_IS_ENABLED(DM_MMC)
03de305e 1659#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
ec841209
KVA		 1660static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1661{
1662 return -ENOTSUPP;
1663}
f99c2efe 1664#endif
ec841209 1665
2a4d212f 1666static int mmc_set_ios(struct mmc *mmc)
272cc70b 1667{
2a4d212f
KVA		 1668 int ret = 0;
1669
93bfd616 1670 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1671 ret = mmc->cfg->ops->set_ios(mmc);
1672
1673 return ret;
272cc70b 1674}
3602a56a
YG		 1675
1676static int mmc_host_power_cycle(struct mmc *mmc)
1677{
1678 int ret = 0;
1679
1680 if (mmc->cfg->ops->host_power_cycle)
1681 ret = mmc->cfg->ops->host_power_cycle(mmc);
1682
1683 return ret;
1684}
8ca51e51 1685#endif
272cc70b 1686
35f67820 1687int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1688{
c0fafe64 1689 if (!disable) {
9546eb92
JC		 1690 if (clock > mmc->cfg->f_max)
1691 clock = mmc->cfg->f_max;
272cc70b 1692
9546eb92
JC		 1693 if (clock < mmc->cfg->f_min)
1694 clock = mmc->cfg->f_min;
1695 }
272cc70b
AF		 1696
1697 mmc->clock = clock;
35f67820 1698 mmc->clk_disable = disable;
272cc70b 1699
d2faadb5
JC		 1700 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1701
2a4d212f 1702 return mmc_set_ios(mmc);
272cc70b
AF		 1703}
1704
2a4d212f 1705static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1706{
1707 mmc->bus_width = width;
1708
2a4d212f 1709 return mmc_set_ios(mmc);
272cc70b
AF		 1710}
1711
4c9d2aaa
JJH		 1712#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1713/*
1714 * helper function to display the capabilities in a human
1715 * friendly manner. The capabilities include bus width and
1716 * supported modes.
1717 */
1718void mmc_dump_capabilities(const char *text, uint caps)
1719{
1720 enum bus_mode mode;
1721
d4d64889 1722 pr_debug("%s: widths [", text);
4c9d2aaa 1723 if (caps & MMC_MODE_8BIT)
d4d64889 1724 pr_debug("8, ");
4c9d2aaa 1725 if (caps & MMC_MODE_4BIT)
d4d64889 1726 pr_debug("4, ");
d0c221fe 1727 if (caps & MMC_MODE_1BIT)
d4d64889
MY		 1728 pr_debug("1, ");
1729 pr_debug("\b\b] modes [");
4c9d2aaa
JJH		 1730 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1731 if (MMC_CAP(mode) & caps)
d4d64889
MY		 1732 pr_debug("%s, ", mmc_mode_name(mode));
1733 pr_debug("\b\b]\n");
4c9d2aaa
JJH		 1734}
1735#endif
1736
d0c221fe
JJH		 1737struct mode_width_tuning {
1738 enum bus_mode mode;
1739 uint widths;
03de305e 1740#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
634d4849 1741 uint tuning;
f99c2efe 1742#endif
d0c221fe
JJH		 1743};
1744
f99c2efe 1745#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1746int mmc_voltage_to_mv(enum mmc_voltage voltage)
1747{
1748 switch (voltage) {
1749 case MMC_SIGNAL_VOLTAGE_000: return 0;
1750 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1751 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1752 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1753 }
1754 return -EINVAL;
1755}
1756
aff5d3c8
KVA		 1757static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1758{
bc1e3272
JJH		 1759 int err;
1760
1761 if (mmc->signal_voltage == signal_voltage)
1762 return 0;
1763
aff5d3c8 1764 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1765 err = mmc_set_ios(mmc);
1766 if (err)
d4d64889 1767 pr_debug("unable to set voltage (err %d)\n", err);
bc1e3272
JJH		 1768
1769 return err;
aff5d3c8 1770}
f99c2efe
JJH		 1771#else
1772static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1773{
1774 return 0;
1775}
1776#endif
aff5d3c8 1777
62d77cea 1778#if !CONFIG_IS_ENABLED(MMC_TINY)
d0c221fe 1779static const struct mode_width_tuning sd_modes_by_pref[] = {
f99c2efe 1780#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
03de305e 1781#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
c10b85d6
JJH		 1782 {
1783 .mode = UHS_SDR104,
1784 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1785 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1786 },
f99c2efe 1787#endif
c10b85d6
JJH		 1788 {
1789 .mode = UHS_SDR50,
1790 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1791 },
1792 {
1793 .mode = UHS_DDR50,
1794 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1795 },
1796 {
1797 .mode = UHS_SDR25,
1798 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1799 },
f99c2efe 1800#endif
d0c221fe
JJH		 1801 {
1802 .mode = SD_HS,
1803 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1804 },
f99c2efe 1805#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1806 {
1807 .mode = UHS_SDR12,
1808 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1809 },
f99c2efe 1810#endif
d0c221fe 1811 {
e8d5dde4 1812 .mode = MMC_LEGACY,
d0c221fe
JJH		 1813 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1814 }
1815};
1816
1817#define for_each_sd_mode_by_pref(caps, mwt) \
1818 for (mwt = sd_modes_by_pref;\
1819 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1820 mwt++) \
1821 if (caps & MMC_CAP(mwt->mode))
1822
01298da3 1823static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1824{
1825 int err;
d0c221fe
JJH		 1826 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1827 const struct mode_width_tuning *mwt;
f99c2efe 1828#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1829 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
f99c2efe
JJH		 1830#else
1831 bool uhs_en = false;
1832#endif
c10b85d6
JJH		 1833 uint caps;
1834
52d241df
JJH		 1835#ifdef DEBUG
1836 mmc_dump_capabilities("sd card", card_caps);
1da8eb59 1837 mmc_dump_capabilities("host", mmc->host_caps);
52d241df 1838#endif
8ac8a263 1839
f49ff799
AP		 1840 if (mmc_host_is_spi(mmc)) {
1841 mmc_set_bus_width(mmc, 1);
e8d5dde4 1842 mmc_select_mode(mmc, MMC_LEGACY);
f49ff799 1843 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
810bc138
PP		 1844#if CONFIG_IS_ENABLED(MMC_WRITE)
1845 err = sd_read_ssr(mmc);
1846 if (err)
1847 pr_warn("unable to read ssr\n");
1848#endif
f49ff799
AP		 1849 return 0;
1850 }
1851
8ac8a263 1852 /* Restrict card's capabilities by what the host can do */
1da8eb59 1853 caps = card_caps & mmc->host_caps;
d0c221fe 1854
c10b85d6
JJH		 1855 if (!uhs_en)
1856 caps &= ~UHS_CAPS;
1857
1858 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1859 uint *w;
1860
1861 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1862 if (*w & caps & mwt->widths) {
d4d64889
MY		 1863 pr_debug("trying mode %s width %d (at %d MHz)\n",
1864 mmc_mode_name(mwt->mode),
1865 bus_width(*w),
1866 mmc_mode2freq(mmc, mwt->mode) / 1000000);
d0c221fe
JJH		 1867
1868 /* configure the bus width (card + host) */
1869 err = sd_select_bus_width(mmc, bus_width(*w));
1870 if (err)
1871 goto error;
1872 mmc_set_bus_width(mmc, bus_width(*w));
1873
1874 /* configure the bus mode (card) */
1875 err = sd_set_card_speed(mmc, mwt->mode);
1876 if (err)
1877 goto error;
1878
1879 /* configure the bus mode (host) */
1880 mmc_select_mode(mmc, mwt->mode);
65117182
JC		 1881 mmc_set_clock(mmc, mmc->tran_speed,
1882 MMC_CLK_ENABLE);
d0c221fe 1883
03de305e 1884#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
c10b85d6
JJH		 1885 /* execute tuning if needed */
1886 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1887 err = mmc_execute_tuning(mmc,
1888 mwt->tuning);
1889 if (err) {
d4d64889 1890 pr_debug("tuning failed\n");
c10b85d6
JJH		 1891 goto error;
1892 }
1893 }
f99c2efe 1894#endif
c10b85d6 1895
5b2e72f3 1896#if CONFIG_IS_ENABLED(MMC_WRITE)
d0c221fe 1897 err = sd_read_ssr(mmc);
0a4c2b09 1898 if (err)
5b2e72f3
JJH		 1899 pr_warn("unable to read ssr\n");
1900#endif
d0c221fe
JJH		 1901 if (!err)
1902 return 0;
1903
d0c221fe
JJH		 1904error:
1905 /* revert to a safer bus speed */
e8d5dde4 1906 mmc_select_mode(mmc, MMC_LEGACY);
65117182
JC		 1907 mmc_set_clock(mmc, mmc->tran_speed,
1908 MMC_CLK_ENABLE);
d0c221fe
JJH		 1909 }
1910 }
8ac8a263
JJH		 1911 }
1912
99b23d45 1913 log_err("unable to select a mode\n");
d0c221fe 1914 return -ENOTSUPP;
8ac8a263
JJH		 1915}
1916
7382e691
JJH		 1917/*
1918 * read the compare the part of ext csd that is constant.
1919 * This can be used to check that the transfer is working
1920 * as expected.
1921 */
1922static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1923{
7382e691 1924 int err;
dfda9d88 1925 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1926 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1927
1de06b9f
JJH		 1928 if (mmc->version < MMC_VERSION_4)
1929 return 0;
1930
7382e691
JJH		 1931 err = mmc_send_ext_csd(mmc, test_csd);
1932 if (err)
1933 return err;
1934
1935 /* Only compare read only fields */
1936 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1937 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1938 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1939 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1940 ext_csd[EXT_CSD_REV]
1941 == test_csd[EXT_CSD_REV] &&
1942 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1943 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1944 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1945 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1946 return 0;
1947
1948 return -EBADMSG;
1949}
1950
f99c2efe 1951#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1952static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1953 uint32_t allowed_mask)
1954{
1955 u32 card_mask = 0;
1956
1957 switch (mode) {
44acd492 1958 case MMC_HS_400_ES:
3dd2626f 1959 case MMC_HS_400:
bc1e3272 1960 case MMC_HS_200:
3dd2626f
PF		 1961 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1962 EXT_CSD_CARD_TYPE_HS400_1_8V))
bc1e3272 1963 card_mask |= MMC_SIGNAL_VOLTAGE_180;
3dd2626f
PF		 1964 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1965 EXT_CSD_CARD_TYPE_HS400_1_2V))
bc1e3272
JJH		 1966 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1967 break;
1968 case MMC_DDR_52:
1969 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1970 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1971 MMC_SIGNAL_VOLTAGE_180;
1972 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1973 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1974 break;
1975 default:
1976 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1977 break;
1978 }
1979
1980 while (card_mask & allowed_mask) {
1981 enum mmc_voltage best_match;
1982
1983 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1984 if (!mmc_set_signal_voltage(mmc, best_match))
1985 return 0;
1986
1987 allowed_mask &= ~best_match;
1988 }
1989
1990 return -ENOTSUPP;
1991}
f99c2efe
JJH		 1992#else
1993static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1994 uint32_t allowed_mask)
1995{
1996 return 0;
1997}
1998#endif
bc1e3272 1999
3862b854 2000static const struct mode_width_tuning mmc_modes_by_pref[] = {
44acd492
PF		 2001#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2002 {
2003 .mode = MMC_HS_400_ES,
2004 .widths = MMC_MODE_8BIT,
2005 },
2006#endif
3dd2626f
PF		 2007#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2008 {
2009 .mode = MMC_HS_400,
2010 .widths = MMC_MODE_8BIT,
2011 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
2012 },
2013#endif
f99c2efe 2014#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
3862b854
JJH		 2015 {
2016 .mode = MMC_HS_200,
2017 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 2018 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854 2019 },
f99c2efe 2020#endif
3862b854
JJH		 2021 {
2022 .mode = MMC_DDR_52,
2023 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
2024 },
2025 {
2026 .mode = MMC_HS_52,
2027 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
2028 },
2029 {
2030 .mode = MMC_HS,
2031 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
2032 },
2033 {
2034 .mode = MMC_LEGACY,
2035 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
2036 }
2037};
2038
2039#define for_each_mmc_mode_by_pref(caps, mwt) \
2040 for (mwt = mmc_modes_by_pref;\
2041 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
2042 mwt++) \
2043 if (caps & MMC_CAP(mwt->mode))
2044
2045static const struct ext_csd_bus_width {
2046 uint cap;
2047 bool is_ddr;
2048 uint ext_csd_bits;
2049} ext_csd_bus_width[] = {
2050 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
2051 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
2052 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
2053 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
2054 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
2055};
2056
3dd2626f
PF		 2057#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2058static int mmc_select_hs400(struct mmc *mmc)
2059{
2060 int err;
2061
2062 /* Set timing to HS200 for tuning */
b9a2a0e2 2063 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
3dd2626f
PF		 2064 if (err)
2065 return err;
2066
2067 /* configure the bus mode (host) */
2068 mmc_select_mode(mmc, MMC_HS_200);
2069 mmc_set_clock(mmc, mmc->tran_speed, false);
2070
2071 /* execute tuning if needed */
d1343522 2072 mmc->hs400_tuning = true;
3dd2626f 2073 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
d1343522 2074 mmc->hs400_tuning = false;
3dd2626f
PF		 2075 if (err) {
2076 debug("tuning failed\n");
2077 return err;
2078 }
2079
2080 /* Set back to HS */
efddda8f 2081 mmc_set_card_speed(mmc, MMC_HS_52, true);
3dd2626f 2082
d271e105
YL		 2083 err = mmc_hs400_prepare_ddr(mmc);
2084 if (err)
2085 return err;
2086
3dd2626f
PF		 2087 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2088 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
2089 if (err)
2090 return err;
2091
b9a2a0e2 2092 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
3dd2626f
PF		 2093 if (err)
2094 return err;
2095
2096 mmc_select_mode(mmc, MMC_HS_400);
2097 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2098 if (err)
2099 return err;
2100
2101 return 0;
2102}
2103#else
2104static int mmc_select_hs400(struct mmc *mmc)
2105{
2106 return -ENOTSUPP;
2107}
2108#endif
2109
44acd492
PF		 2110#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2111#if !CONFIG_IS_ENABLED(DM_MMC)
2112static int mmc_set_enhanced_strobe(struct mmc *mmc)
2113{
2114 return -ENOTSUPP;
2115}
2116#endif
2117static int mmc_select_hs400es(struct mmc *mmc)
2118{
2119 int err;
2120
2121 err = mmc_set_card_speed(mmc, MMC_HS, true);
2122 if (err)
2123 return err;
2124
2125 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2126 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2127 EXT_CSD_BUS_WIDTH_STROBE);
2128 if (err) {
2129 printf("switch to bus width for hs400 failed\n");
2130 return err;
2131 }
2132 /* TODO: driver strength */
2133 err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2134 if (err)
2135 return err;
2136
2137 mmc_select_mode(mmc, MMC_HS_400_ES);
2138 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2139 if (err)
2140 return err;
2141
2142 return mmc_set_enhanced_strobe(mmc);
2143}
2144#else
2145static int mmc_select_hs400es(struct mmc *mmc)
2146{
2147 return -ENOTSUPP;
2148}
2149#endif
2150
3862b854
JJH		 2151#define for_each_supported_width(caps, ddr, ecbv) \
2152 for (ecbv = ext_csd_bus_width;\
2153 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2154 ecbv++) \
2155 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2156
01298da3 2157static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 2158{
52ff04a2 2159 int err = 0;
3862b854
JJH		 2160 const struct mode_width_tuning *mwt;
2161 const struct ext_csd_bus_width *ecbw;
8ac8a263 2162
52d241df
JJH		 2163#ifdef DEBUG
2164 mmc_dump_capabilities("mmc", card_caps);
1da8eb59 2165 mmc_dump_capabilities("host", mmc->host_caps);
52d241df
JJH		 2166#endif
2167
f49ff799
AP		 2168 if (mmc_host_is_spi(mmc)) {
2169 mmc_set_bus_width(mmc, 1);
2170 mmc_select_mode(mmc, MMC_LEGACY);
2171 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2172 return 0;
2173 }
2174
8ac8a263 2175 /* Restrict card's capabilities by what the host can do */
1da8eb59 2176 card_caps &= mmc->host_caps;
8ac8a263
JJH		 2177
2178 /* Only version 4 of MMC supports wider bus widths */
2179 if (mmc->version < MMC_VERSION_4)
2180 return 0;
2181
dfda9d88 2182 if (!mmc->ext_csd) {
d4d64889 2183 pr_debug("No ext_csd found!\n"); /* this should enver happen */
dfda9d88
JJH		 2184 return -ENOTSUPP;
2185 }
2186
b9a2a0e2 2187#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
fb8c2e8f
YL		 2188 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
2189 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
b9a2a0e2
MV		 2190 /*
2191 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2192 * before doing anything else, since a transition from either of
2193 * the HS200/HS400 mode directly to legacy mode is not supported.
2194 */
2195 if (mmc->selected_mode == MMC_HS_200 ||
fb8c2e8f
YL		 2196 mmc->selected_mode == MMC_HS_400 ||
2197 mmc->selected_mode == MMC_HS_400_ES)
b9a2a0e2
MV		 2198 mmc_set_card_speed(mmc, MMC_HS, true);
2199 else
2200#endif
2201 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
01298da3
JJH		 2202
2203 for_each_mmc_mode_by_pref(card_caps, mwt) {
2204 for_each_supported_width(card_caps & mwt->widths,
3862b854 2205 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 2206 enum mmc_voltage old_voltage;
d4d64889
MY		 2207 pr_debug("trying mode %s width %d (at %d MHz)\n",
2208 mmc_mode_name(mwt->mode),
2209 bus_width(ecbw->cap),
2210 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 2211 old_voltage = mmc->signal_voltage;
2212 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2213 MMC_ALL_SIGNAL_VOLTAGE);
2214 if (err)
2215 continue;
2216
3862b854
JJH		 2217 /* configure the bus width (card + host) */
2218 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2219 EXT_CSD_BUS_WIDTH,
2220 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2221 if (err)
2222 goto error;
2223 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 2224
3dd2626f
PF		 2225 if (mwt->mode == MMC_HS_400) {
2226 err = mmc_select_hs400(mmc);
2227 if (err) {
2228 printf("Select HS400 failed %d\n", err);
2229 goto error;
2230 }
44acd492
PF		 2231 } else if (mwt->mode == MMC_HS_400_ES) {
2232 err = mmc_select_hs400es(mmc);
2233 if (err) {
2234 printf("Select HS400ES failed %d\n",
2235 err);
2236 goto error;
2237 }
3dd2626f
PF		 2238 } else {
2239 /* configure the bus speed (card) */
b9a2a0e2 2240 err = mmc_set_card_speed(mmc, mwt->mode, false);
3862b854
JJH		 2241 if (err)
2242 goto error;
8ac8a263 2243
3dd2626f
PF		 2244 /*
2245 * configure the bus width AND the ddr mode
2246 * (card). The host side will be taken care
2247 * of in the next step
2248 */
2249 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2250 err = mmc_switch(mmc,
2251 EXT_CSD_CMD_SET_NORMAL,
2252 EXT_CSD_BUS_WIDTH,
2253 ecbw->ext_csd_bits);
2254 if (err)
2255 goto error;
2256 }
2257
2258 /* configure the bus mode (host) */
2259 mmc_select_mode(mmc, mwt->mode);
2260 mmc_set_clock(mmc, mmc->tran_speed,
2261 MMC_CLK_ENABLE);
03de305e 2262#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
8ac8a263 2263
3dd2626f
PF		 2264 /* execute tuning if needed */
2265 if (mwt->tuning) {
2266 err = mmc_execute_tuning(mmc,
2267 mwt->tuning);
2268 if (err) {
58896458 2269 pr_debug("tuning failed : %d\n", err);
3dd2626f
PF		 2270 goto error;
2271 }
634d4849 2272 }
f99c2efe 2273#endif
3dd2626f 2274 }
634d4849 2275
3862b854
JJH		 2276 /* do a transfer to check the configuration */
2277 err = mmc_read_and_compare_ext_csd(mmc);
2278 if (!err)
2279 return 0;
2280error:
bc1e3272 2281 mmc_set_signal_voltage(mmc, old_voltage);
64dbd86b 2282 /* if an error occurred, revert to a safer bus mode */
3862b854
JJH		 2283 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2284 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2285 mmc_select_mode(mmc, MMC_LEGACY);
50dee4f3 2286 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
3862b854
JJH		 2287 mmc_set_bus_width(mmc, 1);
2288 }
8ac8a263
JJH		 2289 }
2290
99b23d45 2291 log_err("unable to select a mode: %d\n", err);
8ac8a263 2292
3862b854 2293 return -ENOTSUPP;
8ac8a263 2294}
27ba82cb
MV		 2295#else
2296static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
2297{
2298 return 0;
2299};
2300
2301static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2302{
2303 return 0;
2304};
62d77cea
MV		 2305#endif
2306
2307#if CONFIG_IS_ENABLED(MMC_TINY)
2308DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2309#endif
8ac8a263 2310
dfda9d88 2311static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 2312{
2313 int err, i;
2314 u64 capacity;
2315 bool has_parts = false;
2316 bool part_completed;
58a6fb7b
JJH		 2317 static const u32 mmc_versions[] = {
2318 MMC_VERSION_4,
2319 MMC_VERSION_4_1,
2320 MMC_VERSION_4_2,
2321 MMC_VERSION_4_3,
ace1bed3 2322 MMC_VERSION_4_4,
58a6fb7b
JJH		 2323 MMC_VERSION_4_41,
2324 MMC_VERSION_4_5,
2325 MMC_VERSION_5_0,
2326 MMC_VERSION_5_1
2327 };
2328
62d77cea
MV		 2329#if CONFIG_IS_ENABLED(MMC_TINY)
2330 u8 *ext_csd = ext_csd_bkup;
2331
2332 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2333 return 0;
2334
2335 if (!mmc->ext_csd)
229d689e 2336 memset(ext_csd_bkup, 0, MMC_MAX_BLOCK_LEN);
62d77cea
MV		 2337
2338 err = mmc_send_ext_csd(mmc, ext_csd);
2339 if (err)
2340 goto error;
2341
2342 /* store the ext csd for future reference */
2343 if (!mmc->ext_csd)
2344 mmc->ext_csd = ext_csd;
2345#else
f7d5dffc 2346 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
c744b6f6
JJH		 2347
2348 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2349 return 0;
2350
2351 /* check ext_csd version and capacity */
2352 err = mmc_send_ext_csd(mmc, ext_csd);
2353 if (err)
f7d5dffc
JJH		 2354 goto error;
2355
2356 /* store the ext csd for future reference */
2357 if (!mmc->ext_csd)
2358 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2359 if (!mmc->ext_csd)
2360 return -ENOMEM;
2361 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
62d77cea 2362#endif
76584e33 2363 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
58a6fb7b
JJH		 2364 return -EINVAL;
2365
2366 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2367
2368 if (mmc->version >= MMC_VERSION_4_2) {
c744b6f6
JJH		 2369 /*
2370 * According to the JEDEC Standard, the value of
2371 * ext_csd's capacity is valid if the value is more
2372 * than 2GB
2373 */
2374 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2375 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2376 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2377 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2378 capacity *= MMC_MAX_BLOCK_LEN;
2379 if ((capacity >> 20) > 2 * 1024)
2380 mmc->capacity_user = capacity;
2381 }
2382
39320c53
JJH		 2383 if (mmc->version >= MMC_VERSION_4_5)
2384 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2385
c744b6f6
JJH		 2386 /* The partition data may be non-zero but it is only
2387 * effective if PARTITION_SETTING_COMPLETED is set in
2388 * EXT_CSD, so ignore any data if this bit is not set,
2389 * except for enabling the high-capacity group size
2390 * definition (see below).
2391 */
2392 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2393 EXT_CSD_PARTITION_SETTING_COMPLETED);
2394
513e00b6
JJH		 2395 mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2396 /* Some eMMC set the value too low so set a minimum */
2397 if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2398 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2399
c744b6f6
JJH		 2400 /* store the partition info of emmc */
2401 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2402 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2403 ext_csd[EXT_CSD_BOOT_MULT])
2404 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2405 if (part_completed &&
2406 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2407 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2408
2409 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2410
2411 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2412
2413 for (i = 0; i < 4; i++) {
2414 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2415 uint mult = (ext_csd[idx + 2] << 16) +
2416 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2417 if (mult)
2418 has_parts = true;
2419 if (!part_completed)
2420 continue;
2421 mmc->capacity_gp[i] = mult;
2422 mmc->capacity_gp[i] *=
2423 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2424 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2425 mmc->capacity_gp[i] <<= 19;
2426 }
2427
371dc068 2428#ifndef CONFIG_XPL_BUILD
c744b6f6
JJH		 2429 if (part_completed) {
2430 mmc->enh_user_size =
2431 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2432 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2433 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2434 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2435 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2436 mmc->enh_user_size <<= 19;
2437 mmc->enh_user_start =
2438 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2439 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2440 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2441 ext_csd[EXT_CSD_ENH_START_ADDR];
2442 if (mmc->high_capacity)
2443 mmc->enh_user_start <<= 9;
2444 }
173c06df 2445#endif
c744b6f6
JJH		 2446
2447 /*
2448 * Host needs to enable ERASE_GRP_DEF bit if device is
2449 * partitioned. This bit will be lost every time after a reset
2450 * or power off. This will affect erase size.
2451 */
2452 if (part_completed)
2453 has_parts = true;
2454 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2455 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2456 has_parts = true;
2457 if (has_parts) {
2458 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2459 EXT_CSD_ERASE_GROUP_DEF, 1);
2460
2461 if (err)
f7d5dffc 2462 goto error;
c744b6f6
JJH		 2463
2464 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2465 }
2466
2467 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
e6fa5a54 2468#if CONFIG_IS_ENABLED(MMC_WRITE)
c744b6f6
JJH		 2469 /* Read out group size from ext_csd */
2470 mmc->erase_grp_size =
2471 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
e6fa5a54 2472#endif
c744b6f6
JJH		 2473 /*
2474 * if high capacity and partition setting completed
2475 * SEC_COUNT is valid even if it is smaller than 2 GiB
2476 * JEDEC Standard JESD84-B45, 6.2.4
2477 */
2478 if (mmc->high_capacity && part_completed) {
2479 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2480 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2481 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2482 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2483 capacity *= MMC_MAX_BLOCK_LEN;
2484 mmc->capacity_user = capacity;
2485 }
e6fa5a54
JJH		 2486 }
2487#if CONFIG_IS_ENABLED(MMC_WRITE)
2488 else {
c744b6f6
JJH		 2489 /* Calculate the group size from the csd value. */
2490 int erase_gsz, erase_gmul;
2491
2492 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2493 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2494 mmc->erase_grp_size = (erase_gsz + 1)
2495 * (erase_gmul + 1);
2496 }
e6fa5a54 2497#endif
b7a6e2c9 2498#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
c744b6f6
JJH		 2499 mmc->hc_wp_grp_size = 1024
2500 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2501 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
b7a6e2c9 2502#endif
c744b6f6
JJH		 2503
2504 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2505
eeb739a6
LP		 2506 mmc->can_trim =
2507 !!(ext_csd[EXT_CSD_SEC_FEATURE] & EXT_CSD_SEC_FEATURE_TRIM_EN);
2508
c744b6f6 2509 return 0;
f7d5dffc
JJH		 2510error:
2511 if (mmc->ext_csd) {
62d77cea 2512#if !CONFIG_IS_ENABLED(MMC_TINY)
f7d5dffc 2513 free(mmc->ext_csd);
62d77cea 2514#endif
f7d5dffc
JJH		 2515 mmc->ext_csd = NULL;
2516 }
2517 return err;
c744b6f6
JJH		 2518}
2519
fdbb873e 2520static int mmc_startup(struct mmc *mmc)
272cc70b 2521{
f866a46d 2522 int err, i;
272cc70b 2523 uint mult, freq;
c744b6f6 2524 u64 cmult, csize;
272cc70b 2525 struct mmc_cmd cmd;
c40fdca6 2526 struct blk_desc *bdesc;
272cc70b 2527
d52ebf10
TC		 2528#ifdef CONFIG_MMC_SPI_CRC_ON
2529 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2530 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2531 cmd.resp_type = MMC_RSP_R1;
2532 cmd.cmdarg = 1;
d52ebf10 2533 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2534 if (err)
2535 return err;
2536 }
2537#endif
2538
272cc70b 2539 /* Put the Card in Identify Mode */
d52ebf10
TC		 2540 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2541 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2542 cmd.resp_type = MMC_RSP_R2;
2543 cmd.cmdarg = 0;
272cc70b 2544
da129170 2545 err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4);
272cc70b
AF		 2546 if (err)
2547 return err;
2548
2549 memcpy(mmc->cid, cmd.response, 16);
2550
2551 /*
2552 * For MMC cards, set the Relative Address.
2553 * For SD cards, get the Relatvie Address.
2554 * This also puts the cards into Standby State
2555 */
d52ebf10
TC		 2556 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2557 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2558 cmd.cmdarg = mmc->rca << 16;
2559 cmd.resp_type = MMC_RSP_R6;
272cc70b 2560
d52ebf10 2561 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2562
d52ebf10
TC		 2563 if (err)
2564 return err;
272cc70b 2565
d52ebf10
TC		 2566 if (IS_SD(mmc))
2567 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2568 }
272cc70b
AF		 2569
2570 /* Get the Card-Specific Data */
2571 cmd.cmdidx = MMC_CMD_SEND_CSD;
2572 cmd.resp_type = MMC_RSP_R2;
2573 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2574
2575 err = mmc_send_cmd(mmc, &cmd, NULL);
2576
2577 if (err)
2578 return err;
2579
998be3dd
RV		 2580 mmc->csd[0] = cmd.response[0];
2581 mmc->csd[1] = cmd.response[1];
2582 mmc->csd[2] = cmd.response[2];
2583 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2584
2585 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2586 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2587
2588 switch (version) {
53e8e40b
BM		 2589 case 0:
2590 mmc->version = MMC_VERSION_1_2;
2591 break;
2592 case 1:
2593 mmc->version = MMC_VERSION_1_4;
2594 break;
2595 case 2:
2596 mmc->version = MMC_VERSION_2_2;
2597 break;
2598 case 3:
2599 mmc->version = MMC_VERSION_3;
2600 break;
2601 case 4:
2602 mmc->version = MMC_VERSION_4;
2603 break;
2604 default:
2605 mmc->version = MMC_VERSION_1_2;
2606 break;
272cc70b
AF		 2607 }
2608 }
2609
2610 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2611 freq = fbase[(cmd.response[0] & 0x7)];
2612 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2613
35f9e196 2614 mmc->legacy_speed = freq * mult;
f9a86fb1
HS		 2615 if (!mmc->legacy_speed)
2616 log_debug("TRAN_SPEED: reserved value");
35f9e196 2617 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2618
ab71188c 2619 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2620 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
e6fa5a54 2621#if CONFIG_IS_ENABLED(MMC_WRITE)
272cc70b
AF		 2622
2623 if (IS_SD(mmc))
2624 mmc->write_bl_len = mmc->read_bl_len;
2625 else
998be3dd 2626 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
e6fa5a54 2627#endif
272cc70b
AF		 2628
2629 if (mmc->high_capacity) {
2630 csize = (mmc->csd[1] & 0x3f) << 16
2631 | (mmc->csd[2] & 0xffff0000) >> 16;
2632 cmult = 8;
2633 } else {
2634 csize = (mmc->csd[1] & 0x3ff) << 2
2635 | (mmc->csd[2] & 0xc0000000) >> 30;
2636 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2637 }
2638
f866a46d
SW		 2639 mmc->capacity_user = (csize + 1) << (cmult + 2);
2640 mmc->capacity_user *= mmc->read_bl_len;
2641 mmc->capacity_boot = 0;
2642 mmc->capacity_rpmb = 0;
2643 for (i = 0; i < 4; i++)
2644 mmc->capacity_gp[i] = 0;
272cc70b 2645
8bfa195e
SG		 2646 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2647 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2648
e6fa5a54 2649#if CONFIG_IS_ENABLED(MMC_WRITE)
8bfa195e
SG		 2650 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2651 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2652#endif
272cc70b 2653
ab71188c
MN		 2654 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2655 cmd.cmdidx = MMC_CMD_SET_DSR;
2656 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2657 cmd.resp_type = MMC_RSP_NONE;
2658 if (mmc_send_cmd(mmc, &cmd, NULL))
d8e3d420 2659 pr_warn("MMC: SET_DSR failed\n");
ab71188c
MN		 2660 }
2661
272cc70b 2662 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2663 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2664 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2665 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2666 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2667 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2668
d52ebf10
TC		 2669 if (err)
2670 return err;
2671 }
272cc70b 2672
e6f99a56
LW		 2673 /*
2674 * For SD, its erase group is always one sector
2675 */
e6fa5a54 2676#if CONFIG_IS_ENABLED(MMC_WRITE)
e6f99a56 2677 mmc->erase_grp_size = 1;
e6fa5a54 2678#endif
bc897b1d 2679 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2680
dfda9d88 2681 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2682 if (err)
2683 return err;
d23e2c09 2684
c40fdca6 2685 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2686 if (err)
2687 return err;
2688
62d77cea
MV		 2689#if CONFIG_IS_ENABLED(MMC_TINY)
2690 mmc_set_clock(mmc, mmc->legacy_speed, false);
e8d5dde4 2691 mmc_select_mode(mmc, MMC_LEGACY);
62d77cea
MV		 2692 mmc_set_bus_width(mmc, 1);
2693#else
01298da3
JJH		 2694 if (IS_SD(mmc)) {
2695 err = sd_get_capabilities(mmc);
2696 if (err)
2697 return err;
2698 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2699 } else {
2700 err = mmc_get_capabilities(mmc);
2701 if (err)
2702 return err;
8adf50ef 2703 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
01298da3 2704 }
62d77cea 2705#endif
272cc70b
AF		 2706 if (err)
2707 return err;
2708
01298da3 2709 mmc->best_mode = mmc->selected_mode;
ad5fd922 2710
5af8f45c
AG		 2711 /* Fix the block length for DDR mode */
2712 if (mmc->ddr_mode) {
2713 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2714#if CONFIG_IS_ENABLED(MMC_WRITE)
5af8f45c 2715 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2716#endif
5af8f45c
AG		 2717 }
2718
272cc70b 2719 /* fill in device description */
c40fdca6
SG		 2720 bdesc = mmc_get_blk_desc(mmc);
2721 bdesc->lun = 0;
2722 bdesc->hwpart = 0;
2723 bdesc->type = 0;
2724 bdesc->blksz = mmc->read_bl_len;
2725 bdesc->log2blksz = LOG2(bdesc->blksz);
2726 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
371dc068 2727#if !defined(CONFIG_XPL_BUILD) || \
fc011f64 2728 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
27084c03 2729 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
c40fdca6 2730 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2731 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2732 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2733 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2734 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2735 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2736 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2737 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2738 (mmc->cid[2] >> 16) & 0xf);
56196826 2739#else
c40fdca6
SG		 2740 bdesc->vendor[0] = 0;
2741 bdesc->product[0] = 0;
2742 bdesc->revision[0] = 0;
56196826 2743#endif
272cc70b 2744
371dc068 2745#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
eef05fd3
AP		 2746 part_init(bdesc);
2747#endif
2748
272cc70b
AF		 2749 return 0;
2750}
2751
fdbb873e 2752static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2753{
2754 struct mmc_cmd cmd;
2755 int err;
2756
2757 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2758 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2759 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2760 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2761
2762 err = mmc_send_cmd(mmc, &cmd, NULL);
2763
2764 if (err)
2765 return err;
2766
998be3dd 2767 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2768 return -EOPNOTSUPP;
272cc70b
AF		 2769 else
2770 mmc->version = SD_VERSION_2;
2771
2772 return 0;
2773}
2774
c4d660d4 2775#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2776/* board-specific MMC power initializations. */
2777__weak void board_mmc_power_init(void)
2778{
2779}
05cbeb7c 2780#endif
95de9ab2 2781
2051aefe
PF		 2782static int mmc_power_init(struct mmc *mmc)
2783{
c4d660d4 2784#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2785#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2786 int ret;
2787
2788 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2789 &mmc->vmmc_supply);
2790 if (ret)
d4d64889 2791 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2792
06ec045f
JJH		 2793 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2794 &mmc->vqmmc_supply);
2795 if (ret)
d4d64889 2796 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2797#endif
2798#else /* !CONFIG_DM_MMC */
2799 /*
2800 * Driver model should use a regulator, as above, rather than calling
2801 * out to board code.
2802 */
2803 board_mmc_power_init();
2804#endif
2805 return 0;
2806}
2807
2808/*
2809 * put the host in the initial state:
2810 * - turn on Vdd (card power supply)
2811 * - configure the bus width and clock to minimal values
2812 */
2813static void mmc_set_initial_state(struct mmc *mmc)
2814{
2815 int err;
2816
2817 /* First try to set 3.3V. If it fails set to 1.8V */
2818 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2819 if (err != 0)
2820 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2821 if (err != 0)
d8e3d420 2822 pr_warn("mmc: failed to set signal voltage\n");
fb7c3beb
KVA		 2823
2824 mmc_select_mode(mmc, MMC_LEGACY);
2825 mmc_set_bus_width(mmc, 1);
65117182 2826 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
fb7c3beb 2827}
06ec045f 2828
fb7c3beb
KVA		 2829static int mmc_power_on(struct mmc *mmc)
2830{
2831#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2832 if (mmc->vmmc_supply) {
9a2e9cc6
JK		 2833 int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
2834 true);
fb7c3beb 2835
9a2e9cc6 2836 if (ret && ret != -ENOSYS) {
58896458 2837 printf("Error enabling VMMC supply : %d\n", ret);
06ec045f
JJH		 2838 return ret;
2839 }
2051aefe 2840 }
05cbeb7c 2841#endif
fb7c3beb
KVA		 2842 return 0;
2843}
2844
2845static int mmc_power_off(struct mmc *mmc)
2846{
65117182 2847 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
fb7c3beb
KVA		 2848#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2849 if (mmc->vmmc_supply) {
9a2e9cc6
JK		 2850 int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
2851 false);
fb7c3beb 2852
9a2e9cc6 2853 if (ret && ret != -ENOSYS) {
58896458 2854 pr_debug("Error disabling VMMC supply : %d\n", ret);
fb7c3beb
KVA		 2855 return ret;
2856 }
2857 }
2051aefe
PF		 2858#endif
2859 return 0;
2860}
2861
fb7c3beb
KVA		 2862static int mmc_power_cycle(struct mmc *mmc)
2863{
2864 int ret;
2865
2866 ret = mmc_power_off(mmc);
2867 if (ret)
2868 return ret;
3602a56a
YG		 2869
2870 ret = mmc_host_power_cycle(mmc);
2871 if (ret)
2872 return ret;
2873
fb7c3beb
KVA		 2874 /*
2875 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2876 * to be on the safer side.
2877 */
2878 udelay(2000);
2879 return mmc_power_on(mmc);
2880}
2881
a4c577f9 2882int mmc_get_op_cond(struct mmc *mmc, bool quiet)
272cc70b 2883{
c10b85d6 2884 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2885 int err;
272cc70b 2886
bc897b1d
LW		 2887 if (mmc->has_init)
2888 return 0;
2889
2051aefe
PF		 2890 err = mmc_power_init(mmc);
2891 if (err)
2892 return err;
95de9ab2 2893
83dc4227
KVA		 2894#ifdef CONFIG_MMC_QUIRKS
2895 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
d4a5fa31
JJ		 2896 MMC_QUIRK_RETRY_SEND_CID |
2897 MMC_QUIRK_RETRY_APP_CMD;
83dc4227
KVA		 2898#endif
2899
04a2ea24
JJH		 2900 err = mmc_power_cycle(mmc);
2901 if (err) {
2902 /*
2903 * if power cycling is not supported, we should not try
2904 * to use the UHS modes, because we wouldn't be able to
2905 * recover from an error during the UHS initialization.
2906 */
d4d64889 2907 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
04a2ea24
JJH		 2908 uhs_en = false;
2909 mmc->host_caps &= ~UHS_CAPS;
2910 err = mmc_power_on(mmc);
2911 }
fb7c3beb
KVA		 2912 if (err)
2913 return err;
2914
e7881d85 2915#if CONFIG_IS_ENABLED(DM_MMC)
390f9bdd
YL		 2916 /*
2917 * Re-initialization is needed to clear old configuration for
2918 * mmc rescan.
2919 */
2920 err = mmc_reinit(mmc);
8ca51e51 2921#else
ab769f22 2922 /* made sure it's not NULL earlier */
93bfd616 2923 err = mmc->cfg->ops->init(mmc);
390f9bdd 2924#endif
272cc70b
AF		 2925 if (err)
2926 return err;
786e8f81 2927 mmc->ddr_mode = 0;
aff5d3c8 2928
c10b85d6 2929retry:
fb7c3beb 2930 mmc_set_initial_state(mmc);
318a7a57 2931
272cc70b
AF		 2932 /* Reset the Card */
2933 err = mmc_go_idle(mmc);
2934
2935 if (err)
2936 return err;
2937
f5624b10 2938 /* The internal partition reset to user partition(0) at every CMD0 */
c40fdca6 2939 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2940
272cc70b 2941 /* Test for SD version 2 */
afd5932b 2942 err = mmc_send_if_cond(mmc);
272cc70b 2943
272cc70b 2944 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2945 err = sd_send_op_cond(mmc, uhs_en);
2946 if (err && uhs_en) {
2947 uhs_en = false;
2948 mmc_power_cycle(mmc);
2949 goto retry;
2950 }
272cc70b
AF		 2951
2952 /* If the command timed out, we check for an MMC card */
915ffa52 2953 if (err == -ETIMEDOUT) {
272cc70b
AF		 2954 err = mmc_send_op_cond(mmc);
2955
bd47c135 2956 if (err) {
371dc068 2957#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
a4c577f9 2958 if (!quiet)
99b23d45
SG		 2959 log_err("Card did not respond to voltage select! : %d\n",
2960 err);
56196826 2961#endif
915ffa52 2962 return -EOPNOTSUPP;
272cc70b
AF		 2963 }
2964 }
2965
6c09eba5
JN		 2966 return err;
2967}
2968
2969int mmc_start_init(struct mmc *mmc)
2970{
2971 bool no_card;
2972 int err = 0;
2973
2974 /*
2975 * all hosts are capable of 1 bit bus-width and able to use the legacy
2976 * timings.
2977 */
e8d5dde4 2978 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
19f7a34a
AG		 2979 MMC_MODE_1BIT;
2980
2981 if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) {
2982 if (mmc->user_speed_mode != MMC_MODES_END) {
2983 int i;
2984 /* set host caps */
2985 if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) {
2986 /* Remove all existing speed capabilities */
2987 for (i = MMC_LEGACY; i < MMC_MODES_END; i++)
2988 mmc->host_caps &= ~MMC_CAP(i);
2989 mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode)
2990 | MMC_CAP(MMC_LEGACY) |
2991 MMC_MODE_1BIT);
2992 } else {
99b23d45 2993 log_err("bus_mode requested is not supported\n");
19f7a34a
AG		 2994 return -EINVAL;
2995 }
2996 }
2997 }
32860bdb
FA		 2998#if CONFIG_IS_ENABLED(DM_MMC)
2999 mmc_deferred_probe(mmc);
3000#endif
6c09eba5 3001#if !defined(CONFIG_MMC_BROKEN_CD)
6c09eba5
JN		 3002 no_card = mmc_getcd(mmc) == 0;
3003#else
3004 no_card = 0;
3005#endif
3006#if !CONFIG_IS_ENABLED(DM_MMC)
fea3939d 3007 /* we pretend there's no card when init is NULL */
6c09eba5
JN		 3008 no_card = no_card || (mmc->cfg->ops->init == NULL);
3009#endif
3010 if (no_card) {
3011 mmc->has_init = 0;
371dc068 3012#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
99b23d45 3013 log_err("MMC: no card present\n");
6c09eba5
JN		 3014#endif
3015 return -ENOMEDIUM;
3016 }
3017
a4c577f9 3018 err = mmc_get_op_cond(mmc, false);
6c09eba5 3019
bd47c135 3020 if (!err)
e9550449
CLC		 3021 mmc->init_in_progress = 1;
3022
3023 return err;
3024}
3025
3026static int mmc_complete_init(struct mmc *mmc)
3027{
3028 int err = 0;
3029
bd47c135 3030 mmc->init_in_progress = 0;
e9550449
CLC		 3031 if (mmc->op_cond_pending)
3032 err = mmc_complete_op_cond(mmc);
3033
3034 if (!err)
3035 err = mmc_startup(mmc);
bc897b1d
LW		 3036 if (err)
3037 mmc->has_init = 0;
3038 else
3039 mmc->has_init = 1;
e9550449
CLC		 3040 return err;
3041}
3042
90cc07fd
MV		 3043static void __maybe_unused mmc_cyclic_cd_poll(struct cyclic_info *c)
3044{
3045 struct mmc *m = CONFIG_IS_ENABLED(CYCLIC, (container_of(c, struct mmc, cyclic)), (NULL));
3046
3047 if (!m->has_init)
3048 return;
3049
3050 if (mmc_getcd(m))
3051 return;
3052
3053 mmc_deinit(m);
3054 m->has_init = 0;
3055}
3056
e9550449
CLC		 3057int mmc_init(struct mmc *mmc)
3058{
bd47c135 3059 int err = 0;
36332b6e 3060 __maybe_unused ulong start;
c4d660d4 3061#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 3062 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 3063
33fb211d
SG		 3064 upriv->mmc = mmc;
3065#endif
e9550449
CLC		 3066 if (mmc->has_init)
3067 return 0;
d803fea5
MZ		 3068
3069 start = get_timer(0);
3070
e9550449
CLC		 3071 if (!mmc->init_in_progress)
3072 err = mmc_start_init(mmc);
3073
bd47c135 3074 if (!err)
e9550449 3075 err = mmc_complete_init(mmc);
919b4858 3076 if (err)
d4d64889 3077 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
919b4858 3078
90cc07fd
MV		 3079 if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic.func), (NULL))) {
3080 /* Register cyclic function for card detect polling */
3081 CONFIG_IS_ENABLED(CYCLIC, (cyclic_register(&mmc->cyclic,
3082 mmc_cyclic_cd_poll,
3083 100 * 1000,
3084 mmc->cfg->name)));
3085 }
3086
bc897b1d 3087 return err;
272cc70b
AF		 3088}
3089
fceea992
MV		 3090int mmc_deinit(struct mmc *mmc)
3091{
3092 u32 caps_filtered;
3093
90cc07fd
MV		 3094 if (CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic.func), (NULL)))
3095 CONFIG_IS_ENABLED(CYCLIC, (cyclic_unregister(&mmc->cyclic)));
3096
27ba82cb
MV		 3097 if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) &&
3098 !CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) &&
3099 !CONFIG_IS_ENABLED(MMC_HS400_SUPPORT))
3100 return 0;
3101
fceea992
MV		 3102 if (!mmc->has_init)
3103 return 0;
3104
3105 if (IS_SD(mmc)) {
3106 caps_filtered = mmc->card_caps &
3107 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
3108 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
3109 MMC_CAP(UHS_SDR104));
3110
3111 return sd_select_mode_and_width(mmc, caps_filtered);
3112 } else {
3113 caps_filtered = mmc->card_caps &
fb8c2e8f 3114 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES));
fceea992
MV		 3115
3116 return mmc_select_mode_and_width(mmc, caps_filtered);
3117 }
3118}
fceea992 3119
ab71188c
MN		 3120int mmc_set_dsr(struct mmc *mmc, u16 val)
3121{
3122 mmc->dsr = val;
3123 return 0;
3124}
3125
cee9ab7c 3126/* CPU-specific MMC initializations */
b75d8dc5 3127__weak int cpu_mmc_init(struct bd_info *bis)
272cc70b
AF		 3128{
3129 return -1;
3130}
3131
cee9ab7c 3132/* board-specific MMC initializations. */
b75d8dc5 3133__weak int board_mmc_init(struct bd_info *bis)
cee9ab7c
JH		 3134{
3135 return -1;
3136}
272cc70b 3137
e9550449
CLC		 3138void mmc_set_preinit(struct mmc *mmc, int preinit)
3139{
3140 mmc->preinit = preinit;
3141}
3142
8a856db2 3143#if CONFIG_IS_ENABLED(DM_MMC)
b75d8dc5 3144static int mmc_probe(struct bd_info *bis)
8e3332e2 3145{
4a1db6d8 3146 int ret, i;
8e3332e2 3147 struct uclass *uc;
4a1db6d8 3148 struct udevice *dev;
8e3332e2
SS		 3149
3150 ret = uclass_get(UCLASS_MMC, &uc);
3151 if (ret)
3152 return ret;
3153
4a1db6d8
SG		 3154 /*
3155 * Try to add them in sequence order. Really with driver model we
3156 * should allow holes, but the current MMC list does not allow that.
3157 * So if we request 0, 1, 3 we will get 0, 1, 2.
3158 */
3159 for (i = 0; ; i++) {
3160 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
3161 if (ret == -ENODEV)
3162 break;
3163 }
3164 uclass_foreach_dev(dev, uc) {
3165 ret = device_probe(dev);
8e3332e2 3166 if (ret)
99b23d45 3167 log_err("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 3168 }
3169
3170 return 0;
3171}
3172#else
b75d8dc5 3173static int mmc_probe(struct bd_info *bis)
8e3332e2
SS		 3174{
3175 if (board_mmc_init(bis) < 0)
3176 cpu_mmc_init(bis);
3177
3178 return 0;
3179}
3180#endif
e9550449 3181
b75d8dc5 3182int mmc_initialize(struct bd_info *bis)
272cc70b 3183{
1b26bab1 3184 static int initialized = 0;
8e3332e2 3185 int ret;
1b26bab1
DK		 3186 if (initialized) /* Avoid initializing mmc multiple times */
3187 return 0;
3188 initialized = 1;
3189
c4d660d4 3190#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 3191#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 3192 mmc_list_init();
b5b838f1 3193#endif
c40fdca6 3194#endif
8e3332e2
SS		 3195 ret = mmc_probe(bis);
3196 if (ret)
3197 return ret;
272cc70b 3198
371dc068 3199#ifndef CONFIG_XPL_BUILD
272cc70b 3200 print_mmc_devices(',');
bb0dc108 3201#endif
272cc70b 3202
c40fdca6 3203 mmc_do_preinit();
272cc70b
AF		 3204 return 0;
3205}
cd3d4880 3206
80f02019
LV		 3207#if CONFIG_IS_ENABLED(DM_MMC)
3208int mmc_init_device(int num)
3209{
3210 struct udevice *dev;
3211 struct mmc *m;
3212 int ret;
3213
2153a08a
AG		 3214 if (uclass_get_device_by_seq(UCLASS_MMC, num, &dev)) {
3215 ret = uclass_get_device(UCLASS_MMC, num, &dev);
3216 if (ret)
e771a9db 3217 return log_msg_ret("ini", ret);
2153a08a 3218 }
80f02019
LV		 3219
3220 m = mmc_get_mmc_dev(dev);
3221 if (!m)
3222 return 0;
337af54a
VYA		 3223
3224 /* Initialising user set speed mode */
3225 m->user_speed_mode = MMC_MODES_END;
3226
80f02019
LV		 3227 if (m->preinit)
3228 mmc_start_init(m);
3229
3230 return 0;
3231}
3232#endif
3233
cd3d4880 3234#ifdef CONFIG_CMD_BKOPS_ENABLE
cf1f7355 3235int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable)
cd3d4880
TM		 3236{
3237 int err;
cf1f7355 3238 u32 bit = autobkops ? BIT(1) : BIT(0);
cd3d4880
TM		 3239 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3240
3241 err = mmc_send_ext_csd(mmc, ext_csd);
3242 if (err) {
3243 puts("Could not get ext_csd register values\n");
3244 return err;
3245 }
3246
3247 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3248 puts("Background operations not supported on device\n");
3249 return -EMEDIUMTYPE;
3250 }
3251
cf1f7355 3252 if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) {
cd3d4880
TM		 3253 puts("Background operations already enabled\n");
3254 return 0;
3255 }
3256
cf1f7355
MV		 3257 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN,
3258 enable ? bit : 0);
cd3d4880 3259 if (err) {
cf1f7355
MV		 3260 printf("Failed to %sable manual background operations\n",
3261 enable ? "en" : "dis");
cd3d4880
TM		 3262 return err;
3263 }
3264
cf1f7355
MV		 3265 printf("%sabled %s background operations\n",
3266 enable ? "En" : "Dis", autobkops ? "auto" : "manual");
cd3d4880
TM		 3267
3268 return 0;
3269}
3270#endif
4dee3f78
DW		 3271
3272__weak int mmc_get_env_dev(void)
3273{
3274#ifdef CONFIG_SYS_MMC_ENV_DEV
3275 return CONFIG_SYS_MMC_ENV_DEV;
3276#else
3277 return 0;
3278#endif
3279}
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