[J-u-boot.git] / drivers / mmc / meson_gx_mmc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2016 Carlo Caione <[email protected]>
 */

#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
#include <pwrseq.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include <linux/log2.h>
#include "meson_gx_mmc.h"

bool meson_gx_mmc_is_compatible(struct udevice *dev,
				enum meson_gx_mmc_compatible family)
{
	enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);

	return compat == family;
}

static inline void *get_regbase(const struct mmc *mmc)
{
	struct meson_mmc_plat *pdata = mmc->priv;

	return pdata->regbase;
}

static inline uint32_t meson_read(struct mmc *mmc, int offset)
{
	return readl(get_regbase(mmc) + offset);
}

static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
{
	writel(val, get_regbase(mmc) + offset);
}

static void meson_mmc_config_clock(struct mmc *mmc)
{
	uint32_t meson_mmc_clk = 0;
	unsigned int clk, clk_src, clk_div;

	if (!mmc->clock)
		return;

	/* TOFIX This should use the proper clock taken from DT */

	/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
	if (mmc->clock > 16000000) {
		clk = SD_EMMC_CLKSRC_DIV2;
		clk_src = CLK_SRC_DIV2;
	} else {
		clk = SD_EMMC_CLKSRC_24M;
		clk_src = CLK_SRC_24M;
	}
	clk_div = DIV_ROUND_UP(clk, mmc->clock);

	/*
	 * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
	 * If CLK_CO_PHASE_270 is used, it's more stable than other.
	 * Other SoCs use CLK_CO_PHASE_180 by default.
	 * It needs to find what is a proper value about each SoCs.
	 */
	if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
		meson_mmc_clk |= CLK_CO_PHASE_270;
	else
		meson_mmc_clk |= CLK_CO_PHASE_180;

	/* 180 phase tx clock */
	meson_mmc_clk |= CLK_TX_PHASE_000;

	/* clock settings */
	meson_mmc_clk |= clk_src;
	meson_mmc_clk |= clk_div;

	meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
}

static int meson_dm_mmc_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	uint32_t meson_mmc_cfg;

	meson_mmc_config_clock(mmc);

	meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);

	meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
	if (mmc->bus_width == 1)
		meson_mmc_cfg |= CFG_BUS_WIDTH_1;
	else if (mmc->bus_width == 4)
		meson_mmc_cfg |= CFG_BUS_WIDTH_4;
	else if (mmc->bus_width == 8)
		meson_mmc_cfg |= CFG_BUS_WIDTH_8;
	else
		return -EINVAL;

	/* 512 bytes block length */
	meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
	meson_mmc_cfg |= CFG_BL_LEN_512;

	/* Response timeout 256 clk */
	meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
	meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;

	/* Command-command gap 16 clk */
	meson_mmc_cfg &= ~CFG_RC_CC_MASK;
	meson_mmc_cfg |= CFG_RC_CC_16;

	meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);

	return 0;
}

static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
				struct mmc_cmd *cmd)
{
	uint32_t meson_mmc_cmd = 0, cfg;

	meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136)
			meson_mmc_cmd |= CMD_CFG_RESP_128;

		if (cmd->resp_type & MMC_RSP_BUSY)
			meson_mmc_cmd |= CMD_CFG_R1B;

		if (!(cmd->resp_type & MMC_RSP_CRC))
			meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
	} else {
		meson_mmc_cmd |= CMD_CFG_NO_RESP;
	}

	if (data) {
		cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
		cfg &= ~CFG_BL_LEN_MASK;
		cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
		meson_write(mmc, cfg, MESON_SD_EMMC_CFG);

		if (data->flags == MMC_DATA_WRITE)
			meson_mmc_cmd |= CMD_CFG_DATA_WR;

		meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
				 data->blocks;
	}

	meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
			 CMD_CFG_END_OF_CHAIN;

	meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
}

static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
{
	struct meson_mmc_plat *pdata = mmc->priv;
	unsigned int data_size;
	uint32_t data_addr = 0;

	if (data) {
		data_size = data->blocks * data->blocksize;

		if (data->flags == MMC_DATA_READ) {
			data_addr = (ulong) data->dest;
			invalidate_dcache_range(data_addr,
						data_addr + data_size);
		} else {
			pdata->w_buf = calloc(data_size, sizeof(char));
			data_addr = (ulong) pdata->w_buf;
			memcpy(pdata->w_buf, data->src, data_size);
			flush_dcache_range(data_addr, data_addr + data_size);
		}
	}

	meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
}

static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
{
	if (cmd->resp_type & MMC_RSP_136) {
		cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
		cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
		cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
		cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
	} else {
		cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
	}
}

static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
				 struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	struct meson_mmc_plat *pdata = mmc->priv;
	uint32_t status;
	ulong start;
	int ret = 0;

	/* max block size supported by chip is 512 byte */
	if (data && data->blocksize > 512)
		return -EINVAL;

	meson_mmc_setup_cmd(mmc, data, cmd);
	meson_mmc_setup_addr(mmc, data);

	meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);

	/* use 10s timeout */
	start = get_timer(0);
	do {
		status = meson_read(mmc, MESON_SD_EMMC_STATUS);
	} while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);

	if (!(status & STATUS_END_OF_CHAIN))
		ret = -ETIMEDOUT;
	else if (status & STATUS_RESP_TIMEOUT)
		ret = -ETIMEDOUT;
	else if (status & STATUS_ERR_MASK)
		ret = -EIO;

	meson_mmc_read_response(mmc, cmd);

	if (data && data->flags == MMC_DATA_WRITE)
		free(pdata->w_buf);

	/* reset status bits */
	meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);

	return ret;
}

static const struct dm_mmc_ops meson_dm_mmc_ops = {
	.send_cmd = meson_dm_mmc_send_cmd,
	.set_ios = meson_dm_mmc_set_ios,
};

static int meson_mmc_of_to_plat(struct udevice *dev)
{
	struct meson_mmc_plat *pdata = dev_get_plat(dev);
	fdt_addr_t addr;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	pdata->regbase = (void *)addr;

	return 0;
}

static int meson_mmc_probe(struct udevice *dev)
{
	struct meson_mmc_plat *pdata = dev_get_plat(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct mmc *mmc = &pdata->mmc;
	struct mmc_config *cfg = &pdata->cfg;
	struct clk_bulk clocks;
	uint32_t val;
	int ret;

	/* Enable the clocks feeding the MMC controller */
	ret = clk_get_bulk(dev, &clocks);
	if (ret)
		return ret;

	ret = clk_enable_bulk(&clocks);
	if (ret)
		return ret;

	cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
			MMC_VDD_31_32 | MMC_VDD_165_195;
	cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
			MMC_MODE_HS_52MHz | MMC_MODE_HS;
	cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
	cfg->f_max = 100000000; /* 100 MHz */
	cfg->b_max = 511; /* max 512 - 1 blocks */
	cfg->name = dev->name;

	mmc->priv = pdata;
	upriv->mmc = mmc;

	mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);

#if CONFIG_IS_ENABLED(MMC_PWRSEQ)
	/* Enable power if needed */
	ret = mmc_pwrseq_get_power(dev, cfg);
	if (!ret) {
		ret = pwrseq_set_power(cfg->pwr_dev, true);
		if (ret)
			return ret;
	}
#endif

	/* reset all status bits */
	meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);

	/* disable interrupts */
	meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);

	/* enable auto clock mode */
	val = meson_read(mmc, MESON_SD_EMMC_CFG);
	val &= ~CFG_SDCLK_ALWAYS_ON;
	val |= CFG_AUTO_CLK;
	meson_write(mmc, val, MESON_SD_EMMC_CFG);

	return 0;
}

int meson_mmc_bind(struct udevice *dev)
{
	struct meson_mmc_plat *pdata = dev_get_plat(dev);

	return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
}

static const struct udevice_id meson_mmc_match[] = {
	{ .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
	{ .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
	{ .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(meson_mmc) = {
	.name = "meson_gx_mmc",
	.id = UCLASS_MMC,
	.of_match = meson_mmc_match,
	.ops = &meson_dm_mmc_ops,
	.probe = meson_mmc_probe,
	.bind = meson_mmc_bind,
	.of_to_plat = meson_mmc_of_to_plat,
	.plat_auto	= sizeof(struct meson_mmc_plat),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
93738620 CC	2	/*
93738620 CC	3	* (C) Copyright 2016 Carlo Caione <[email protected]>
93738620 CC	4	*/
93738620 CC	5
0392416f	6	#include <clk.h>
1eb69ae4	7	#include <cpu_func.h>
9d922450	8	#include <dm.h>
93738620 CC	9	#include <fdtdec.h>
93738620 CC	10	#include <malloc.h>
a10388dc	11	#include <pwrseq.h>
93738620 CC	12	#include <mmc.h>
93738620 CC	13	#include <asm/io.h>
a10388dc	14	#include <asm/gpio.h>
c05ed00a	15	#include <linux/delay.h>
93738620	16	#include <linux/log2.h>
77863d43	17	#include "meson_gx_mmc.h"
93738620	18
0dbb54eb NA	19	bool meson_gx_mmc_is_compatible(struct udevice *dev,
	20	enum meson_gx_mmc_compatible family)
	21	{
	22	enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
	23
	24	return compat == family;
	25	}
	26
93738620 CC	27	static inline void get_regbase(const struct mmc mmc)
93738620 CC	28	{
8a8d24bd	29	struct meson_mmc_plat *pdata = mmc->priv;
93738620 CC	30
	31	return pdata->regbase;
	32	}
	33
	34	static inline uint32_t meson_read(struct mmc *mmc, int offset)
	35	{
	36	return readl(get_regbase(mmc) + offset);
	37	}
	38
	39	static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
	40	{
	41	writel(val, get_regbase(mmc) + offset);
	42	}
	43
	44	static void meson_mmc_config_clock(struct mmc *mmc)
	45	{
	46	uint32_t meson_mmc_clk = 0;
	47	unsigned int clk, clk_src, clk_div;
	48
f6549c85 HS	49	if (!mmc->clock)
	50	return;
	51
0dbb54eb NA	52	/* TOFIX This should use the proper clock taken from DT */
0dbb54eb NA	53
93738620 CC	54	/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
	55	if (mmc->clock > 16000000) {
	56	clk = SD_EMMC_CLKSRC_DIV2;
	57	clk_src = CLK_SRC_DIV2;
	58	} else {
	59	clk = SD_EMMC_CLKSRC_24M;
	60	clk_src = CLK_SRC_24M;
	61	}
	62	clk_div = DIV_ROUND_UP(clk, mmc->clock);
	63
0dbb54eb NA	64	/*
	65	* SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
	66	* If CLK_CO_PHASE_270 is used, it's more stable than other.
	67	* Other SoCs use CLK_CO_PHASE_180 by default.
	68	* It needs to find what is a proper value about each SoCs.
	69	*/
	70	if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
	71	meson_mmc_clk \|= CLK_CO_PHASE_270;
	72	else
	73	meson_mmc_clk \|= CLK_CO_PHASE_180;
93738620 CC	74
	75	/* 180 phase tx clock */
	76	meson_mmc_clk \|= CLK_TX_PHASE_000;
	77
	78	/* clock settings */
	79	meson_mmc_clk \|= clk_src;
	80	meson_mmc_clk \|= clk_div;
	81
	82	meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
	83	}
	84
	85	static int meson_dm_mmc_set_ios(struct udevice *dev)
	86	{
	87	struct mmc *mmc = mmc_get_mmc_dev(dev);
	88	uint32_t meson_mmc_cfg;
	89
	90	meson_mmc_config_clock(mmc);
	91
	92	meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
	93
	94	meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
	95	if (mmc->bus_width == 1)
	96	meson_mmc_cfg \|= CFG_BUS_WIDTH_1;
	97	else if (mmc->bus_width == 4)
	98	meson_mmc_cfg \|= CFG_BUS_WIDTH_4;
	99	else if (mmc->bus_width == 8)
	100	meson_mmc_cfg \|= CFG_BUS_WIDTH_8;
	101	else
	102	return -EINVAL;
	103
	104	/* 512 bytes block length */
	105	meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
	106	meson_mmc_cfg \|= CFG_BL_LEN_512;
	107
	108	/* Response timeout 256 clk */
	109	meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
	110	meson_mmc_cfg \|= CFG_RESP_TIMEOUT_256;
	111
	112	/* Command-command gap 16 clk */
	113	meson_mmc_cfg &= ~CFG_RC_CC_MASK;
	114	meson_mmc_cfg \|= CFG_RC_CC_16;
	115
	116	meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
	117
	118	return 0;
	119	}
	120
	121	static void meson_mmc_setup_cmd(struct mmc mmc, struct mmc_data data,
	122	struct mmc_cmd *cmd)
	123	{
	124	uint32_t meson_mmc_cmd = 0, cfg;
	125
	126	meson_mmc_cmd \|= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
	127
	128	if (cmd->resp_type & MMC_RSP_PRESENT) {
	129	if (cmd->resp_type & MMC_RSP_136)
	130	meson_mmc_cmd \|= CMD_CFG_RESP_128;
	131
	132	if (cmd->resp_type & MMC_RSP_BUSY)
	133	meson_mmc_cmd \|= CMD_CFG_R1B;
	134
	135	if (!(cmd->resp_type & MMC_RSP_CRC))
	136	meson_mmc_cmd \|= CMD_CFG_RESP_NOCRC;
	137	} else {
138	meson_mmc_cmd \|= CMD_CFG_NO_RESP;
139	}
140
141	if (data) {
142	cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
143	cfg &= ~CFG_BL_LEN_MASK;
144	cfg \|= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
145	meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
146
147	if (data->flags == MMC_DATA_WRITE)
148	meson_mmc_cmd \|= CMD_CFG_DATA_WR;
149
150	meson_mmc_cmd \|= CMD_CFG_DATA_IO \| CMD_CFG_BLOCK_MODE \|
151	data->blocks;
152	}
153
154	meson_mmc_cmd \|= CMD_CFG_TIMEOUT_4S \| CMD_CFG_OWNER \|
155	CMD_CFG_END_OF_CHAIN;
156
157	meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
158	}
159
160	static void meson_mmc_setup_addr(struct mmc mmc, struct mmc_data data)
161	{
8a8d24bd	162	struct meson_mmc_plat *pdata = mmc->priv;
93738620 CC	163	unsigned int data_size;
	164	uint32_t data_addr = 0;
	165
	166	if (data) {
	167	data_size = data->blocks * data->blocksize;
	168
	169	if (data->flags == MMC_DATA_READ) {
	170	data_addr = (ulong) data->dest;
	171	invalidate_dcache_range(data_addr,
	172	data_addr + data_size);
	173	} else {
	174	pdata->w_buf = calloc(data_size, sizeof(char));
	175	data_addr = (ulong) pdata->w_buf;
	176	memcpy(pdata->w_buf, data->src, data_size);
	177	flush_dcache_range(data_addr, data_addr + data_size);
	178	}
	179	}
	180
	181	meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
	182	}
	183
	184	static void meson_mmc_read_response(struct mmc mmc, struct mmc_cmd cmd)
	185	{
	186	if (cmd->resp_type & MMC_RSP_136) {
	187	cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
	188	cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
	189	cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
	190	cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
	191	} else {
	192	cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
	193	}
	194	}
	195
	196	static int meson_dm_mmc_send_cmd(struct udevice dev, struct mmc_cmd cmd,
	197	struct mmc_data *data)
	198	{
	199	struct mmc *mmc = mmc_get_mmc_dev(dev);
8a8d24bd	200	struct meson_mmc_plat *pdata = mmc->priv;
93738620 CC	201	uint32_t status;
	202	ulong start;
	203	int ret = 0;
	204
	205	/* max block size supported by chip is 512 byte */
	206	if (data && data->blocksize > 512)
	207	return -EINVAL;
	208
	209	meson_mmc_setup_cmd(mmc, data, cmd);
	210	meson_mmc_setup_addr(mmc, data);
	211
	212	meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
	213
	214	/* use 10s timeout */
	215	start = get_timer(0);
	216	do {
	217	status = meson_read(mmc, MESON_SD_EMMC_STATUS);
	218	} while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
	219
	220	if (!(status & STATUS_END_OF_CHAIN))
	221	ret = -ETIMEDOUT;
	222	else if (status & STATUS_RESP_TIMEOUT)
	223	ret = -ETIMEDOUT;
	224	else if (status & STATUS_ERR_MASK)
	225	ret = -EIO;
	226
	227	meson_mmc_read_response(mmc, cmd);
	228
	229	if (data && data->flags == MMC_DATA_WRITE)
	230	free(pdata->w_buf);
	231
	232	/* reset status bits */
	233	meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
	234
	235	return ret;
	236	}
	237
	238	static const struct dm_mmc_ops meson_dm_mmc_ops = {
	239	.send_cmd = meson_dm_mmc_send_cmd,
	240	.set_ios = meson_dm_mmc_set_ios,
	241	};
	242
d1998a9f	243	static int meson_mmc_of_to_plat(struct udevice *dev)
93738620	244	{
8a8d24bd	245	struct meson_mmc_plat *pdata = dev_get_plat(dev);
93738620 CC	246	fdt_addr_t addr;
93738620 CC	247
2548493a	248	addr = dev_read_addr(dev);
93738620 CC	249	if (addr == FDT_ADDR_T_NONE)
	250	return -EINVAL;
	251
	252	pdata->regbase = (void *)addr;
	253
	254	return 0;
	255	}
	256
	257	static int meson_mmc_probe(struct udevice *dev)
	258	{
8a8d24bd	259	struct meson_mmc_plat *pdata = dev_get_plat(dev);
93738620 CC	260	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	261	struct mmc *mmc = &pdata->mmc;
	262	struct mmc_config *cfg = &pdata->cfg;
0392416f	263	struct clk_bulk clocks;
93738620	264	uint32_t val;
0392416f JB	265	int ret;
0392416f JB	266
0392416f JB	267	/* Enable the clocks feeding the MMC controller */
	268	ret = clk_get_bulk(dev, &clocks);
	269	if (ret)
	270	return ret;
	271
	272	ret = clk_enable_bulk(&clocks);
	273	if (ret)
	274	return ret;
	275
93738620 CC	276	cfg->voltages = MMC_VDD_33_34 \| MMC_VDD_32_33 \|
	277	MMC_VDD_31_32 \| MMC_VDD_165_195;
	278	cfg->host_caps = MMC_MODE_8BIT \| MMC_MODE_4BIT \|
	279	MMC_MODE_HS_52MHz \| MMC_MODE_HS;
	280	cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
	281	cfg->f_max = 100000000; /* 100 MHz */
f98205c7	282	cfg->b_max = 511; /* max 512 - 1 blocks */
93738620 CC	283	cfg->name = dev->name;
	284
	285	mmc->priv = pdata;
	286	upriv->mmc = mmc;
	287
65117182	288	mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
93738620	289
d06e4899	290	#if CONFIG_IS_ENABLED(MMC_PWRSEQ)
a10388dc	291	/* Enable power if needed */
a96ea4d8	292	ret = mmc_pwrseq_get_power(dev, cfg);
a10388dc	293	if (!ret) {
a96ea4d8	294	ret = pwrseq_set_power(cfg->pwr_dev, true);
a10388dc NA	295	if (ret)
	296	return ret;
	297	}
	298	#endif
	299
93738620 CC	300	/* reset all status bits */
	301	meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
	302
	303	/* disable interrupts */
	304	meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
	305
	306	/* enable auto clock mode */
	307	val = meson_read(mmc, MESON_SD_EMMC_CFG);
	308	val &= ~CFG_SDCLK_ALWAYS_ON;
	309	val \|= CFG_AUTO_CLK;
	310	meson_write(mmc, val, MESON_SD_EMMC_CFG);
	311
	312	return 0;
	313	}
	314
	315	int meson_mmc_bind(struct udevice *dev)
	316	{
8a8d24bd	317	struct meson_mmc_plat *pdata = dev_get_plat(dev);
93738620 CC	318
	319	return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
	320	}
	321
	322	static const struct udevice_id meson_mmc_match[] = {
0dbb54eb NA	323	{ .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
	324	{ .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
	325	{ .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
93738620 CC	326	{ /* sentinel */ }
	327	};
	328
	329	U_BOOT_DRIVER(meson_mmc) = {
	330	.name = "meson_gx_mmc",
	331	.id = UCLASS_MMC,
	332	.of_match = meson_mmc_match,
	333	.ops = &meson_dm_mmc_ops,
	334	.probe = meson_mmc_probe,
	335	.bind = meson_mmc_bind,
d1998a9f	336	.of_to_plat = meson_mmc_of_to_plat,
8a8d24bd	337	.plat_auto = sizeof(struct meson_mmc_plat),
93738620	338	};