[J-u-boot.git] / drivers / pinctrl / intel / pinctrl.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 Intel Corp.
 * Copyright 2019 Google LLC
 *
 * Taken partly from coreboot gpio.c
 *
 * Pinctrl is modelled as a separate device-tree node and device for each
 * 'community' (basically a set of GPIOs). The separate devices work together
 * and many functions permit any PINCTRL device to be provided as a parameter,
 * since the pad numbering is unique across all devices.
 *
 * Each pinctrl has a single child GPIO device to handle GPIO access and
 * therefore there is a simple GPIO driver included in this file.
 */

#define LOG_CATEGORY UCLASS_GPIO

#include <common.h>
#include <dm.h>
#include <irq.h>
#include <log.h>
#include <malloc.h>
#include <p2sb.h>
#include <spl.h>
#include <asm-generic/gpio.h>
#include <asm/intel_pinctrl.h>
#include <asm/intel_pinctrl_defs.h>
#include <asm/arch/gpio.h>
#include <asm/itss.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
#include <linux/err.h>

#define GPIO_DW_SIZE(x)			(sizeof(u32) * (x))
#define PAD_CFG_OFFSET(x, dw_num)	((x) + GPIO_DW_SIZE(dw_num))
#define PAD_CFG0_OFFSET(x)		PAD_CFG_OFFSET(x, 0)
#define PAD_CFG1_OFFSET(x)		PAD_CFG_OFFSET(x, 1)

#define MISCCFG_GPE0_DW0_SHIFT 8
#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
#define MISCCFG_GPE0_DW1_SHIFT 12
#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
#define MISCCFG_GPE0_DW2_SHIFT 16
#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)

#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 +	\
				((group) * sizeof(u32)))
#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 +	\
				((group) * sizeof(u32)))
#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 +	\
				((group) * sizeof(uint32_t)))
#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 +	\
				((group) * sizeof(uint32_t)))

/**
 * relative_pad_in_comm() - Get the relative position of a GPIO
 *
 * This finds the position of a GPIO within a community
 *
 * @comm: Community to search
 * @gpio: Pad number to look up (assumed to be valid)
 * @return offset, 0 for first GPIO in community
 */
static size_t relative_pad_in_comm(const struct pad_community *comm,
				   uint gpio)
{
	return gpio - comm->first_pad;
}

/**
 * pinctrl_group_index() - Find group for a a pad
 *
 * Find the group within the community that the pad is a part of
 *
 * @comm: Community to search
 * @relative_pad: Pad to look up
 * @return group number if found (see community_n_groups, etc.), or
 *	-ESPIPE if no groups, or -ENOENT if not found
 */
static int pinctrl_group_index(const struct pad_community *comm,
			       uint relative_pad)
{
	int i;

	if (!comm->groups)
		return -ESPIPE;

	/* find the base pad number for this pad's group */
	for (i = 0; i < comm->num_groups; i++) {
		if (relative_pad >= comm->groups[i].first_pad &&
		    relative_pad < comm->groups[i].first_pad +
		    comm->groups[i].size)
			return i;
	}

	return -ENOENT;
}

static int pinctrl_group_index_scaled(const struct pad_community *comm,
				      uint relative_pad, size_t scale)
{
	int ret;

	ret = pinctrl_group_index(comm, relative_pad);
	if (ret < 0)
		return ret;

	return ret * scale;
}

static int pinctrl_within_group(const struct pad_community *comm,
				uint relative_pad)
{
	int ret;

	ret = pinctrl_group_index(comm, relative_pad);
	if (ret < 0)
		return ret;

	return relative_pad - comm->groups[ret].first_pad;
}

static u32 pinctrl_bitmask_within_group(const struct pad_community *comm,
					uint relative_pad)
{
	return 1U << pinctrl_within_group(comm, relative_pad);
}

/**
 * pinctrl_get_device() - Find the device for a particular pad
 *
 * Each pinctr, device is attached to one community and this supports a number
 * of pads. This function finds the device which controls a particular pad.
 *
 * @pad: Pad to check
 * @devp: Returns the device for that pad
 * @return 0 if OK, -ENOTBLK if no device was found for the given pin
 */
static int pinctrl_get_device(uint pad, struct udevice **devp)
{
	struct udevice *dev;

	/*
	 * We have to probe each one of these since the community link is only
	 * attached in intel_pinctrl_of_to_plat().
	 */
	uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
		struct intel_pinctrl_priv *priv = dev_get_priv(dev);
		const struct pad_community *comm = priv->comm;

		if (pad >= comm->first_pad && pad <= comm->last_pad) {
			*devp = dev;
			return 0;
		}
	}
	log_debug("pad %d not found\n", pad);

	return -ENOTBLK;
}

int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp)
{
	const struct pad_community *comm;
	struct intel_pinctrl_priv *priv;
	struct udevice *dev;
	int ret;

	ret = pinctrl_get_device(pad, &dev);
	if (ret)
		return log_msg_ret("pad", ret);
	priv = dev_get_priv(dev);
	comm = priv->comm;
	*devp = dev;
	*offsetp = relative_pad_in_comm(comm, pad);

	return 0;
}

static int pinctrl_configure_owner(struct udevice *dev,
				   const struct pad_config *cfg,
				   const struct pad_community *comm)
{
	u32 hostsw_own;
	u16 hostsw_own_offset;
	int pin;
	int ret;

	pin = relative_pad_in_comm(comm, cfg->pad);

	/*
	 * Based on the gpio pin number configure the corresponding bit in
	 * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
	 */
	hostsw_own_offset = comm->host_own_reg_0;
	ret = pinctrl_group_index_scaled(comm, pin, sizeof(u32));
	if (ret < 0)
		return ret;
	hostsw_own_offset += ret;

	hostsw_own = pcr_read32(dev, hostsw_own_offset);

	/*
	 *The 4th bit in pad_config 1 (RO) is used to indicate if the pad
	 * needs GPIO driver ownership.  Set the bit if GPIO driver ownership
	 * requested, otherwise clear the bit.
	 */
	if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)
		hostsw_own |= pinctrl_bitmask_within_group(comm, pin);
	else
		hostsw_own &= ~pinctrl_bitmask_within_group(comm, pin);

	pcr_write32(dev, hostsw_own_offset, hostsw_own);

	return 0;
}

static int gpi_enable_smi(struct udevice *dev, const struct pad_config *cfg,
			  const struct pad_community *comm)
{
	u32 value;
	u16 sts_reg;
	u16 en_reg;
	int group;
	int pin;
	int ret;

	if ((cfg->pad_config[0] & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI)
		return 0;

	pin = relative_pad_in_comm(comm, cfg->pad);
	ret = pinctrl_group_index(comm, pin);
	if (ret < 0)
		return ret;
	group = ret;

	sts_reg = GPI_SMI_STS_OFFSET(comm, group);
	value = pcr_read32(dev, sts_reg);
	/* Write back 1 to reset the sts bits */
	pcr_write32(dev, sts_reg, value);

	/* Set enable bits */
	en_reg = GPI_SMI_EN_OFFSET(comm, group);
	pcr_setbits32(dev, en_reg, pinctrl_bitmask_within_group(comm, pin));

	return 0;
}

static int pinctrl_configure_itss(struct udevice *dev,
				  const struct pad_config *cfg,
				  uint pad_cfg_offset)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);

	if (!priv->itss_pol_cfg)
		return -ENOSYS;

	int irq;

	/*
	 * Set up ITSS polarity if pad is routed to APIC.
	 *
	 * The ITSS takes only active high interrupt signals. Therefore,
	 * if the pad configuration indicates an inversion assume the
	 * intent is for the ITSS polarity. Before forwarding on the
	 * request to the APIC there's an inversion setting for how the
	 * signal is forwarded to the APIC. Honor the inversion setting
	 * in the GPIO pad configuration so that a hardware active low
	 * signal looks that way to the APIC (double inversion).
	 */
	if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC))
		return 0;

	irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset));
	irq &= PAD_CFG1_IRQ_MASK;
	if (!irq) {
		if (spl_phase() > PHASE_TPL)
			log_err("GPIO %u doesn't support APIC routing\n",
				cfg->pad);

		return -EPROTONOSUPPORT;
	}
	irq_set_polarity(priv->itss, irq,
			 cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT);

	return 0;
}

/* Number of DWx config registers can be different for different SOCs */
static uint pad_config_offset(struct intel_pinctrl_priv *priv, uint pad)
{
	const struct pad_community *comm = priv->comm;
	size_t offset;

	offset = relative_pad_in_comm(comm, pad);
	offset *= GPIO_DW_SIZE(priv->num_cfgs);

	return offset + comm->pad_cfg_base;
}

static int pinctrl_pad_reset_config_override(const struct pad_community *comm,
					     u32 config_value)
{
	const struct reset_mapping *rst_map = comm->reset_map;
	int i;

	/* Logical reset values equal chipset values */
	if (!rst_map || !comm->num_reset_vals)
		return config_value;

	for (i = 0; i < comm->num_reset_vals; i++, rst_map++) {
		if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) {
			config_value &= ~PAD_CFG0_RESET_MASK;
			config_value |= rst_map->chipset;

			return config_value;
		}
	}
	if (spl_phase() > PHASE_TPL)
		log_err("Logical-to-Chipset mapping not found\n");

	return -ENOENT;
}

static const int mask[4] = {
	PAD_CFG0_TX_STATE |
	PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |
	PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK |
	PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL |
	PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK |
	PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK,

#ifdef CONFIG_INTEL_PINCTRL_IOSTANDBY
	PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK | PAD_CFG1_IOSSTATE_MASK,
#else
	PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK,
#endif

	PAD_CFG2_DEBOUNCE_MASK,

	0,
};

/**
 * pinctrl_configure_pad() - Configure a pad
 *
 * @dev: Pinctrl device containing the pad (see pinctrl_get_device())
 * @cfg: Configuration to apply
 * @return 0 if OK, -ve on error
 */
static int pinctrl_configure_pad(struct udevice *dev,
				 const struct pad_config *cfg)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	const struct pad_community *comm = priv->comm;
	uint config_offset;
	u32 pad_conf, soc_pad_conf;
	int ret;
	int i;

	if (IS_ERR(comm))
		return PTR_ERR(comm);
	config_offset = pad_config_offset(priv, cfg->pad);
	for (i = 0; i < priv->num_cfgs; i++) {
		pad_conf = pcr_read32(dev, PAD_CFG_OFFSET(config_offset, i));

		soc_pad_conf = cfg->pad_config[i];
		if (i == 0) {
			ret = pinctrl_pad_reset_config_override(comm,
								soc_pad_conf);
			if (ret < 0)
				return ret;
			soc_pad_conf = ret;
		}
		soc_pad_conf &= mask[i];
		soc_pad_conf |= pad_conf & ~mask[i];

		log_debug("pinctrl_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x : 0x%08x]\n",
			  comm->port, relative_pad_in_comm(comm, cfg->pad), i,
			  pad_conf,/* old value */
			  /* value passed from pinctrl table */
			  cfg->pad_config[i],
			  soc_pad_conf); /*new value*/
		pcr_write32(dev, PAD_CFG_OFFSET(config_offset, i),
			    soc_pad_conf);
	}
	ret = pinctrl_configure_itss(dev, cfg, config_offset);
	if (ret && ret != -ENOSYS)
		return log_msg_ret("itss config failed", ret);
	ret = pinctrl_configure_owner(dev, cfg, comm);
	if (ret)
		return ret;
	ret = gpi_enable_smi(dev, cfg, comm);
	if (ret)
		return ret;

	return 0;
}

u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	const struct pad_community *comm = priv->comm;
	uint config_offset;

	assert(device_get_uclass_id(dev) == UCLASS_PINCTRL);
	config_offset = comm->pad_cfg_base + offset *
		 GPIO_DW_SIZE(priv->num_cfgs);

	return config_offset;
}

u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
{
	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);

	return (u32)(ulong)pcr_reg_address(dev, config_offset);
}

u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset)
{
	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);

	return pcr_read32(dev, config_offset);
}

int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	const struct pad_community *comm = priv->comm;
	int group;

	if (IS_ENABLED(CONFIG_INTEL_PINCTRL_MULTI_ACPI_DEVICES))
		return offset;
	group = pinctrl_group_index(comm, offset);

	/* If pad base is not set then use GPIO number as ACPI pin number */
	if (comm->groups[group].acpi_pad_base == PAD_BASE_NONE)
		return comm->first_pad + offset;

	/*
	 * If this group has a non-zero pad base then compute the ACPI pin
	 * number from the pad base and the relative pad in the group.
	 */
	return comm->groups[group].acpi_pad_base +
		 pinctrl_within_group(comm, offset);
}

int pinctrl_route_gpe(struct udevice *itss, uint gpe0b, uint gpe0c, uint gpe0d)
{
	struct udevice *pinctrl_dev;
	u32 misccfg_value;
	u32 misccfg_clr;
	int ret;

	/*
	 * Get the group here for community specific MISCCFG register.
	 * If any of these returns -1 then there is some error in devicetree
	 * where the group is probably hardcoded and does not comply with the
	 * PMC group defines. So we return from here and MISCFG is set to
	 * default.
	 */
	ret = irq_route_pmc_gpio_gpe(itss, gpe0b);
	if (ret)
		return ret;
	gpe0b = ret;

	ret = irq_route_pmc_gpio_gpe(itss, gpe0c);
	if (ret)
		return ret;
	gpe0c = ret;

	ret = irq_route_pmc_gpio_gpe(itss, gpe0d);
	if (ret)
		return ret;
	gpe0d = ret;

	misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT;
	misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT;
	misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT;

	/* Program GPIO_MISCCFG */
	misccfg_clr = MISCCFG_GPE0_DW2_MASK | MISCCFG_GPE0_DW1_MASK |
		MISCCFG_GPE0_DW0_MASK;

	log_debug("misccfg_clr:%x misccfg_value:%x\n", misccfg_clr,
		  misccfg_value);
	uclass_foreach_dev_probe(UCLASS_PINCTRL, pinctrl_dev) {
		pcr_clrsetbits32(pinctrl_dev, GPIO_MISCCFG, misccfg_clr,
				 misccfg_value);
	}

	return 0;
}

int pinctrl_gpi_clear_int_cfg(void)
{
	struct udevice *dev;
	struct uclass *uc;
	int ret;

	ret = uclass_get(UCLASS_PINCTRL, &uc);
	if (ret)
		return log_msg_ret("pinctrl uc", ret);
	uclass_foreach_dev(dev, uc) {
		struct intel_pinctrl_priv *priv = dev_get_priv(dev);
		const struct pad_community *comm = priv->comm;
		uint sts_value;
		int group;

		for (group = 0; group < comm->num_gpi_regs; group++) {
			/* Clear the enable register */
			pcr_write32(dev, GPI_IE_OFFSET(comm, group), 0);

			/* Read and clear the set status register bits*/
			sts_value = pcr_read32(dev,
					       GPI_IS_OFFSET(comm, group));
			pcr_write32(dev, GPI_IS_OFFSET(comm, group), sts_value);
		}
	}

	return 0;
}

int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	const u32 *ptr;
	int i;

	log_debug("%s: pads_count=%d\n", __func__, pads_count);
	for (ptr = pads, i = 0; i < pads_count;
	     ptr += 1 + priv->num_cfgs, i++) {
		struct udevice *pad_dev = NULL;
		struct pad_config *cfg;
		int ret;

		cfg = (struct pad_config *)ptr;
		ret = pinctrl_get_device(cfg->pad, &pad_dev);
		if (ret)
			return ret;
		ret = pinctrl_configure_pad(pad_dev, cfg);
		if (ret)
			return ret;
	}

	return 0;
}

int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
		      u32 **padsp, int *pad_countp)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	u32 *pads;
	int size;
	int ret;

	*padsp = NULL;
	*pad_countp = 0;
	size = ofnode_read_size(node, prop);
	if (size < 0)
		return 0;

	pads = malloc(size);
	if (!pads)
		return -ENOMEM;
	size /= sizeof(fdt32_t);
	ret = ofnode_read_u32_array(node, prop, pads, size);
	if (ret) {
		free(pads);
		return ret;
	}
	*pad_countp = size / (1 + priv->num_cfgs);
	*padsp = pads;

	return 0;
}

int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	int count = 0;
	int i;

	for (i = 0; i < size;) {
		u32 val;
		int j;

		for (val = j = 0; j < priv->num_cfgs + 1; j++)
			val |= pads[i + j];
		if (!val)
			break;
		count++;
		i += priv->num_cfgs + 1;
	}

	return count;
}

int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node)
{
	int pads_count;
	u32 *pads;
	int ret;

	if (device_get_uclass_id(dev) != UCLASS_PINCTRL)
		return log_msg_ret("uclass", -EPROTONOSUPPORT);
	ret = pinctrl_read_pads(dev, node, "pads", &pads, &pads_count);
	if (ret)
		return log_msg_ret("no pads", ret);
	ret = pinctrl_config_pads(dev, pads, pads_count);
	free(pads);
	if (ret)
		return log_msg_ret("pad config", ret);

	return 0;
}

int intel_pinctrl_of_to_plat(struct udevice *dev,
			     const struct pad_community *comm, int num_cfgs)
{
	struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);

	if (!comm) {
		if (spl_phase() > PHASE_TPL)
			log_err("Cannot find community for pid %d\n",
				pplat->pid);
		return -EDOM;
	}
	priv->comm = comm;
	priv->num_cfgs = num_cfgs;

	return 0;
}

int intel_pinctrl_probe(struct udevice *dev)
{
	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	int ret;

	priv->itss_pol_cfg = true;
	ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
	if (ret)
		return log_msg_ret("Cannot find ITSS", ret);

	return 0;
}

const struct pinctrl_ops intel_pinctrl_ops = {
	/* No operations are supported, but DM expects this to be present */
};
Commit	Line	Data
74749f1e SG	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2017 Intel Corp.
	4	* Copyright 2019 Google LLC
	5	*
	6	* Taken partly from coreboot gpio.c
	7	*
	8	* Pinctrl is modelled as a separate device-tree node and device for each
	9	* 'community' (basically a set of GPIOs). The separate devices work together
	10	* and many functions permit any PINCTRL device to be provided as a parameter,
	11	* since the pad numbering is unique across all devices.
	12	*
	13	* Each pinctrl has a single child GPIO device to handle GPIO access and
	14	* therefore there is a simple GPIO driver included in this file.
	15	*/
	16
	17	#define LOG_CATEGORY UCLASS_GPIO
	18
	19	#include <common.h>
	20	#include <dm.h>
	21	#include <irq.h>
f7ae49fc	22	#include <log.h>
336d4615	23	#include <malloc.h>
74749f1e SG	24	#include <p2sb.h>
	25	#include <spl.h>
	26	#include <asm-generic/gpio.h>
	27	#include <asm/intel_pinctrl.h>
	28	#include <asm/intel_pinctrl_defs.h>
	29	#include <asm/arch/gpio.h>
142c9751	30	#include <asm/itss.h>
74749f1e SG	31	#include <dm/device-internal.h>
74749f1e SG	32	#include <dt-bindings/gpio/gpio.h>
61b29b82	33	#include <linux/err.h>
74749f1e SG	34
	35	#define GPIO_DW_SIZE(x) (sizeof(u32) * (x))
	36	#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num))
	37	#define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0)
	38	#define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1)
	39
	40	#define MISCCFG_GPE0_DW0_SHIFT 8
	41	#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
	42	#define MISCCFG_GPE0_DW1_SHIFT 12
	43	#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
	44	#define MISCCFG_GPE0_DW2_SHIFT 16
	45	#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
	46
	47	#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \
	48	((group) * sizeof(u32)))
	49	#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \
	50	((group) * sizeof(u32)))
	51	#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \
	52	((group) * sizeof(uint32_t)))
	53	#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \
	54	((group) * sizeof(uint32_t)))
	55
	56	/**
	57	* relative_pad_in_comm() - Get the relative position of a GPIO
	58	*
	59	* This finds the position of a GPIO within a community
	60	*
	61	* @comm: Community to search
	62	* @gpio: Pad number to look up (assumed to be valid)
	63	* @return offset, 0 for first GPIO in community
	64	*/
	65	static size_t relative_pad_in_comm(const struct pad_community *comm,
	66	uint gpio)
	67	{
	68	return gpio - comm->first_pad;
	69	}
	70
	71	/**
	72	* pinctrl_group_index() - Find group for a a pad
	73	*
	74	* Find the group within the community that the pad is a part of
	75	*
	76	* @comm: Community to search
	77	* @relative_pad: Pad to look up
	78	* @return group number if found (see community_n_groups, etc.), or
	79	* -ESPIPE if no groups, or -ENOENT if not found
	80	*/
	81	static int pinctrl_group_index(const struct pad_community *comm,
	82	uint relative_pad)
	83	{
	84	int i;
	85
	86	if (!comm->groups)
	87	return -ESPIPE;
	88
	89	/* find the base pad number for this pad's group */
	90	for (i = 0; i < comm->num_groups; i++) {
	91	if (relative_pad >= comm->groups[i].first_pad &&
	92	relative_pad < comm->groups[i].first_pad +
	93	comm->groups[i].size)
	94	return i;
	95	}
	96
	97	return -ENOENT;
98	}
99
100	static int pinctrl_group_index_scaled(const struct pad_community *comm,
101	uint relative_pad, size_t scale)
102	{
103	int ret;
104
105	ret = pinctrl_group_index(comm, relative_pad);
106	if (ret < 0)
107	return ret;
108
109	return ret * scale;
110	}
111
112	static int pinctrl_within_group(const struct pad_community *comm,
113	uint relative_pad)
114	{
115	int ret;
116
117	ret = pinctrl_group_index(comm, relative_pad);
118	if (ret < 0)
119	return ret;
120
121	return relative_pad - comm->groups[ret].first_pad;
122	}
123
124	static u32 pinctrl_bitmask_within_group(const struct pad_community *comm,
125	uint relative_pad)
126	{
127	return 1U << pinctrl_within_group(comm, relative_pad);
128	}
129
130	/**
131	* pinctrl_get_device() - Find the device for a particular pad
132	*
133	* Each pinctr, device is attached to one community and this supports a number
134	* of pads. This function finds the device which controls a particular pad.
135	*
136	* @pad: Pad to check
137	* @devp: Returns the device for that pad
138	* @return 0 if OK, -ENOTBLK if no device was found for the given pin
139	*/
140	static int pinctrl_get_device(uint pad, struct udevice **devp)
141	{
142	struct udevice *dev;
143
144	/*
145	* We have to probe each one of these since the community link is only
d1998a9f	146	* attached in intel_pinctrl_of_to_plat().
74749f1e SG	147	*/
	148	uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
	149	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	150	const struct pad_community *comm = priv->comm;
	151
	152	if (pad >= comm->first_pad && pad <= comm->last_pad) {
	153	*devp = dev;
	154	return 0;
	155	}
	156	}
dd27cd6d	157	log_debug("pad %d not found\n", pad);
74749f1e SG	158
	159	return -ENOTBLK;
	160	}
	161
	162	int intel_pinctrl_get_pad(uint pad, struct udevice *devp, uint offsetp)
	163	{
	164	const struct pad_community *comm;
	165	struct intel_pinctrl_priv *priv;
	166	struct udevice *dev;
	167	int ret;
	168
	169	ret = pinctrl_get_device(pad, &dev);
	170	if (ret)
	171	return log_msg_ret("pad", ret);
	172	priv = dev_get_priv(dev);
	173	comm = priv->comm;
	174	*devp = dev;
	175	*offsetp = relative_pad_in_comm(comm, pad);
	176
	177	return 0;
	178	}
	179
	180	static int pinctrl_configure_owner(struct udevice *dev,
	181	const struct pad_config *cfg,
	182	const struct pad_community *comm)
	183	{
	184	u32 hostsw_own;
	185	u16 hostsw_own_offset;
	186	int pin;
	187	int ret;
	188
	189	pin = relative_pad_in_comm(comm, cfg->pad);
	190
	191	/*
	192	* Based on the gpio pin number configure the corresponding bit in
	193	* HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
	194	*/
	195	hostsw_own_offset = comm->host_own_reg_0;
	196	ret = pinctrl_group_index_scaled(comm, pin, sizeof(u32));
	197	if (ret < 0)
	198	return ret;
	199	hostsw_own_offset += ret;
	200
	201	hostsw_own = pcr_read32(dev, hostsw_own_offset);
	202
	203	/*
	204	*The 4th bit in pad_config 1 (RO) is used to indicate if the pad
	205	* needs GPIO driver ownership. Set the bit if GPIO driver ownership
	206	* requested, otherwise clear the bit.
	207	*/
	208	if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)
	209	hostsw_own \|= pinctrl_bitmask_within_group(comm, pin);
	210	else
	211	hostsw_own &= ~pinctrl_bitmask_within_group(comm, pin);
	212
	213	pcr_write32(dev, hostsw_own_offset, hostsw_own);
	214
	215	return 0;
	216	}
	217
	218	static int gpi_enable_smi(struct udevice dev, const struct pad_config cfg,
	219	const struct pad_community *comm)
	220	{
	221	u32 value;
222	u16 sts_reg;
223	u16 en_reg;
224	int group;
225	int pin;
226	int ret;
227
228	if ((cfg->pad_config[0] & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI)
229	return 0;
230
231	pin = relative_pad_in_comm(comm, cfg->pad);
232	ret = pinctrl_group_index(comm, pin);
233	if (ret < 0)
234	return ret;
235	group = ret;
236
237	sts_reg = GPI_SMI_STS_OFFSET(comm, group);
238	value = pcr_read32(dev, sts_reg);
239	/* Write back 1 to reset the sts bits */
240	pcr_write32(dev, sts_reg, value);
241
242	/* Set enable bits */
243	en_reg = GPI_SMI_EN_OFFSET(comm, group);
244	pcr_setbits32(dev, en_reg, pinctrl_bitmask_within_group(comm, pin));
245
246	return 0;
247	}
248
249	static int pinctrl_configure_itss(struct udevice *dev,
250	const struct pad_config *cfg,
251	uint pad_cfg_offset)
252	{
253	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
254
255	if (!priv->itss_pol_cfg)
256	return -ENOSYS;
257
258	int irq;
259
260	/*
261	* Set up ITSS polarity if pad is routed to APIC.
262	*
263	* The ITSS takes only active high interrupt signals. Therefore,
264	* if the pad configuration indicates an inversion assume the
265	* intent is for the ITSS polarity. Before forwarding on the
266	* request to the APIC there's an inversion setting for how the
267	* signal is forwarded to the APIC. Honor the inversion setting
268	* in the GPIO pad configuration so that a hardware active low
269	* signal looks that way to the APIC (double inversion).
270	*/
271	if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC))
272	return 0;
273
274	irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset));
275	irq &= PAD_CFG1_IRQ_MASK;
276	if (!irq) {
53d59694 SG	277	if (spl_phase() > PHASE_TPL)
	278	log_err("GPIO %u doesn't support APIC routing\n",
	279	cfg->pad);
74749f1e SG	280
	281	return -EPROTONOSUPPORT;
	282	}
	283	irq_set_polarity(priv->itss, irq,
	284	cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT);
	285
	286	return 0;
	287	}
	288
	289	/* Number of DWx config registers can be different for different SOCs */
	290	static uint pad_config_offset(struct intel_pinctrl_priv *priv, uint pad)
	291	{
	292	const struct pad_community *comm = priv->comm;
	293	size_t offset;
	294
	295	offset = relative_pad_in_comm(comm, pad);
	296	offset *= GPIO_DW_SIZE(priv->num_cfgs);
	297
	298	return offset + comm->pad_cfg_base;
	299	}
	300
	301	static int pinctrl_pad_reset_config_override(const struct pad_community *comm,
	302	u32 config_value)
	303	{
	304	const struct reset_mapping *rst_map = comm->reset_map;
	305	int i;
	306
	307	/* Logical reset values equal chipset values */
	308	if (!rst_map \|\| !comm->num_reset_vals)
	309	return config_value;
	310
	311	for (i = 0; i < comm->num_reset_vals; i++, rst_map++) {
	312	if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) {
	313	config_value &= ~PAD_CFG0_RESET_MASK;
	314	config_value \|= rst_map->chipset;
	315
	316	return config_value;
	317	}
	318	}
53d59694 SG	319	if (spl_phase() > PHASE_TPL)
53d59694 SG	320	log_err("Logical-to-Chipset mapping not found\n");
74749f1e SG	321
	322	return -ENOENT;
	323	}
	324
	325	static const int mask[4] = {
	326	PAD_CFG0_TX_STATE \|
	327	PAD_CFG0_TX_DISABLE \| PAD_CFG0_RX_DISABLE \| PAD_CFG0_MODE_MASK \|
	328	PAD_CFG0_ROUTE_MASK \| PAD_CFG0_RXTENCFG_MASK \|
	329	PAD_CFG0_RXINV_MASK \| PAD_CFG0_PREGFRXSEL \|
	330	PAD_CFG0_TRIG_MASK \| PAD_CFG0_RXRAW1_MASK \|
	331	PAD_CFG0_RXPADSTSEL_MASK \| PAD_CFG0_RESET_MASK,
	332
	333	#ifdef CONFIG_INTEL_PINCTRL_IOSTANDBY
	334	PAD_CFG1_IOSTERM_MASK \| PAD_CFG1_PULL_MASK \| PAD_CFG1_IOSSTATE_MASK,
	335	#else
	336	PAD_CFG1_IOSTERM_MASK \| PAD_CFG1_PULL_MASK,
	337	#endif
	338
	339	PAD_CFG2_DEBOUNCE_MASK,
	340
	341	0,
	342	};
	343
	344	/**
	345	* pinctrl_configure_pad() - Configure a pad
	346	*
	347	* @dev: Pinctrl device containing the pad (see pinctrl_get_device())
	348	* @cfg: Configuration to apply
	349	* @return 0 if OK, -ve on error
	350	*/
	351	static int pinctrl_configure_pad(struct udevice *dev,
	352	const struct pad_config *cfg)
	353	{
	354	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	355	const struct pad_community *comm = priv->comm;
	356	uint config_offset;
	357	u32 pad_conf, soc_pad_conf;
	358	int ret;
	359	int i;
	360
	361	if (IS_ERR(comm))
	362	return PTR_ERR(comm);
	363	config_offset = pad_config_offset(priv, cfg->pad);
	364	for (i = 0; i < priv->num_cfgs; i++) {
	365	pad_conf = pcr_read32(dev, PAD_CFG_OFFSET(config_offset, i));
	366
	367	soc_pad_conf = cfg->pad_config[i];
	368	if (i == 0) {
	369	ret = pinctrl_pad_reset_config_override(comm,
	370	soc_pad_conf);
	371	if (ret < 0)
	372	return ret;
	373	soc_pad_conf = ret;
	374	}
	375	soc_pad_conf &= mask[i];
	376	soc_pad_conf \|= pad_conf & ~mask[i];
	377
	378	log_debug("pinctrl_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x : 0x%08x]\n",
	379	comm->port, relative_pad_in_comm(comm, cfg->pad), i,
	380	pad_conf,/* old value */
	381	/* value passed from pinctrl table */
	382	cfg->pad_config[i],
	383	soc_pad_conf); /new value/
	384	pcr_write32(dev, PAD_CFG_OFFSET(config_offset, i),
385	soc_pad_conf);
386	}
387	ret = pinctrl_configure_itss(dev, cfg, config_offset);
388	if (ret && ret != -ENOSYS)
389	return log_msg_ret("itss config failed", ret);
390	ret = pinctrl_configure_owner(dev, cfg, comm);
391	if (ret)
392	return ret;
393	ret = gpi_enable_smi(dev, cfg, comm);
394	if (ret)
395	return ret;
396
397	return 0;
398	}
399
4916f458	400	u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset)
74749f1e SG	401	{
	402	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	403	const struct pad_community *comm = priv->comm;
	404	uint config_offset;
	405
	406	assert(device_get_uclass_id(dev) == UCLASS_PINCTRL);
	407	config_offset = comm->pad_cfg_base + offset *
	408	GPIO_DW_SIZE(priv->num_cfgs);
	409
	410	return config_offset;
	411	}
	412
4916f458 SG	413	u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
	414	{
	415	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);
	416
	417	return (u32)(ulong)pcr_reg_address(dev, config_offset);
	418	}
	419
74749f1e SG	420	u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset)
74749f1e SG	421	{
4916f458	422	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);
74749f1e SG	423
	424	return pcr_read32(dev, config_offset);
	425	}
	426
	427	int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
	428	{
	429	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
	430	const struct pad_community *comm = priv->comm;
	431	int group;
	432
a9331a33 SG	433	if (IS_ENABLED(CONFIG_INTEL_PINCTRL_MULTI_ACPI_DEVICES))
a9331a33 SG	434	return offset;
74749f1e SG	435	group = pinctrl_group_index(comm, offset);
	436
	437	/* If pad base is not set then use GPIO number as ACPI pin number */
	438	if (comm->groups[group].acpi_pad_base == PAD_BASE_NONE)
	439	return comm->first_pad + offset;
	440
	441	/*
	442	* If this group has a non-zero pad base then compute the ACPI pin
	443	* number from the pad base and the relative pad in the group.
	444	*/
	445	return comm->groups[group].acpi_pad_base +
	446	pinctrl_within_group(comm, offset);
	447	}
	448
	449	int pinctrl_route_gpe(struct udevice *itss, uint gpe0b, uint gpe0c, uint gpe0d)
	450	{
	451	struct udevice *pinctrl_dev;
	452	u32 misccfg_value;
	453	u32 misccfg_clr;
	454	int ret;
	455
	456	/*
	457	* Get the group here for community specific MISCCFG register.
	458	* If any of these returns -1 then there is some error in devicetree
	459	* where the group is probably hardcoded and does not comply with the
	460	* PMC group defines. So we return from here and MISCFG is set to
	461	* default.
	462	*/
	463	ret = irq_route_pmc_gpio_gpe(itss, gpe0b);
	464	if (ret)
	465	return ret;
	466	gpe0b = ret;
	467
	468	ret = irq_route_pmc_gpio_gpe(itss, gpe0c);
	469	if (ret)
	470	return ret;
	471	gpe0c = ret;
	472
	473	ret = irq_route_pmc_gpio_gpe(itss, gpe0d);
	474	if (ret)
	475	return ret;
	476	gpe0d = ret;
	477
	478	misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT;
	479	misccfg_value \|= gpe0c << MISCCFG_GPE0_DW1_SHIFT;
	480	misccfg_value \|= gpe0d << MISCCFG_GPE0_DW2_SHIFT;
	481
	482	/* Program GPIO_MISCCFG */
	483	misccfg_clr = MISCCFG_GPE0_DW2_MASK \| MISCCFG_GPE0_DW1_MASK \|
	484	MISCCFG_GPE0_DW0_MASK;
	485
	486	log_debug("misccfg_clr:%x misccfg_value:%x\n", misccfg_clr,
	487	misccfg_value);
	488	uclass_foreach_dev_probe(UCLASS_PINCTRL, pinctrl_dev) {
	489	pcr_clrsetbits32(pinctrl_dev, GPIO_MISCCFG, misccfg_clr,
	490	misccfg_value);
	491	}
	492
	493	return 0;
	494	}
	495
	496	int pinctrl_gpi_clear_int_cfg(void)
	497	{
	498	struct udevice *dev;
499	struct uclass *uc;
500	int ret;
501
502	ret = uclass_get(UCLASS_PINCTRL, &uc);
503	if (ret)
504	return log_msg_ret("pinctrl uc", ret);
505	uclass_foreach_dev(dev, uc) {
506	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
507	const struct pad_community *comm = priv->comm;
508	uint sts_value;
509	int group;
510
511	for (group = 0; group < comm->num_gpi_regs; group++) {
512	/* Clear the enable register */
513	pcr_write32(dev, GPI_IE_OFFSET(comm, group), 0);
514
515	/* Read and clear the set status register bits*/
516	sts_value = pcr_read32(dev,
517	GPI_IS_OFFSET(comm, group));
518	pcr_write32(dev, GPI_IS_OFFSET(comm, group), sts_value);
519	}
520	}
521
522	return 0;
523	}
524
525	int pinctrl_config_pads(struct udevice dev, u32 pads, int pads_count)
526	{
527	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
528	const u32 *ptr;
529	int i;
530
531	log_debug("%s: pads_count=%d\n", __func__, pads_count);
532	for (ptr = pads, i = 0; i < pads_count;
533	ptr += 1 + priv->num_cfgs, i++) {
534	struct udevice *pad_dev = NULL;
535	struct pad_config *cfg;
536	int ret;
537
538	cfg = (struct pad_config *)ptr;
539	ret = pinctrl_get_device(cfg->pad, &pad_dev);
540	if (ret)
541	return ret;
542	ret = pinctrl_configure_pad(pad_dev, cfg);
543	if (ret)
544	return ret;
545	}
546
547	return 0;
548	}
549
550	int pinctrl_read_pads(struct udevice dev, ofnode node, const char prop,
551	u32 *padsp, int pad_countp)
552	{
553	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
554	u32 *pads;
555	int size;
556	int ret;
557
558	*padsp = NULL;
559	*pad_countp = 0;
560	size = ofnode_read_size(node, prop);
561	if (size < 0)
562	return 0;
563
564	pads = malloc(size);
565	if (!pads)
566	return -ENOMEM;
567	size /= sizeof(fdt32_t);
568	ret = ofnode_read_u32_array(node, prop, pads, size);
569	if (ret) {
570	free(pads);
571	return ret;
572	}
573	*pad_countp = size / (1 + priv->num_cfgs);
574	*padsp = pads;
575
576	return 0;
577	}
578
579	int pinctrl_count_pads(struct udevice dev, u32 pads, int size)
580	{
581	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
582	int count = 0;
583	int i;
584
585	for (i = 0; i < size;) {
586	u32 val;
587	int j;
588
589	for (val = j = 0; j < priv->num_cfgs + 1; j++)
590	val \|= pads[i + j];
591	if (!val)
592	break;
593	count++;
594	i += priv->num_cfgs + 1;
595	}
596
597	return count;
598	}
599
600	int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node)
601	{
602	int pads_count;
603	u32 *pads;
604	int ret;
605
606	if (device_get_uclass_id(dev) != UCLASS_PINCTRL)
607	return log_msg_ret("uclass", -EPROTONOSUPPORT);
608	ret = pinctrl_read_pads(dev, node, "pads", &pads, &pads_count);
609	if (ret)
610	return log_msg_ret("no pads", ret);
611	ret = pinctrl_config_pads(dev, pads, pads_count);
612	free(pads);
613	if (ret)
614	return log_msg_ret("pad config", ret);
615
616	return 0;
617	}
618
d1998a9f SG	619	int intel_pinctrl_of_to_plat(struct udevice *dev,
d1998a9f SG	620	const struct pad_community *comm, int num_cfgs)
74749f1e	621	{
8a8d24bd	622	struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
74749f1e	623	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
74749f1e SG	624
74749f1e SG	625	if (!comm) {
53d59694 SG	626	if (spl_phase() > PHASE_TPL)
	627	log_err("Cannot find community for pid %d\n",
	628	pplat->pid);
74749f1e SG	629	return -EDOM;
74749f1e SG	630	}
74749f1e SG	631	priv->comm = comm;
	632	priv->num_cfgs = num_cfgs;
	633
	634	return 0;
	635	}
	636
	637	int intel_pinctrl_probe(struct udevice *dev)
	638	{
	639	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
6b651486	640	int ret;
74749f1e SG	641
74749f1e SG	642	priv->itss_pol_cfg = true;
6b651486 SG	643	ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
	644	if (ret)
	645	return log_msg_ret("Cannot find ITSS", ret);
74749f1e SG	646
	647	return 0;
	648	}
	649
	650	const struct pinctrl_ops intel_pinctrl_ops = {
	651	/* No operations are supported, but DM expects this to be present */
	652	};