[J-u-boot.git] / include / configs / pm9263.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * Configuation settings for the RONETIX PM9263 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * SoC must be defined first, before hardware.h is included.
 * In this case SoC is defined in boards.cfg.
 */
#include <asm/hardware.h>

/* ARM asynchronous clock */

#define MASTER_PLL_DIV		6
#define MASTER_PLL_MUL		65
#define MAIN_PLL_DIV		2	/* 2 or 4 */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */

#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
#define CONFIG_PM9263		1	/* on a Ronetix PM9263 Board	*/
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_TEXT_BASE	0

#define MACH_TYPE_PM9263	1475
#define CONFIG_MACH_TYPE	MACH_TYPE_PM9263

/* clocks */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOR_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_PLLXR_OUT(3) |				\
		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
		 (2 << 28) |		/* PLL Clock Frequency Range */	\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))

#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_MCKR_CSS_SLOW |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_MCKR_CSS_PLLA |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)
#else
/* PCK/4 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL			\
		(AT91_PMC_MCKR_CSS_SLOW |		\
		 AT91_PMC_MCKR_PRES_1 |		\
		 AT91_PMC_MCKR_MDIV_4)
/* PCK/4 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL			\
		(AT91_PMC_MCKR_CSS_PLLA |		\
		 AT91_PMC_MCKR_PRES_1 |		\
		 AT91_PMC_MCKR_MDIV_4)
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
	 AT91_MATRIX_CSA_EBI_CS1A)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		0
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_2 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_CR_PROCRST |		\
		AT91_RSTC_MR_ERSTL(1) |	\
		AT91_RSTC_MR_ERSTL(2))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |					\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_USER_LOWLEVEL_INIT	1

/*
 * Hardware drivers
 */
#define CONFIG_AT91_GPIO	1
#define CONFIG_ATMEL_USART	1
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define	CONFIG_USART_ID			ATMEL_ID_SYS

/* LCD */
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_SYS_WHITE_ON_BLACK	1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1

#define CONFIG_LCD_IN_PSRAM		1

/* LED */
#define CONFIG_AT91_LED
#define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
#define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1
#define CONFIG_BOOTP_BOOTPATH		1
#define CONFIG_BOOTP_GATEWAY		1
#define CONFIG_BOOTP_HOSTNAME		1

/*
 * Command line configuration.
 */
#define CONFIG_CMD_NAND		1

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM		0x20000000
#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */

/* DataFlash */
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_HAS_DATAFLASH			1
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
#define AT91_SPI_CLK				15000000
#define DATAFLASH_TCSS				(0x1a << 16)
#define DATAFLASH_TCHS				(0x1 << 24)

/* NOR flash, if populated */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define PHYS_FLASH_1			0x10000000
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MAX_FLASH_BANKS	1

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)

#endif

#define CONFIG_CMD_JFFS2		1
#define CONFIG_JFFS2_CMDLINE		1
#define CONFIG_JFFS2_NAND		1
#define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/

/* PSRAM */
#define	PHYS_PSRAM			0x70000000
#define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
/* Slave EBI1, PSRAM connected */
#define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))

/* Ethernet */
#define CONFIG_MACB			1
#define CONFIG_RMII			1
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R		1

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW			1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#define CONFIG_SYS_USE_FLASH	1
#undef CONFIG_SYS_USE_DATAFLASH
#undef CONFIG_SYS_USE_NANDFLASH

#ifdef CONFIG_SYS_USE_DATAFLASH

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_IS_IN_DATAFLASH
#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
				"root=/dev/mtdblock0 " \
				"mtdparts=atmel_nand:-(root) "\
				"rw rootfstype=jffs2"

#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "		\
				"root=/dev/mtdblock5 "		\
				"mtdparts=atmel_nand:"		\
					"128k(bootstrap)ro,"	\
					"256k(uboot)ro,"	\
					"128k(env1)ro,"		\
					"128k(env2)ro,"		\
					"2M(linux),"		\
					"-(root) "		\
				"rw rootfstype=jffs2"

#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET	0x40000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define	CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_OVERWRITE	1

/* JFFS Partition offset set */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11

#define CONFIG_BOOTCOMMAND		"run flashboot"
#define CONFIG_ROOTPATH			"/ronetix/rootfs"

#define CONFIG_CON_ROT			"fbcon=rotate:3 "
#define CONFIG_BOOTARGS			"root=/dev/mtdblock4 rootfstype=jffs2 "\
					CONFIG_CON_ROT

#define MTDIDS_DEFAULT			"nor0=physmap-flash.0,nand0=nand"
#define MTDPARTS_DEFAULT		\
	"mtdparts=physmap-flash.0:"	\
		"256k(u-boot)ro,"	\
		"64k(u-boot-env)ro,"	\
		"1408k(kernel),"	\
		"-(rootfs);"		\
	"nand:-(nand)"

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
		CONFIG_CON_ROT					\
		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
	"addip=setenv bootargs $(bootargs) "			\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
		":$(hostname):eth0:off\0"			\
	"ramboot=tftpboot 0x22000000 vmImage;"			\
		"run ramargs;run addip;bootm 22000000\0"	\
	"nfsboot=tftpboot 0x22000000 vmImage;"			\
		"run nfsargs;run addip;bootm 22000000\0"	\
	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
	""

#else
#error "Undefined memory device"
#endif

#define CONFIG_BAUDRATE			115200

#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING		1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)

#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
				GENERATED_GBL_DATA_SIZE)

#endif
Commit	Line	Data
f0a2c7b4 II	1	/*
f0a2c7b4 II	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <[email protected]>
f0a2c7b4 II	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Ilko Iliev <www.ronetix.at>
	6	*
	7	* Configuation settings for the RONETIX PM9263 board.
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
f0a2c7b4 II	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
684a567a AD	15	/*
	16	* SoC must be defined first, before hardware.h is included.
	17	* In this case SoC is defined in boards.cfg.
	18	*/
	19	#include <asm/hardware.h>
	20
f0a2c7b4	21	/* ARM asynchronous clock */
f0a2c7b4	22
01550a2b JCPV	23	#define MASTER_PLL_DIV 6
01550a2b JCPV	24	#define MASTER_PLL_MUL 65
f0a2c7b4	25	#define MAIN_PLL_DIV 2 /* 2 or 4 */
7c966a8b	26	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
684a567a	27	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
f0a2c7b4	28
684a567a	29	#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
f0a2c7b4 II	30	#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
f0a2c7b4 II	31	#define CONFIG_ARCH_CPU_INIT
9a2a05a4	32	#define CONFIG_SYS_TEXT_BASE 0
f0a2c7b4	33
a3e09cc2 AD	34	#define MACH_TYPE_PM9263 1475
	35	#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
	36
f0a2c7b4	37	/* clocks */
01550a2b	38	#define CONFIG_SYS_MOR_VAL \
20d98c2c	39	(AT91_PMC_MOR_MOSCEN \| \
01550a2b JCPV	40	(255 << 8)) /* Main Oscillator Start-up Time */
01550a2b JCPV	41	#define CONFIG_SYS_PLLAR_VAL \
20d98c2c AD	42	(AT91_PMC_PLLAR_29 \| /* Bit 29 must be 1 when prog */ \
	43	AT91_PMC_PLLXR_OUT(3) \| \
	44	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \| /* PLL Counter */\
01550a2b JCPV	45	(2 << 28) \| /* PLL Clock Frequency Range */ \
01550a2b JCPV	46	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
f0a2c7b4 II	47
	48	#if (MAIN_PLL_DIV == 2)
	49	/* PCK/2 = MCK Master Clock from PLLA */
01550a2b	50	#define CONFIG_SYS_MCKR1_VAL \
20d98c2c AD	51	(AT91_PMC_MCKR_CSS_SLOW \| \
	52	AT91_PMC_MCKR_PRES_1 \| \
	53	AT91_PMC_MCKR_MDIV_2)
f0a2c7b4	54	/* PCK/2 = MCK Master Clock from PLLA */
01550a2b	55	#define CONFIG_SYS_MCKR2_VAL \
20d98c2c AD	56	(AT91_PMC_MCKR_CSS_PLLA \| \
	57	AT91_PMC_MCKR_PRES_1 \| \
	58	AT91_PMC_MCKR_MDIV_2)
f0a2c7b4 II	59	#else
f0a2c7b4 II	60	/* PCK/4 = MCK Master Clock from PLLA */
01550a2b	61	#define CONFIG_SYS_MCKR1_VAL \
20d98c2c AD	62	(AT91_PMC_MCKR_CSS_SLOW \| \
	63	AT91_PMC_MCKR_PRES_1 \| \
	64	AT91_PMC_MCKR_MDIV_4)
f0a2c7b4	65	/* PCK/4 = MCK Master Clock from PLLA */
01550a2b	66	#define CONFIG_SYS_MCKR2_VAL \
20d98c2c AD	67	(AT91_PMC_MCKR_CSS_PLLA \| \
	68	AT91_PMC_MCKR_PRES_1 \| \
	69	AT91_PMC_MCKR_MDIV_4)
f0a2c7b4 II	70	#endif
	71	/* define PDC[31:16] as DATA[31:16] */
	72	#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
	73	/* no pull-up for D[31:16] */
	74	#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
	75	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
01550a2b	76	#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
20d98c2c AD	77	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V \| \
20d98c2c AD	78	AT91_MATRIX_CSA_EBI_CS1A)
f0a2c7b4 II	79
	80	/* SDRAM */
	81	/* SDRAMC_MR Mode register */
	82	#define CONFIG_SYS_SDRC_MR_VAL1 0
	83	/* SDRAMC_TR - Refresh Timer register */
01550a2b JCPV	84	#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
	85	/* SDRAMC_CR - Configuration register*/
	86	#define CONFIG_SYS_SDRC_CR_VAL \
	87	(AT91_SDRAMC_NC_9 \| \
	88	AT91_SDRAMC_NR_13 \| \
	89	AT91_SDRAMC_NB_4 \| \
	90	AT91_SDRAMC_CAS_2 \| \
	91	AT91_SDRAMC_DBW_32 \| \
	92	(2 << 8) \| /* tWR - Write Recovery Delay */ \
	93	(7 << 12) \| /* tRC - Row Cycle Delay */ \
	94	(2 << 16) \| /* tRP - Row Precharge Delay */ \
	95	(2 << 20) \| /* tRCD - Row to Column Delay */ \
	96	(5 << 24) \| /* tRAS - Active to Precharge Delay */ \
	97	(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
	98
f0a2c7b4	99	/* Memory Device Register -> SDRAM */
01550a2b JCPV	100	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
01550a2b JCPV	101	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
f0a2c7b4	102	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
01550a2b	103	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
f0a2c7b4 II	104	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
	105	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
	106	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
	107	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
	108	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
	109	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
	110	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
	111	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
01550a2b	112	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
f0a2c7b4	113	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
01550a2b	114	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
f0a2c7b4 II	115	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
	116	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
	117	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
	118
	119	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
01550a2b	120	#define CONFIG_SYS_SMC0_SETUP0_VAL \
20d98c2c AD	121	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
20d98c2c AD	122	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
01550a2b	123	#define CONFIG_SYS_SMC0_PULSE0_VAL \
20d98c2c AD	124	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
20d98c2c AD	125	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
01550a2b	126	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
20d98c2c	127	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
01550a2b	128	#define CONFIG_SYS_SMC0_MODE0_VAL \
20d98c2c AD	129	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	130	AT91_SMC_MODE_DBW_16 \| \
	131	AT91_SMC_MODE_TDF \| \
	132	AT91_SMC_MODE_TDF_CYCLE(6))
f0a2c7b4	133
01550a2b JCPV	134	/* user reset enable */
	135	#define CONFIG_SYS_RSTC_RMR_VAL \
	136	(AT91_RSTC_KEY \| \
20d98c2c AD	137	AT91_RSTC_CR_PROCRST \| \
	138	AT91_RSTC_MR_ERSTL(1) \| \
	139	AT91_RSTC_MR_ERSTL(2))
f0a2c7b4	140
01550a2b JCPV	141	/* Disable Watchdog */
01550a2b JCPV	142	#define CONFIG_SYS_WDTC_WDMR_VAL \
20d98c2c AD	143	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	144	AT91_WDT_MR_WDV(0xfff) \| \
	145	AT91_WDT_MR_WDDIS \| \
	146	AT91_WDT_MR_WDD(0xfff))
f0a2c7b4 II	147
	148	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	149	#define CONFIG_SETUP_MEMORY_TAGS 1
	150	#define CONFIG_INITRD_TAG 1
	151
	152	#undef CONFIG_SKIP_LOWLEVEL_INIT
f0a2c7b4 II	153	#define CONFIG_USER_LOWLEVEL_INIT 1
	154
	155	/*
	156	* Hardware drivers
	157	*/
ea8fbba7	158	#define CONFIG_AT91_GPIO 1
f0a2c7b4	159	#define CONFIG_ATMEL_USART 1
684a567a AD	160	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
684a567a AD	161	#define CONFIG_USART_ID ATMEL_ID_SYS
f0a2c7b4 II	162
f0a2c7b4 II	163	/* LCD */
f0a2c7b4 II	164	#define LCD_BPP LCD_COLOR8
	165	#define CONFIG_LCD_LOGO 1
	166	#undef LCD_TEST_PATTERN
	167	#define CONFIG_LCD_INFO 1
	168	#define CONFIG_LCD_INFO_BELOW_LOGO 1
	169	#define CONFIG_SYS_WHITE_ON_BLACK 1
	170	#define CONFIG_ATMEL_LCD 1
	171	#define CONFIG_ATMEL_LCD_BGR555 1
f0a2c7b4 II	172
	173	#define CONFIG_LCD_IN_PSRAM 1
	174
	175	/* LED */
	176	#define CONFIG_AT91_LED
bcf9fe37 AB	177	#define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */
bcf9fe37 AB	178	#define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */
f0a2c7b4	179
f0a2c7b4 II	180
	181	/*
	182	* BOOTP options
	183	*/
	184	#define CONFIG_BOOTP_BOOTFILESIZE 1
	185	#define CONFIG_BOOTP_BOOTPATH 1
	186	#define CONFIG_BOOTP_GATEWAY 1
	187	#define CONFIG_BOOTP_HOSTNAME 1
	188
	189	/*
	190	* Command line configuration.
	191	*/
f0a2c7b4	192	#define CONFIG_CMD_NAND 1
f0a2c7b4 II	193
	194	/* SDRAM */
	195	#define CONFIG_NR_DRAM_BANKS 1
	196	#define PHYS_SDRAM 0x20000000
	197	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	198
	199	/* DataFlash */
	200	#define CONFIG_ATMEL_DATAFLASH_SPI
	201	#define CONFIG_HAS_DATAFLASH 1
f0a2c7b4 II	202	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
	203	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
	204	#define AT91_SPI_CLK 15000000
	205	#define DATAFLASH_TCSS (0x1a << 16)
	206	#define DATAFLASH_TCHS (0x1 << 24)
	207
	208	/* NOR flash, if populated */
	209	#define CONFIG_SYS_FLASH_CFI 1
	210	#define CONFIG_FLASH_CFI_DRIVER 1
	211	#define PHYS_FLASH_1 0x10000000
	212	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	213	#define CONFIG_SYS_MAX_FLASH_SECT 256
	214	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	215
	216	/* NAND flash */
	217	#ifdef CONFIG_CMD_NAND
	218	#define CONFIG_NAND_ATMEL
f0a2c7b4 II	219	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	220	#define CONFIG_SYS_NAND_BASE 0x40000000
	221	#define CONFIG_SYS_NAND_DBW_8 1
	222	/* our ALE is AD21 */
	223	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	224	/* our CLE is AD22 */
	225	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
ac45bb16 AB	226	#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
ac45bb16 AB	227	#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
2eb99ca8	228
f0a2c7b4 II	229	#endif
	230
	231	#define CONFIG_CMD_JFFS2 1
	232	#define CONFIG_JFFS2_CMDLINE 1
	233	#define CONFIG_JFFS2_NAND 1
	234	#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
	235	#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
	236	#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
	237
	238	/* PSRAM */
	239	#define PHYS_PSRAM 0x70000000
	240	#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
20d98c2c AD	241	/* Slave EBI1, PSRAM connected */
	242	#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY \| \
	243	AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) \| \
	244	AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED \| \
	245	AT91_MATRIX_SCFG_SLOT_CYCLE(255))
f0a2c7b4 II	246
	247	/* Ethernet */
	248	#define CONFIG_MACB 1
	249	#define CONFIG_RMII 1
f0a2c7b4 II	250	#define CONFIG_NET_RETRY_COUNT 20
	251	#define CONFIG_RESET_PHY_R 1
	252
	253	/* USB */
	254	#define CONFIG_USB_ATMEL
dcd2f1a0	255	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
f0a2c7b4	256	#define CONFIG_USB_OHCI_NEW 1
f0a2c7b4 II	257	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	258	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
	259	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
	260	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
f0a2c7b4 II	261
	262	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	263
	264	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
	265	#define CONFIG_SYS_MEMTEST_END 0x23e00000
	266
	267	#define CONFIG_SYS_USE_FLASH 1
	268	#undef CONFIG_SYS_USE_DATAFLASH
	269	#undef CONFIG_SYS_USE_NANDFLASH
	270
	271	#ifdef CONFIG_SYS_USE_DATAFLASH
	272
	273	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
	274	#define CONFIG_ENV_IS_IN_DATAFLASH
	275	#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
	276	#define CONFIG_ENV_OFFSET 0x4200
	277	#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
	278	#define CONFIG_ENV_SIZE 0x4200
	279	#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
	280	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	281	"root=/dev/mtdblock0 " \
918319c7	282	"mtdparts=atmel_nand:-(root) "\
f0a2c7b4 II	283	"rw rootfstype=jffs2"
	284
	285	#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
	286
	287	/* bootstrap + u-boot + env + linux in nandflash */
	288	#define CONFIG_ENV_IS_IN_NAND
	289	#define CONFIG_ENV_OFFSET 0x60000
	290	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	291	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
	292	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
	293	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	294	"root=/dev/mtdblock5 " \
918319c7	295	"mtdparts=atmel_nand:" \
f0a2c7b4 II	296	"128k(bootstrap)ro," \
	297	"256k(uboot)ro," \
	298	"128k(env1)ro," \
	299	"128k(env2)ro," \
	300	"2M(linux)," \
	301	"-(root) " \
	302	"rw rootfstype=jffs2"
	303
	304	#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
	305
	306	#define CONFIG_ENV_IS_IN_FLASH 1
	307	#define CONFIG_ENV_OFFSET 0x40000
	308	#define CONFIG_ENV_SECT_SIZE 0x10000
	309	#define CONFIG_ENV_SIZE 0x10000
	310	#define CONFIG_ENV_OVERWRITE 1
	311
	312	/* JFFS Partition offset set */
	313	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	314	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	315
	316	/* 512k reserved for u-boot */
	317	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
	318
	319	#define CONFIG_BOOTCOMMAND "run flashboot"
8b3637c6	320	#define CONFIG_ROOTPATH "/ronetix/rootfs"
f0a2c7b4 II	321
	322	#define CONFIG_CON_ROT "fbcon=rotate:3 "
	323	#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
	324	CONFIG_CON_ROT
	325
	326	#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
	327	#define MTDPARTS_DEFAULT \
	328	"mtdparts=physmap-flash.0:" \
	329	"256k(u-boot)ro," \
	330	"64k(u-boot-env)ro," \
	331	"1408k(kernel)," \
	332	"-(rootfs);" \
	333	"nand:-(nand)"
	334
	335	#define CONFIG_EXTRA_ENV_SETTINGS \
	336	"mtdids=" MTDIDS_DEFAULT "\0" \
	337	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	338	"partition=nand0,0\0" \
	339	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	340	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	341	CONFIG_CON_ROT \
	342	"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
	343	"addip=setenv bootargs $(bootargs) " \
	344	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
	345	":$(hostname):eth0:off\0" \
	346	"ramboot=tftpboot 0x22000000 vmImage;" \
	347	"run ramargs;run addip;bootm 22000000\0" \
	348	"nfsboot=tftpboot 0x22000000 vmImage;" \
	349	"run nfsargs;run addip;bootm 22000000\0" \
	350	"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
	351	""
	352
	353	#else
	354	#error "Undefined memory device"
	355	#endif
	356
	357	#define CONFIG_BAUDRATE 115200
f0a2c7b4	358
f0a2c7b4 II	359	#define CONFIG_SYS_CBSIZE 256
	360	#define CONFIG_SYS_MAXARGS 16
	361	#define CONFIG_SYS_PBSIZE \
	362	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	363	#define CONFIG_SYS_LONGHELP 1
	364	#define CONFIG_CMDLINE_EDITING 1
	365
f0a2c7b4 II	366	/*
	367	* Size of malloc() pool
	368	*/
	369	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
f0a2c7b4	370
9a2a05a4 AD	371	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	372	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
	373	GENERATED_GBL_DATA_SIZE)
	374
f0a2c7b4	375	#endif