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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
c609719b WD |
2 | /* |
3 | * (C) Copyright 2002 | |
4 | * Rich Ireland, Enterasys Networks, [email protected]. | |
c609719b WD |
5 | */ |
6 | ||
7 | #include <fpga.h> | |
8 | ||
9 | #ifndef _XILINX_H_ | |
10 | #define _XILINX_H_ | |
11 | ||
c609719b WD |
12 | /* Xilinx types |
13 | *********************************************************************/ | |
2df9d5c4 | 14 | typedef enum { /* typedef xilinx_iface */ |
53677ef1 WD |
15 | min_xilinx_iface_type, /* low range check value */ |
16 | slave_serial, /* serial data and external clock */ | |
17 | master_serial, /* serial data w/ internal clock (not used) */ | |
18 | slave_parallel, /* parallel data w/ external latch */ | |
19 | jtag_mode, /* jtag/tap serial (not used ) */ | |
20 | master_selectmap, /* master SelectMap (virtex2) */ | |
21 | slave_selectmap, /* slave SelectMap (virtex2) */ | |
d5dae85f | 22 | devcfg, /* devcfg interface (zynq) */ |
6b245014 | 23 | csu_dma, /* csu_dma interface (zynqmp) */ |
26e054c9 | 24 | cfi, /* CFI interface(versal) */ |
53677ef1 | 25 | max_xilinx_iface_type /* insert all new types before this */ |
2df9d5c4 | 26 | } xilinx_iface; /* end, typedef xilinx_iface */ |
c609719b | 27 | |
2df9d5c4 | 28 | typedef enum { /* typedef xilinx_family */ |
53677ef1 | 29 | min_xilinx_type, /* low range check value */ |
b625b9ae | 30 | xilinx_spartan2, /* Spartan-II Family */ |
2df9d5c4 | 31 | xilinx_virtexE, /* Virtex-E Family */ |
d9071ce0 | 32 | xilinx_virtex2, /* Virtex2 Family */ |
2a6e3869 | 33 | xilinx_spartan3, /* Spartan-III Family */ |
d5dae85f | 34 | xilinx_zynq, /* Zynq Family */ |
6b245014 | 35 | xilinx_zynqmp, /* ZynqMP Family */ |
26e054c9 | 36 | xilinx_versal, /* Versal Family */ |
53677ef1 | 37 | max_xilinx_type /* insert all new types before this */ |
2df9d5c4 | 38 | } xilinx_family; /* end, typedef xilinx_family */ |
c609719b | 39 | |
d7fcbfc1 OS |
40 | /* FPGA bitstream supported types */ |
41 | #define FPGA_LEGACY BIT(0) | |
a3a1afb7 | 42 | #define FPGA_XILINX_ZYNQMP_DDRAUTH BIT(1) |
b524f8fb | 43 | #define FPGA_XILINX_ZYNQMP_ENC BIT(2) |
d7fcbfc1 | 44 | |
f8c1be98 | 45 | typedef struct { /* typedef xilinx_desc */ |
2df9d5c4 MS |
46 | xilinx_family family; /* part type */ |
47 | xilinx_iface iface; /* interface type */ | |
53677ef1 WD |
48 | size_t size; /* bytes of data part can accept */ |
49 | void *iface_fns; /* interface function table */ | |
50 | int cookie; /* implementation specific cookie */ | |
14cfc4f3 | 51 | struct xilinx_fpga_op *operations; /* operations */ |
6631db47 | 52 | char *name; /* device name in bitstream */ |
d7fcbfc1 | 53 | int flags; /* compatible flags */ |
f8c1be98 | 54 | } xilinx_desc; /* end, typedef xilinx_desc */ |
c609719b | 55 | |
14cfc4f3 | 56 | struct xilinx_fpga_op { |
f18adf10 | 57 | int (*load)(xilinx_desc *desc, const void *buf, size_t bsize, |
3e78481d | 58 | bitstream_type bstype, int flags); |
f18adf10 OS |
59 | int (*loadfs)(xilinx_desc *desc, const void *buf, size_t bsize, |
60 | fpga_fs_info *fpga_fsinfo); | |
a18d09ea SDPP |
61 | int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize, |
62 | struct fpga_secure_info *fpga_sec_info); | |
f18adf10 OS |
63 | int (*dump)(xilinx_desc *desc, const void *buf, size_t bsize); |
64 | int (*info)(xilinx_desc *desc); | |
24307b06 OS |
65 | #if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) |
66 | int (*str2flag)(xilinx_desc *desc, const char *string); | |
67 | #endif | |
14cfc4f3 MS |
68 | }; |
69 | ||
c609719b WD |
70 | /* Generic Xilinx Functions |
71 | *********************************************************************/ | |
7a78bd26 | 72 | int xilinx_load(xilinx_desc *desc, const void *image, size_t size, |
7a9a0df8 | 73 | bitstream_type bstype, int flags); |
f8c1be98 MS |
74 | int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); |
75 | int xilinx_info(xilinx_desc *desc); | |
1a897668 SDPP |
76 | int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, |
77 | fpga_fs_info *fpga_fsinfo); | |
a18d09ea SDPP |
78 | int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, |
79 | struct fpga_secure_info *fpga_sec_info); | |
c609719b WD |
80 | |
81 | /* Board specific implementation specific function types | |
82 | *********************************************************************/ | |
2df9d5c4 MS |
83 | typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie); |
84 | typedef int (*xilinx_init_fn)(int cookie); | |
85 | typedef int (*xilinx_err_fn)(int cookie); | |
86 | typedef int (*xilinx_done_fn)(int cookie); | |
87 | typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie); | |
88 | typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie); | |
89 | typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie); | |
90 | typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie); | |
91 | typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie); | |
92 | typedef int (*xilinx_busy_fn)(int cookie); | |
93 | typedef int (*xilinx_abort_fn)(int cookie); | |
94 | typedef int (*xilinx_pre_fn)(int cookie); | |
95 | typedef int (*xilinx_post_fn)(int cookie); | |
96 | typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie); | |
c609719b WD |
97 | |
98 | #endif /* _XILINX_H_ */ |