[J-u-boot.git] / include / power / max8998_pmic.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *  Copyright (C) 2011 Samsung Electronics
 *  Lukasz Majewski <[email protected]>
 */

#ifndef __MAX8998_PMIC_H_
#define __MAX8998_PMIC_H_

/* MAX 8998 registers */
enum {
	MAX8998_REG_IRQ1,
	MAX8998_REG_IRQ2,
	MAX8998_REG_IRQ3,
	MAX8998_REG_IRQ4,
	MAX8998_REG_IRQM1,
	MAX8998_REG_IRQM2,
	MAX8998_REG_IRQM3,
	MAX8998_REG_IRQM4,
	MAX8998_REG_STATUS1,
	MAX8998_REG_STATUS2,
	MAX8998_REG_STATUSM1,
	MAX8998_REG_STATUSM2,
	MAX8998_REG_CHGR1,
	MAX8998_REG_CHGR2,
	MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
	MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
	MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
	MAX8998_REG_ONOFF1,
	MAX8998_REG_ONOFF2,
	MAX8998_REG_ONOFF3,
	MAX8998_REG_ONOFF4,
	MAX8998_REG_BUCK1_VOLTAGE1,
	MAX8998_REG_BUCK1_VOLTAGE2,
	MAX8998_REG_BUCK1_VOLTAGE3,
	MAX8998_REG_BUCK1_VOLTAGE4,
	MAX8998_REG_BUCK2_VOLTAGE1,
	MAX8998_REG_BUCK2_VOLTAGE2,
	MAX8998_REG_BUCK3,
	MAX8998_REG_BUCK4,
	MAX8998_REG_LDO2_LDO3,
	MAX8998_REG_LDO4,
	MAX8998_REG_LDO5,
	MAX8998_REG_LDO6,
	MAX8998_REG_LDO7,
	MAX8998_REG_LDO8_LDO9,
	MAX8998_REG_LDO10_LDO11,
	MAX8998_REG_LDO12,
	MAX8998_REG_LDO13,
	MAX8998_REG_LDO14,
	MAX8998_REG_LDO15,
	MAX8998_REG_LDO16,
	MAX8998_REG_LDO17,
	MAX8998_REG_BKCHR,
	MAX8998_REG_LBCNFG1,
	MAX8998_REG_LBCNFG2,
	PMIC_NUM_OF_REGS,
};

#define MAX8998_LDO3		(1 << 2)
#define MAX8998_LDO4		(1 << 1)
#define MAX8998_LDO7		(1 << 6)
#define MAX8998_LDO8		(1 << 5)
#define MAX8998_LDO17		(1 << 4)
#define MAX8998_SAFEOUT1	(1 << 4)

#define MAX8998_I2C_ADDR        (0xCC >> 1)

enum { LDO_OFF, LDO_ON };

#endif /* __MAX8998_PMIC_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
99385858 ŁM	2	/*
	3	* Copyright (C) 2011 Samsung Electronics
	4	* Lukasz Majewski <[email protected]>
99385858 ŁM	5	*/
	6
	7	#ifndef __MAX8998_PMIC_H_
	8	#define __MAX8998_PMIC_H_
	9
	10	/* MAX 8998 registers */
	11	enum {
	12	MAX8998_REG_IRQ1,
	13	MAX8998_REG_IRQ2,
	14	MAX8998_REG_IRQ3,
	15	MAX8998_REG_IRQ4,
	16	MAX8998_REG_IRQM1,
	17	MAX8998_REG_IRQM2,
	18	MAX8998_REG_IRQM3,
	19	MAX8998_REG_IRQM4,
	20	MAX8998_REG_STATUS1,
	21	MAX8998_REG_STATUS2,
	22	MAX8998_REG_STATUSM1,
	23	MAX8998_REG_STATUSM2,
	24	MAX8998_REG_CHGR1,
	25	MAX8998_REG_CHGR2,
	26	MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
	27	MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
	28	MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
	29	MAX8998_REG_ONOFF1,
	30	MAX8998_REG_ONOFF2,
	31	MAX8998_REG_ONOFF3,
	32	MAX8998_REG_ONOFF4,
	33	MAX8998_REG_BUCK1_VOLTAGE1,
	34	MAX8998_REG_BUCK1_VOLTAGE2,
	35	MAX8998_REG_BUCK1_VOLTAGE3,
	36	MAX8998_REG_BUCK1_VOLTAGE4,
	37	MAX8998_REG_BUCK2_VOLTAGE1,
	38	MAX8998_REG_BUCK2_VOLTAGE2,
	39	MAX8998_REG_BUCK3,
	40	MAX8998_REG_BUCK4,
	41	MAX8998_REG_LDO2_LDO3,
	42	MAX8998_REG_LDO4,
	43	MAX8998_REG_LDO5,
	44	MAX8998_REG_LDO6,
	45	MAX8998_REG_LDO7,
	46	MAX8998_REG_LDO8_LDO9,
	47	MAX8998_REG_LDO10_LDO11,
	48	MAX8998_REG_LDO12,
	49	MAX8998_REG_LDO13,
	50	MAX8998_REG_LDO14,
	51	MAX8998_REG_LDO15,
	52	MAX8998_REG_LDO16,
	53	MAX8998_REG_LDO17,
	54	MAX8998_REG_BKCHR,
	55	MAX8998_REG_LBCNFG1,
	56	MAX8998_REG_LBCNFG2,
	57	PMIC_NUM_OF_REGS,
	58	};
	59
	60	#define MAX8998_LDO3 (1 << 2)
4d86bf08	61	#define MAX8998_LDO4 (1 << 1)
9e26d8a4	62	#define MAX8998_LDO7 (1 << 6)
99385858	63	#define MAX8998_LDO8 (1 << 5)
9e26d8a4	64	#define MAX8998_LDO17 (1 << 4)
ddc7e541	65	#define MAX8998_SAFEOUT1 (1 << 4)
99385858 ŁM	66
	67	#define MAX8998_I2C_ADDR (0xCC >> 1)
	68
	69	enum { LDO_OFF, LDO_ON };
	70
	71	#endif /* __MAX8998_PMIC_H_ */