[J-u-boot.git] / include / cpsw.h

/*
 * CPSW Ethernet Switch Driver
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#ifndef _CPSW_H_
#define _CPSW_H_

#include <dm/ofnode.h>

/* reg offset */
#define CPSW_HOST_PORT_OFFSET	0x108
#define CPSW_SLAVE0_OFFSET	0x208
#define CPSW_SLAVE1_OFFSET	0x308
#define CPSW_SLAVE_SIZE		0x100
#define CPSW_CPDMA_OFFSET	0x800
#define CPSW_HW_STATS		0x900
#define CPSW_STATERAM_OFFSET	0xa00
#define CPSW_CPTS_OFFSET	0xc00
#define CPSW_ALE_OFFSET		0xd00
#define CPSW_SLIVER0_OFFSET	0xd80
#define CPSW_SLIVER1_OFFSET	0xdc0
#define CPSW_BD_OFFSET		0x2000
#define CPSW_MDIO_DIV		0xff

#define AM335X_GMII_SEL_OFFSET	0x630

struct cpsw_slave_data {
	u32		slave_reg_ofs;
	u32		sliver_reg_ofs;
	int		phy_addr;
	int		phy_if;
	ofnode		phy_of_handle;
	int		max_speed;
};

enum {
	CPSW_CTRL_VERSION_1 = 0,
	CPSW_CTRL_VERSION_2	/* am33xx like devices */
};

struct cpsw_platform_data {
	u32	mdio_base;
	u32	cpsw_base;
	u32	mac_id;
	u32	gmii_sel;
	int	mdio_div;
	int	channels;	/* number of cpdma channels (symmetric)	*/
	u32	cpdma_reg_ofs;	/* cpdma register offset		*/
	int	slaves;		/* number of slave cpgmac ports		*/
	u32	ale_reg_ofs;	/* address lookup engine reg offset	*/
	int	ale_entries;	/* ale table size			*/
	u32	host_port_reg_ofs;	/* cpdma host port registers	*/
	u32	hw_stats_reg_ofs;	/* cpsw hw stats counters	*/
	u32	bd_ram_ofs;		/* Buffer Descriptor RAM offset */
	u32	mac_control;
	struct cpsw_slave_data	*slave_data;
	void	(*control)(int enabled);
	u32	host_port_num;
	u32	active_slave;
	bool	rmii_clock_external;
	u8	version;
	const char *phy_sel_compat;
	u32	syscon_addr;
	const char *macid_sel_compat;
};

int cpsw_register(struct cpsw_platform_data *data);
int ti_cm_get_macid_addr(struct udevice *dev, int slave,
			 struct cpsw_platform_data *data);
void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data,
		     u8 *mac_addr);
int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);

#endif /* _CPSW_H_  */
Commit	Line	Data
2b62997c CC	1	/*
	2	* CPSW Ethernet Switch Driver
	3	*
a94a4071	4	* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
2b62997c CC	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#ifndef _CPSW_H_
	17	#define _CPSW_H_
	18
62f8e846 GS	19	#include <dm/ofnode.h>
62f8e846 GS	20
0229c933 FA	21	/* reg offset */
	22	#define CPSW_HOST_PORT_OFFSET 0x108
	23	#define CPSW_SLAVE0_OFFSET 0x208
	24	#define CPSW_SLAVE1_OFFSET 0x308
	25	#define CPSW_SLAVE_SIZE 0x100
	26	#define CPSW_CPDMA_OFFSET 0x800
	27	#define CPSW_HW_STATS 0x900
	28	#define CPSW_STATERAM_OFFSET 0xa00
	29	#define CPSW_CPTS_OFFSET 0xc00
	30	#define CPSW_ALE_OFFSET 0xd00
	31	#define CPSW_SLIVER0_OFFSET 0xd80
	32	#define CPSW_SLIVER1_OFFSET 0xdc0
	33	#define CPSW_BD_OFFSET 0x2000
	34	#define CPSW_MDIO_DIV 0xff
	35
	36	#define AM335X_GMII_SEL_OFFSET 0x630
	37
2b62997c CC	38	struct cpsw_slave_data {
	39	u32 slave_reg_ofs;
	40	u32 sliver_reg_ofs;
9c653aad	41	int phy_addr;
2b62997c	42	int phy_if;
62f8e846	43	ofnode phy_of_handle;
3c57b620	44	int max_speed;
2b62997c CC	45	};
	46
	47	enum {
	48	CPSW_CTRL_VERSION_1 = 0,
	49	CPSW_CTRL_VERSION_2 /* am33xx like devices */
	50	};
	51
	52	struct cpsw_platform_data {
	53	u32 mdio_base;
	54	u32 cpsw_base;
4cc77895 M	55	u32 mac_id;
4cc77895 M	56	u32 gmii_sel;
2b62997c CC	57	int mdio_div;
	58	int channels; /* number of cpdma channels (symmetric) */
	59	u32 cpdma_reg_ofs; /* cpdma register offset */
	60	int slaves; /* number of slave cpgmac ports */
	61	u32 ale_reg_ofs; /* address lookup engine reg offset */
	62	int ale_entries; /* ale table size */
	63	u32 host_port_reg_ofs; /* cpdma host port registers */
	64	u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
2bf36ac6	65	u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */
2b62997c CC	66	u32 mac_control;
	67	struct cpsw_slave_data *slave_data;
	68	void (*control)(int enabled);
	69	u32 host_port_num;
7a022753	70	u32 active_slave;
ab971530	71	bool rmii_clock_external;
2b62997c	72	u8 version;
e50f878c	73	const char *phy_sel_compat;
a58d222d FA	74	u32 syscon_addr;
a58d222d FA	75	const char *macid_sel_compat;
2b62997c CC	76	};
	77
	78	int cpsw_register(struct cpsw_platform_data *data);
a58d222d FA	79	int ti_cm_get_macid_addr(struct udevice *dev, int slave,
	80	struct cpsw_platform_data *data);
	81	void ti_cm_get_macid(struct udevice dev, struct cpsw_platform_data data,
	82	u8 *mac_addr);
e2597be5	83	int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);
2b62997c CC	84
2b62997c CC	85	#endif /* _CPSW_H_ */