[J-u-boot.git] / include / armcoremodule.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2005
 * ARM Ltd.
 * Peter Pearse, <[email protected]>
 * Configuration for ARM Core Modules.
 * No standalonw port yet available
 * - this file is included by both integratorap.h & integratorcp.h
 */

#ifndef __ARMCOREMODULE_H
#define __ARMCOREMODULE_H

#define CM_BASE			0x10000000

/* CM registers common to all CMs */
/* Note that observed values after reboot into the ARM Boot Monitor
   have been used as defaults, rather than the POR values */
#define OS_CTRL			0x0000000C
#define CMMASK_REMAP		0x00000005	/* set remap & led           */
#define CMMASK_RESET		0x00000008
#define OS_LOCK			0x00000014
#define CMVAL_LOCK1		0x0000A000	/* locking value             */
#define CMVAL_LOCK2		0x0000005F	/* locking value             */
#define CMVAL_UNLOCK		0x00000000	/* any value != CM_LOCKVAL   */
#define OS_SDRAM		0x00000020
#define OS_INIT			0x00000024
#define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
#define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
#define CMMASK_LOWVEC		0x00000000	/* vectors @ 0x00000000 */
#define CMMASK_LE		0xFFFFFFF7	/* little endian */
#define CMMASK_CMxx6_COMMON	0x00000013      /* Common value for CMxx6 */
						/* - observed reset value of */
						/*   CM926EJ-S */
						/*   CM1136-EJ-S */

#define OS_SPD		0x00000100	/* The SDRAM SPD data is copied here */

#endif /* __ARMCOREMODULE_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
9b880bd4 WD	2	/*
	3	* (C) Copyright 2005
	4	* ARM Ltd.
	5	* Peter Pearse, <[email protected]>
	6	* Configuration for ARM Core Modules.
	7	* No standalonw port yet available
	8	* - this file is included by both integratorap.h & integratorcp.h
9b880bd4 WD	9	*/
	10
	11	#ifndef __ARMCOREMODULE_H
	12	#define __ARMCOREMODULE_H
	13
53677ef1	14	#define CM_BASE 0x10000000
9b880bd4 WD	15
	16	/* CM registers common to all CMs */
	17	/* Note that observed values after reboot into the ARM Boot Monitor
	18	have been used as defaults, rather than the POR values */
53677ef1	19	#define OS_CTRL 0x0000000C
9b880bd4 WD	20	#define CMMASK_REMAP 0x00000005 /* set remap & led */
9b880bd4 WD	21	#define CMMASK_RESET 0x00000008
53677ef1 WD	22	#define OS_LOCK 0x00000014
53677ef1 WD	23	#define CMVAL_LOCK1 0x0000A000 /* locking value */
9b880bd4 WD	24	#define CMVAL_LOCK2 0x0000005F /* locking value */
	25	#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
	26	#define OS_SDRAM 0x00000020
53677ef1	27	#define OS_INIT 0x00000024
9b880bd4 WD	28	#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
	29	#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
	30	#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */
	31	#define CMMASK_LE 0xFFFFFFF7 /* little endian */
	32	#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */
	33	/* - observed reset value of */
	34	/* CM926EJ-S */
	35	/* CM1136-EJ-S */
	36
9b880bd4	37	#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
9b880bd4 WD	38
9b880bd4 WD	39	#endif /* __ARMCOREMODULE_H */