[J-u-boot.git] / drivers / power / ftpmu010.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009 Faraday Technology
 * Po-Yu Chuang <[email protected]>
 *
 * Copyright (C) 2010 Andes Technology Corporation
 * Shawn Lin, Andes Technology Corporation <[email protected]>
 * Macpaul Lin, Andes Technology Corporation <[email protected]>
 */

#include <common.h>
#include <asm/io.h>
#include <faraday/ftpmu010.h>

/* OSCC: OSC Control Register */
void ftpmu010_32768osc_enable(void)
{
	static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
	unsigned int oscc;

	/* enable the 32768Hz oscillator */
	oscc = readl(&pmu->OSCC);
	oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
	writel(oscc, &pmu->OSCC);

	/* wait until ready */
	while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
		;

	/* select 32768Hz oscillator */
	oscc = readl(&pmu->OSCC);
	oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
	writel(oscc, &pmu->OSCC);
}

/* MFPSR: Multi-Function Port Setting Register */
void ftpmu010_mfpsr_select_dev(unsigned int dev)
{
	static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
	unsigned int mfpsr;

	mfpsr = readl(&pmu->MFPSR);
	mfpsr |= dev;
	writel(mfpsr, &pmu->MFPSR);
}

void ftpmu010_mfpsr_diselect_dev(unsigned int dev)
{
	static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
	unsigned int mfpsr;

	mfpsr = readl(&pmu->MFPSR);
	mfpsr &= ~dev;
	writel(mfpsr, &pmu->MFPSR);
}

/* PDLLCR0: PLL/DLL Control Register 0 */
void ftpmu010_dlldis_disable(void)
{
	static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
	unsigned int pdllcr0;

	pdllcr0 = readl(&pmu->PDLLCR0);
	pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS;
	writel(pdllcr0, &pmu->PDLLCR0);
}

void ftpmu010_sdram_clk_disable(unsigned int cr0)
{
	static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
	unsigned int pdllcr0;

	pdllcr0 = readl(&pmu->PDLLCR0);
	pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
	writel(pdllcr0, &pmu->PDLLCR0);
}

/* SDRAMHTC: SDRAM Signal Hold Time Control */
void ftpmu010_sdramhtc_set(unsigned int val)
{
	static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
	unsigned int sdramhtc;

	sdramhtc = readl(&pmu->SDRAMHTC);
	sdramhtc |= val;
	writel(sdramhtc, &pmu->SDRAMHTC);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f8ea15f7 ML	2	/*
	3	* (C) Copyright 2009 Faraday Technology
	4	* Po-Yu Chuang <[email protected]>
	5	*
	6	* Copyright (C) 2010 Andes Technology Corporation
	7	* Shawn Lin, Andes Technology Corporation <[email protected]>
	8	* Macpaul Lin, Andes Technology Corporation <[email protected]>
f8ea15f7 ML	9	*/
	10
	11	#include <common.h>
	12	#include <asm/io.h>
d6150db2	13	#include <faraday/ftpmu010.h>
f8ea15f7	14
caddb8e4	15	/* OSCC: OSC Control Register */
f8ea15f7 ML	16	void ftpmu010_32768osc_enable(void)
f8ea15f7 ML	17	{
caddb8e4	18	static struct ftpmu010 pmu = (struct ftpmu010 )CONFIG_FTPMU010_BASE;
f8ea15f7 ML	19	unsigned int oscc;
	20
	21	/* enable the 32768Hz oscillator */
	22	oscc = readl(&pmu->OSCC);
	23	oscc &= ~(FTPMU010_OSCC_OSCL_OFF \| FTPMU010_OSCC_OSCL_TRI);
	24	writel(oscc, &pmu->OSCC);
	25
	26	/* wait until ready */
	27	while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
	28	;
	29
	30	/* select 32768Hz oscillator */
	31	oscc = readl(&pmu->OSCC);
	32	oscc \|= FTPMU010_OSCC_OSCL_RTCLSEL;
	33	writel(oscc, &pmu->OSCC);
	34	}
	35
caddb8e4 ML	36	/* MFPSR: Multi-Function Port Setting Register */
	37	void ftpmu010_mfpsr_select_dev(unsigned int dev)
	38	{
	39	static struct ftpmu010 pmu = (struct ftpmu010 )CONFIG_FTPMU010_BASE;
	40	unsigned int mfpsr;
	41
	42	mfpsr = readl(&pmu->MFPSR);
	43	mfpsr \|= dev;
	44	writel(mfpsr, &pmu->MFPSR);
	45	}
	46
	47	void ftpmu010_mfpsr_diselect_dev(unsigned int dev)
	48	{
	49	static struct ftpmu010 pmu = (struct ftpmu010 )CONFIG_FTPMU010_BASE;
	50	unsigned int mfpsr;
	51
	52	mfpsr = readl(&pmu->MFPSR);
	53	mfpsr &= ~dev;
	54	writel(mfpsr, &pmu->MFPSR);
	55	}
	56
	57	/* PDLLCR0: PLL/DLL Control Register 0 */
f8ea15f7 ML	58	void ftpmu010_dlldis_disable(void)
f8ea15f7 ML	59	{
caddb8e4	60	static struct ftpmu010 pmu = (struct ftpmu010 )CONFIG_FTPMU010_BASE;
f8ea15f7 ML	61	unsigned int pdllcr0;
	62
	63	pdllcr0 = readl(&pmu->PDLLCR0);
	64	pdllcr0 \|= FTPMU010_PDLLCR0_DLLDIS;
	65	writel(pdllcr0, &pmu->PDLLCR0);
	66	}
	67
	68	void ftpmu010_sdram_clk_disable(unsigned int cr0)
	69	{
caddb8e4	70	static struct ftpmu010 pmu = (struct ftpmu010 )CONFIG_FTPMU010_BASE;
f8ea15f7 ML	71	unsigned int pdllcr0;
	72
	73	pdllcr0 = readl(&pmu->PDLLCR0);
	74	pdllcr0 \|= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
	75	writel(pdllcr0, &pmu->PDLLCR0);
	76	}
caddb8e4 ML	77
	78	/* SDRAMHTC: SDRAM Signal Hold Time Control */
	79	void ftpmu010_sdramhtc_set(unsigned int val)
	80	{
	81	static struct ftpmu010 pmu = (struct ftpmu010 )CONFIG_FTPMU010_BASE;
	82	unsigned int sdramhtc;
	83
	84	sdramhtc = readl(&pmu->SDRAMHTC);
	85	sdramhtc \|= val;
	86	writel(sdramhtc, &pmu->SDRAMHTC);
	87	}