[J-u-boot.git] / drivers / net / sunxi_emac.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * sunxi_emac.c -- Allwinner A10 ethernet driver
 *
 * (C) Copyright 2012, Stefan Roese <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <linux/err.h>
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>

/* EMAC register  */
struct emac_regs {
	u32 ctl;	/* 0x00 */
	u32 tx_mode;	/* 0x04 */
	u32 tx_flow;	/* 0x08 */
	u32 tx_ctl0;	/* 0x0c */
	u32 tx_ctl1;	/* 0x10 */
	u32 tx_ins;	/* 0x14 */
	u32 tx_pl0;	/* 0x18 */
	u32 tx_pl1;	/* 0x1c */
	u32 tx_sta;	/* 0x20 */
	u32 tx_io_data;	/* 0x24 */
	u32 tx_io_data1;/* 0x28 */
	u32 tx_tsvl0;	/* 0x2c */
	u32 tx_tsvh0;	/* 0x30 */
	u32 tx_tsvl1;	/* 0x34 */
	u32 tx_tsvh1;	/* 0x38 */
	u32 rx_ctl;	/* 0x3c */
	u32 rx_hash0;	/* 0x40 */
	u32 rx_hash1;	/* 0x44 */
	u32 rx_sta;	/* 0x48 */
	u32 rx_io_data;	/* 0x4c */
	u32 rx_fbc;	/* 0x50 */
	u32 int_ctl;	/* 0x54 */
	u32 int_sta;	/* 0x58 */
	u32 mac_ctl0;	/* 0x5c */
	u32 mac_ctl1;	/* 0x60 */
	u32 mac_ipgt;	/* 0x64 */
	u32 mac_ipgr;	/* 0x68 */
	u32 mac_clrt;	/* 0x6c */
	u32 mac_maxf;	/* 0x70 */
	u32 mac_supp;	/* 0x74 */
	u32 mac_test;	/* 0x78 */
	u32 mac_mcfg;	/* 0x7c */
	u32 mac_mcmd;	/* 0x80 */
	u32 mac_madr;	/* 0x84 */
	u32 mac_mwtd;	/* 0x88 */
	u32 mac_mrdd;	/* 0x8c */
	u32 mac_mind;	/* 0x90 */
	u32 mac_ssrr;	/* 0x94 */
	u32 mac_a0;	/* 0x98 */
	u32 mac_a1;	/* 0x9c */
};

/* SRAMC register  */
struct sunxi_sramc_regs {
	u32 ctrl0;
	u32 ctrl1;
};

/* 0: Disable       1: Aborted frame enable(default) */
#define EMAC_TX_AB_M		(0x1 << 0)
/* 0: CPU           1: DMA(default) */
#define EMAC_TX_TM		(0x1 << 1)

#define EMAC_TX_SETUP		(0)

/* 0: DRQ asserted  1: DRQ automatically(default) */
#define EMAC_RX_DRQ_MODE	(0x1 << 1)
/* 0: CPU           1: DMA(default) */
#define EMAC_RX_TM		(0x1 << 2)
/* 0: Normal(default)        1: Pass all Frames */
#define EMAC_RX_PA		(0x1 << 4)
/* 0: Normal(default)        1: Pass Control Frames */
#define EMAC_RX_PCF		(0x1 << 5)
/* 0: Normal(default)        1: Pass Frames with CRC Error */
#define EMAC_RX_PCRCE		(0x1 << 6)
/* 0: Normal(default)        1: Pass Frames with Length Error */
#define EMAC_RX_PLE		(0x1 << 7)
/* 0: Normal                 1: Pass Frames length out of range(default) */
#define EMAC_RX_POR		(0x1 << 8)
/* 0: Not accept             1: Accept unicast Packets(default) */
#define EMAC_RX_UCAD		(0x1 << 16)
/* 0: Normal(default)        1: DA Filtering */
#define EMAC_RX_DAF		(0x1 << 17)
/* 0: Not accept             1: Accept multicast Packets(default) */
#define EMAC_RX_MCO		(0x1 << 20)
/* 0: Disable(default)       1: Enable Hash filter */
#define EMAC_RX_MHF		(0x1 << 21)
/* 0: Not accept             1: Accept Broadcast Packets(default) */
#define EMAC_RX_BCO		(0x1 << 22)
/* 0: Disable(default)       1: Enable SA Filtering */
#define EMAC_RX_SAF		(0x1 << 24)
/* 0: Normal(default)        1: Inverse Filtering */
#define EMAC_RX_SAIF		(0x1 << 25)

#define EMAC_RX_SETUP		(EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
				 EMAC_RX_MCO | EMAC_RX_BCO)

/* 0: Disable                1: Enable Receive Flow Control(default) */
#define EMAC_MAC_CTL0_RFC	(0x1 << 2)
/* 0: Disable                1: Enable Transmit Flow Control(default) */
#define EMAC_MAC_CTL0_TFC	(0x1 << 3)

#define EMAC_MAC_CTL0_SETUP	(EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)

/* 0: Disable                1: Enable MAC Frame Length Checking(default) */
#define EMAC_MAC_CTL1_FLC	(0x1 << 1)
/* 0: Disable(default)       1: Enable Huge Frame */
#define EMAC_MAC_CTL1_HF	(0x1 << 2)
/* 0: Disable(default)       1: Enable MAC Delayed CRC */
#define EMAC_MAC_CTL1_DCRC	(0x1 << 3)
/* 0: Disable                1: Enable MAC CRC(default) */
#define EMAC_MAC_CTL1_CRC	(0x1 << 4)
/* 0: Disable                1: Enable MAC PAD Short frames(default) */
#define EMAC_MAC_CTL1_PC	(0x1 << 5)
/* 0: Disable(default)       1: Enable MAC PAD Short frames and append CRC */
#define EMAC_MAC_CTL1_VC	(0x1 << 6)
/* 0: Disable(default)       1: Enable MAC auto detect Short frames */
#define EMAC_MAC_CTL1_ADP	(0x1 << 7)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_PRE	(0x1 << 8)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_LPE	(0x1 << 9)
/* 0: Disable(default)       1: Enable no back off */
#define EMAC_MAC_CTL1_NB	(0x1 << 12)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_BNB	(0x1 << 13)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_ED	(0x1 << 14)

#define EMAC_MAC_CTL1_SETUP	(EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
				 EMAC_MAC_CTL1_PC)

#define EMAC_MAC_IPGT		0x15

#define EMAC_MAC_NBTB_IPG1	0xc
#define EMAC_MAC_NBTB_IPG2	0x12

#define EMAC_MAC_CW		0x37
#define EMAC_MAC_RM		0xf

#define EMAC_MAC_MFL		0x0600

/* Receive status */
#define EMAC_CRCERR		(0x1 << 4)
#define EMAC_LENERR		(0x3 << 5)

#define EMAC_RX_BUFSIZE		2000

struct emac_eth_dev {
	struct emac_regs *regs;
	struct clk clk;
	struct mii_dev *bus;
	struct phy_device *phydev;
	int link_printed;
#ifdef CONFIG_DM_ETH
	uchar rx_buf[EMAC_RX_BUFSIZE];
#endif
};

struct emac_rxhdr {
	s16 rx_len;
	u16 rx_status;
};

static void emac_inblk_32bit(void *reg, void *data, int count)
{
	int cnt = (count + 3) >> 2;

	if (cnt) {
		u32 *buf = data;

		do {
			u32 x = readl(reg);
			*buf++ = x;
		} while (--cnt);
	}
}

static void emac_outblk_32bit(void *reg, void *data, int count)
{
	int cnt = (count + 3) >> 2;

	if (cnt) {
		const u32 *buf = data;

		do {
			writel(*buf++, reg);
		} while (--cnt);
	}
}

/* Read a word from phyxcer */
static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	struct emac_eth_dev *priv = bus->priv;
	struct emac_regs *regs = priv->regs;

	/* issue the phy address and reg */
	writel(addr << 8 | reg, &regs->mac_madr);

	/* pull up the phy io line */
	writel(0x1, &regs->mac_mcmd);

	/* Wait read complete */
	mdelay(1);

	/* push down the phy io line */
	writel(0x0, &regs->mac_mcmd);

	/* And read data */
	return readl(&regs->mac_mrdd);
}

/* Write a word to phyxcer */
static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
			  u16 value)
{
	struct emac_eth_dev *priv = bus->priv;
	struct emac_regs *regs = priv->regs;

	/* issue the phy address and reg */
	writel(addr << 8 | reg, &regs->mac_madr);

	/* pull up the phy io line */
	writel(0x1, &regs->mac_mcmd);

	/* Wait write complete */
	mdelay(1);

	/* push down the phy io line */
	writel(0x0, &regs->mac_mcmd);

	/* and write data */
	writel(value, &regs->mac_mwtd);

	return 0;
}

static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
{
	int ret, mask = 0xffffffff;

#ifdef CONFIG_PHY_ADDR
	mask = 1 << CONFIG_PHY_ADDR;
#endif

	priv->bus = mdio_alloc();
	if (!priv->bus) {
		printf("Failed to allocate MDIO bus\n");
		return -ENOMEM;
	}

	priv->bus->read = emac_mdio_read;
	priv->bus->write = emac_mdio_write;
	priv->bus->priv = priv;
	strcpy(priv->bus->name, "emac");

	ret = mdio_register(priv->bus);
	if (ret)
		return ret;

	priv->phydev = phy_find_by_mask(priv->bus, mask,
					PHY_INTERFACE_MODE_MII);
	if (!priv->phydev)
		return -ENODEV;

	phy_connect_dev(priv->phydev, dev);
	phy_config(priv->phydev);

	return 0;
}

static void emac_setup(struct emac_eth_dev *priv)
{
	struct emac_regs *regs = priv->regs;
	u32 reg_val;

	/* Set up TX */
	writel(EMAC_TX_SETUP, &regs->tx_mode);

	/* Set up RX */
	writel(EMAC_RX_SETUP, &regs->rx_ctl);

	/* Set MAC */
	/* Set MAC CTL0 */
	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);

	/* Set MAC CTL1 */
	reg_val = 0;
	if (priv->phydev->duplex == DUPLEX_FULL)
		reg_val = (0x1 << 0);
	writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);

	/* Set up IPGT */
	writel(EMAC_MAC_IPGT, &regs->mac_ipgt);

	/* Set up IPGR */
	writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);

	/* Set up Collison window */
	writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);

	/* Set up Max Frame Length */
	writel(EMAC_MAC_MFL, &regs->mac_maxf);
}

static void emac_reset(struct emac_eth_dev *priv)
{
	struct emac_regs *regs = priv->regs;

	debug("resetting device\n");

	/* RESET device */
	writel(0, &regs->ctl);
	udelay(200);

	writel(1, &regs->ctl);
	udelay(200);
}

static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
{
	struct emac_regs *regs = priv->regs;
	u32 enetaddr_lo, enetaddr_hi;

	enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
	enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);

	writel(enetaddr_hi, &regs->mac_a0);
	writel(enetaddr_lo, &regs->mac_a1);

	return 0;
}

static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
{
	struct emac_regs *regs = priv->regs;
	int ret;

	/* Init EMAC */

	/* Flush RX FIFO */
	setbits_le32(&regs->rx_ctl, 0x8);
	udelay(1);

	/* Init MAC */

	/* Soft reset MAC */
	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);

	/* Clear RX counter */
	writel(0x0, &regs->rx_fbc);
	udelay(1);

	/* Set up EMAC */
	emac_setup(priv);

	_sunxi_write_hwaddr(priv, enetaddr);

	mdelay(1);

	emac_reset(priv);

	/* PHY POWER UP */
	ret = phy_startup(priv->phydev);
	if (ret) {
		printf("Could not initialize PHY %s\n",
		       priv->phydev->dev->name);
		return ret;
	}

	/* Print link status only once */
	if (!priv->link_printed) {
		printf("ENET Speed is %d Mbps - %s duplex connection\n",
		       priv->phydev->speed,
		       priv->phydev->duplex ? "FULL" : "HALF");
		priv->link_printed = 1;
	}

	/* Set EMAC SPEED depend on PHY */
	if (priv->phydev->speed == SPEED_100)
		setbits_le32(&regs->mac_supp, 1 << 8);
	else
		clrbits_le32(&regs->mac_supp, 1 << 8);

	/* Set duplex depend on phy */
	if (priv->phydev->duplex == DUPLEX_FULL)
		setbits_le32(&regs->mac_ctl1, 1 << 0);
	else
		clrbits_le32(&regs->mac_ctl1, 1 << 0);

	/* Enable RX/TX */
	setbits_le32(&regs->ctl, 0x7);

	return 0;
}

static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
{
	struct emac_regs *regs = priv->regs;
	struct emac_rxhdr rxhdr;
	u32 rxcount;
	u32 reg_val;
	int rx_len;
	int rx_status;
	int good_packet;

	/* Check packet ready or not */

	/* Race warning: The first packet might arrive with
	 * the interrupts disabled, but the second will fix
	 */
	rxcount = readl(&regs->rx_fbc);
	if (!rxcount) {
		/* Had one stuck? */
		rxcount = readl(&regs->rx_fbc);
		if (!rxcount)
			return -EAGAIN;
	}

	reg_val = readl(&regs->rx_io_data);
	if (reg_val != 0x0143414d) {
		/* Disable RX */
		clrbits_le32(&regs->ctl, 0x1 << 2);

		/* Flush RX FIFO */
		setbits_le32(&regs->rx_ctl, 0x1 << 3);
		while (readl(&regs->rx_ctl) & (0x1 << 3))
			;

		/* Enable RX */
		setbits_le32(&regs->ctl, 0x1 << 2);

		return -EAGAIN;
	}

	/* A packet ready now
	 * Get status/length
	 */
	good_packet = 1;

	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));

	rx_len = rxhdr.rx_len;
	rx_status = rxhdr.rx_status;

	/* Packet Status check */
	if (rx_len < 0x40) {
		good_packet = 0;
		debug("RX: Bad Packet (runt)\n");
	}

	/* rx_status is identical to RSR register. */
	if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
		good_packet = 0;
		if (rx_status & EMAC_CRCERR)
			printf("crc error\n");
		if (rx_status & EMAC_LENERR)
			printf("length error\n");
	}

	/* Move data from EMAC */
	if (good_packet) {
		if (rx_len > EMAC_RX_BUFSIZE) {
			printf("Received packet is too big (len=%d)\n", rx_len);
			return -EMSGSIZE;
		}
		emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
		return rx_len;
	}

	return -EIO; /* Bad packet */
}

static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
				int len)
{
	struct emac_regs *regs = priv->regs;

	/* Select channel 0 */
	writel(0, &regs->tx_ins);

	/* Write packet */
	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);

	/* Set TX len */
	writel(len, &regs->tx_pl0);

	/* Start translate from fifo to phy */
	setbits_le32(&regs->tx_ctl0, 1);

	return 0;
}

static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
{
	struct sunxi_sramc_regs *sram =
		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
	struct emac_regs *regs = priv->regs;
	int pin, ret;

	/* Map SRAM to EMAC */
	setbits_le32(&sram->ctrl1, 0x5 << 2);

	/* Configure pin mux settings for MII Ethernet */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);

	/* Set up clock gating */
	ret = clk_enable(&priv->clk);
	if (ret) {
		dev_err(dev, "failed to enable emac clock\n");
		return ret;
	}

	/* Set MII clock */
	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);

	return 0;
}

static int sunxi_emac_eth_start(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);

	return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
}

static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);

	return _sunxi_emac_eth_send(priv, packet, length);
}

static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	int rx_len;

	rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
	*packetp = priv->rx_buf;

	return rx_len;
}

static void sunxi_emac_eth_stop(struct udevice *dev)
{
	/* Nothing to do here */
}

static int sunxi_emac_eth_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct emac_eth_dev *priv = dev_get_priv(dev);
	int ret;

	priv->regs = (struct emac_regs *)pdata->iobase;

	ret = clk_get_by_index(dev, 0, &priv->clk);
	if (ret) {
		dev_err(dev, "failed to get emac clock\n");
		return ret;
	}

	ret = sunxi_emac_board_setup(priv);
	if (ret)
		return ret;

	return sunxi_emac_init_phy(priv, dev);
}

static const struct eth_ops sunxi_emac_eth_ops = {
	.start			= sunxi_emac_eth_start,
	.send			= sunxi_emac_eth_send,
	.recv			= sunxi_emac_eth_recv,
	.stop			= sunxi_emac_eth_stop,
};

static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);

	pdata->iobase = devfdt_get_addr(dev);

	return 0;
}

static const struct udevice_id sunxi_emac_eth_ids[] = {
	{ .compatible = "allwinner,sun4i-a10-emac" },
	{ }
};

U_BOOT_DRIVER(eth_sunxi_emac) = {
	.name	= "eth_sunxi_emac",
	.id	= UCLASS_ETH,
	.of_match = sunxi_emac_eth_ids,
	.ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
	.probe	= sunxi_emac_eth_probe,
	.ops	= &sunxi_emac_eth_ops,
	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
518ce472	2	/*
b70ed300	3	* sunxi_emac.c -- Allwinner A10 ethernet driver
518ce472 HN	4	*
518ce472 HN	5	* (C) Copyright 2012, Stefan Roese <[email protected]>
518ce472 HN	6	*/
	7
	8	#include <common.h>
0ed8eaf1	9	#include <clk.h>
939ed1cb	10	#include <dm.h>
b70ed300	11	#include <linux/err.h>
518ce472	12	#include <malloc.h>
518ce472	13	#include <miiphy.h>
b70ed300	14	#include <net.h>
518ce472 HN	15	#include <asm/io.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/gpio.h>
	18
	19	/* EMAC register */
b70ed300	20	struct emac_regs {
518ce472 HN	21	u32 ctl; /* 0x00 */
	22	u32 tx_mode; /* 0x04 */
	23	u32 tx_flow; /* 0x08 */
	24	u32 tx_ctl0; /* 0x0c */
	25	u32 tx_ctl1; /* 0x10 */
	26	u32 tx_ins; /* 0x14 */
	27	u32 tx_pl0; /* 0x18 */
	28	u32 tx_pl1; /* 0x1c */
	29	u32 tx_sta; /* 0x20 */
	30	u32 tx_io_data; /* 0x24 */
b70ed300	31	u32 tx_io_data1;/* 0x28 */
518ce472 HN	32	u32 tx_tsvl0; /* 0x2c */
	33	u32 tx_tsvh0; /* 0x30 */
	34	u32 tx_tsvl1; /* 0x34 */
	35	u32 tx_tsvh1; /* 0x38 */
	36	u32 rx_ctl; /* 0x3c */
	37	u32 rx_hash0; /* 0x40 */
	38	u32 rx_hash1; /* 0x44 */
	39	u32 rx_sta; /* 0x48 */
	40	u32 rx_io_data; /* 0x4c */
	41	u32 rx_fbc; /* 0x50 */
	42	u32 int_ctl; /* 0x54 */
	43	u32 int_sta; /* 0x58 */
	44	u32 mac_ctl0; /* 0x5c */
	45	u32 mac_ctl1; /* 0x60 */
	46	u32 mac_ipgt; /* 0x64 */
	47	u32 mac_ipgr; /* 0x68 */
	48	u32 mac_clrt; /* 0x6c */
	49	u32 mac_maxf; /* 0x70 */
	50	u32 mac_supp; /* 0x74 */
	51	u32 mac_test; /* 0x78 */
	52	u32 mac_mcfg; /* 0x7c */
	53	u32 mac_mcmd; /* 0x80 */
	54	u32 mac_madr; /* 0x84 */
	55	u32 mac_mwtd; /* 0x88 */
	56	u32 mac_mrdd; /* 0x8c */
	57	u32 mac_mind; /* 0x90 */
	58	u32 mac_ssrr; /* 0x94 */
	59	u32 mac_a0; /* 0x98 */
	60	u32 mac_a1; /* 0x9c */
	61	};
	62
	63	/* SRAMC register */
	64	struct sunxi_sramc_regs {
	65	u32 ctrl0;
	66	u32 ctrl1;
	67	};
	68
	69	/* 0: Disable 1: Aborted frame enable(default) */
	70	#define EMAC_TX_AB_M (0x1 << 0)
	71	/* 0: CPU 1: DMA(default) */
	72	#define EMAC_TX_TM (0x1 << 1)
	73
	74	#define EMAC_TX_SETUP (0)
	75
	76	/* 0: DRQ asserted 1: DRQ automatically(default) */
	77	#define EMAC_RX_DRQ_MODE (0x1 << 1)
	78	/* 0: CPU 1: DMA(default) */
	79	#define EMAC_RX_TM (0x1 << 2)
	80	/* 0: Normal(default) 1: Pass all Frames */
	81	#define EMAC_RX_PA (0x1 << 4)
	82	/* 0: Normal(default) 1: Pass Control Frames */
	83	#define EMAC_RX_PCF (0x1 << 5)
	84	/* 0: Normal(default) 1: Pass Frames with CRC Error */
	85	#define EMAC_RX_PCRCE (0x1 << 6)
	86	/* 0: Normal(default) 1: Pass Frames with Length Error */
	87	#define EMAC_RX_PLE (0x1 << 7)
	88	/* 0: Normal 1: Pass Frames length out of range(default) */
	89	#define EMAC_RX_POR (0x1 << 8)
	90	/* 0: Not accept 1: Accept unicast Packets(default) */
	91	#define EMAC_RX_UCAD (0x1 << 16)
	92	/* 0: Normal(default) 1: DA Filtering */
	93	#define EMAC_RX_DAF (0x1 << 17)
	94	/* 0: Not accept 1: Accept multicast Packets(default) */
	95	#define EMAC_RX_MCO (0x1 << 20)
96	/* 0: Disable(default) 1: Enable Hash filter */
97	#define EMAC_RX_MHF (0x1 << 21)
98	/* 0: Not accept 1: Accept Broadcast Packets(default) */
99	#define EMAC_RX_BCO (0x1 << 22)
100	/* 0: Disable(default) 1: Enable SA Filtering */
101	#define EMAC_RX_SAF (0x1 << 24)
102	/* 0: Normal(default) 1: Inverse Filtering */
103	#define EMAC_RX_SAIF (0x1 << 25)
104
105	#define EMAC_RX_SETUP (EMAC_RX_POR \| EMAC_RX_UCAD \| EMAC_RX_DAF \| \
106	EMAC_RX_MCO \| EMAC_RX_BCO)
107
108	/* 0: Disable 1: Enable Receive Flow Control(default) */
109	#define EMAC_MAC_CTL0_RFC (0x1 << 2)
110	/* 0: Disable 1: Enable Transmit Flow Control(default) */
111	#define EMAC_MAC_CTL0_TFC (0x1 << 3)
112
113	#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC \| EMAC_MAC_CTL0_TFC)
114
115	/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
116	#define EMAC_MAC_CTL1_FLC (0x1 << 1)
117	/* 0: Disable(default) 1: Enable Huge Frame */
118	#define EMAC_MAC_CTL1_HF (0x1 << 2)
119	/* 0: Disable(default) 1: Enable MAC Delayed CRC */
120	#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
121	/* 0: Disable 1: Enable MAC CRC(default) */
122	#define EMAC_MAC_CTL1_CRC (0x1 << 4)
123	/* 0: Disable 1: Enable MAC PAD Short frames(default) */
124	#define EMAC_MAC_CTL1_PC (0x1 << 5)
125	/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
126	#define EMAC_MAC_CTL1_VC (0x1 << 6)
127	/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
128	#define EMAC_MAC_CTL1_ADP (0x1 << 7)
129	/* 0: Disable(default) 1: Enable */
130	#define EMAC_MAC_CTL1_PRE (0x1 << 8)
131	/* 0: Disable(default) 1: Enable */
132	#define EMAC_MAC_CTL1_LPE (0x1 << 9)
133	/* 0: Disable(default) 1: Enable no back off */
134	#define EMAC_MAC_CTL1_NB (0x1 << 12)
135	/* 0: Disable(default) 1: Enable */
136	#define EMAC_MAC_CTL1_BNB (0x1 << 13)
137	/* 0: Disable(default) 1: Enable */
138	#define EMAC_MAC_CTL1_ED (0x1 << 14)
139
140	#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC \| EMAC_MAC_CTL1_CRC \| \
141	EMAC_MAC_CTL1_PC)
142
143	#define EMAC_MAC_IPGT 0x15
144
b70ed300	145	#define EMAC_MAC_NBTB_IPG1 0xc
518ce472 HN	146	#define EMAC_MAC_NBTB_IPG2 0x12
	147
	148	#define EMAC_MAC_CW 0x37
b70ed300	149	#define EMAC_MAC_RM 0xf
518ce472 HN	150
	151	#define EMAC_MAC_MFL 0x0600
	152
	153	/* Receive status */
b70ed300 SR	154	#define EMAC_CRCERR (0x1 << 4)
b70ed300 SR	155	#define EMAC_LENERR (0x3 << 5)
518ce472	156
d88c2f11	157	#define EMAC_RX_BUFSIZE 2000
518ce472	158
b70ed300	159	struct emac_eth_dev {
8145dea4	160	struct emac_regs *regs;
0ed8eaf1	161	struct clk clk;
8145dea4 HG	162	struct mii_dev *bus;
8145dea4 HG	163	struct phy_device *phydev;
518ce472	164	int link_printed;
939ed1cb HG	165	#ifdef CONFIG_DM_ETH
	166	uchar rx_buf[EMAC_RX_BUFSIZE];
	167	#endif
518ce472 HN	168	};
518ce472 HN	169
b70ed300	170	struct emac_rxhdr {
518ce472 HN	171	s16 rx_len;
	172	u16 rx_status;
	173	};
	174
b70ed300	175	static void emac_inblk_32bit(void reg, void data, int count)
518ce472 HN	176	{
	177	int cnt = (count + 3) >> 2;
	178
	179	if (cnt) {
	180	u32 *buf = data;
	181
	182	do {
	183	u32 x = readl(reg);
	184	*buf++ = x;
	185	} while (--cnt);
	186	}
	187	}
	188
b70ed300	189	static void emac_outblk_32bit(void reg, void data, int count)
518ce472 HN	190	{
	191	int cnt = (count + 3) >> 2;
	192
	193	if (cnt) {
	194	const u32 *buf = data;
	195
	196	do {
	197	writel(*buf++, reg);
	198	} while (--cnt);
	199	}
	200	}
	201
b70ed300	202	/* Read a word from phyxcer */
8145dea4	203	static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
518ce472	204	{
8145dea4 HG	205	struct emac_eth_dev *priv = bus->priv;
8145dea4 HG	206	struct emac_regs *regs = priv->regs;
518ce472 HN	207
	208	/* issue the phy address and reg */
	209	writel(addr << 8 \| reg, &regs->mac_madr);
	210
	211	/* pull up the phy io line */
	212	writel(0x1, &regs->mac_mcmd);
	213
	214	/* Wait read complete */
	215	mdelay(1);
	216
	217	/* push down the phy io line */
	218	writel(0x0, &regs->mac_mcmd);
	219
8145dea4 HG	220	/* And read data */
8145dea4 HG	221	return readl(&regs->mac_mrdd);
518ce472 HN	222	}
518ce472 HN	223
b70ed300	224	/* Write a word to phyxcer */
8145dea4 HG	225	static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
8145dea4 HG	226	u16 value)
518ce472	227	{
8145dea4 HG	228	struct emac_eth_dev *priv = bus->priv;
8145dea4 HG	229	struct emac_regs *regs = priv->regs;
518ce472 HN	230
	231	/* issue the phy address and reg */
	232	writel(addr << 8 \| reg, &regs->mac_madr);
	233
	234	/* pull up the phy io line */
	235	writel(0x1, &regs->mac_mcmd);
	236
	237	/* Wait write complete */
	238	mdelay(1);
	239
	240	/* push down the phy io line */
	241	writel(0x0, &regs->mac_mcmd);
	242
	243	/* and write data */
	244	writel(value, &regs->mac_mwtd);
	245
	246	return 0;
	247	}
	248
8145dea4	249	static int sunxi_emac_init_phy(struct emac_eth_dev priv, void dev)
518ce472	250	{
8145dea4 HG	251	int ret, mask = 0xffffffff;
	252
	253	#ifdef CONFIG_PHY_ADDR
	254	mask = 1 << CONFIG_PHY_ADDR;
	255	#endif
	256
	257	priv->bus = mdio_alloc();
	258	if (!priv->bus) {
	259	printf("Failed to allocate MDIO bus\n");
	260	return -ENOMEM;
	261	}
	262
	263	priv->bus->read = emac_mdio_read;
	264	priv->bus->write = emac_mdio_write;
	265	priv->bus->priv = priv;
	266	strcpy(priv->bus->name, "emac");
	267
	268	ret = mdio_register(priv->bus);
	269	if (ret)
	270	return ret;
	271
	272	priv->phydev = phy_find_by_mask(priv->bus, mask,
	273	PHY_INTERFACE_MODE_MII);
	274	if (!priv->phydev)
	275	return -ENODEV;
	276
	277	phy_connect_dev(priv->phydev, dev);
	278	phy_config(priv->phydev);
	279
	280	return 0;
	281	}
	282
	283	static void emac_setup(struct emac_eth_dev *priv)
	284	{
	285	struct emac_regs *regs = priv->regs;
518ce472	286	u32 reg_val;
518ce472 HN	287
	288	/* Set up TX */
	289	writel(EMAC_TX_SETUP, &regs->tx_mode);
	290
	291	/* Set up RX */
	292	writel(EMAC_RX_SETUP, &regs->rx_ctl);
	293
	294	/* Set MAC */
	295	/* Set MAC CTL0 */
	296	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
	297
	298	/* Set MAC CTL1 */
518ce472	299	reg_val = 0;
8145dea4	300	if (priv->phydev->duplex == DUPLEX_FULL)
518ce472 HN	301	reg_val = (0x1 << 0);
	302	writel(EMAC_MAC_CTL1_SETUP \| reg_val, &regs->mac_ctl1);
	303
	304	/* Set up IPGT */
	305	writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
	306
	307	/* Set up IPGR */
	308	writel(EMAC_MAC_NBTB_IPG2 \| (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
	309
	310	/* Set up Collison window */
	311	writel(EMAC_MAC_RM \| (EMAC_MAC_CW << 8), &regs->mac_clrt);
	312
	313	/* Set up Max Frame Length */
	314	writel(EMAC_MAC_MFL, &regs->mac_maxf);
	315	}
	316
f9f62d2d	317	static void emac_reset(struct emac_eth_dev *priv)
518ce472	318	{
f9f62d2d	319	struct emac_regs *regs = priv->regs;
518ce472 HN	320
	321	debug("resetting device\n");
	322
	323	/* RESET device */
	324	writel(0, &regs->ctl);
	325	udelay(200);
	326
	327	writel(1, &regs->ctl);
	328	udelay(200);
	329	}
	330
ace1520c	331	static int _sunxi_write_hwaddr(struct emac_eth_dev priv, u8 enetaddr)
	332	{
	333	struct emac_regs *regs = priv->regs;
	334	u32 enetaddr_lo, enetaddr_hi;
	335
	336	enetaddr_lo = enetaddr[2] \| (enetaddr[1] << 8) \| (enetaddr[0] << 16);
	337	enetaddr_hi = enetaddr[5] \| (enetaddr[4] << 8) \| (enetaddr[3] << 16);
	338
6e35686d JH	339	writel(enetaddr_hi, &regs->mac_a0);
6e35686d JH	340	writel(enetaddr_lo, &regs->mac_a1);
ace1520c	341
	342	return 0;
	343	}
	344
f9f62d2d	345	static int _sunxi_emac_eth_init(struct emac_eth_dev priv, u8 enetaddr)
518ce472	346	{
f9f62d2d	347	struct emac_regs *regs = priv->regs;
8145dea4	348	int ret;
518ce472 HN	349
	350	/* Init EMAC */
	351
	352	/* Flush RX FIFO */
	353	setbits_le32(&regs->rx_ctl, 0x8);
	354	udelay(1);
	355
	356	/* Init MAC */
	357
	358	/* Soft reset MAC */
b70ed300	359	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
518ce472 HN	360
	361	/* Clear RX counter */
	362	writel(0x0, &regs->rx_fbc);
	363	udelay(1);
	364
	365	/* Set up EMAC */
8145dea4	366	emac_setup(priv);
518ce472	367
ace1520c	368	_sunxi_write_hwaddr(priv, enetaddr);
518ce472 HN	369
	370	mdelay(1);
	371
f9f62d2d	372	emac_reset(priv);
518ce472 HN	373
518ce472 HN	374	/* PHY POWER UP */
8145dea4 HG	375	ret = phy_startup(priv->phydev);
	376	if (ret) {
	377	printf("Could not initialize PHY %s\n",
	378	priv->phydev->dev->name);
	379	return ret;
	380	}
518ce472 HN	381
	382	/* Print link status only once */
	383	if (!priv->link_printed) {
	384	printf("ENET Speed is %d Mbps - %s duplex connection\n",
8145dea4 HG	385	priv->phydev->speed,
8145dea4 HG	386	priv->phydev->duplex ? "FULL" : "HALF");
518ce472 HN	387	priv->link_printed = 1;
	388	}
	389
	390	/* Set EMAC SPEED depend on PHY */
8145dea4 HG	391	if (priv->phydev->speed == SPEED_100)
	392	setbits_le32(&regs->mac_supp, 1 << 8);
	393	else
	394	clrbits_le32(&regs->mac_supp, 1 << 8);
518ce472 HN	395
518ce472 HN	396	/* Set duplex depend on phy */
8145dea4 HG	397	if (priv->phydev->duplex == DUPLEX_FULL)
	398	setbits_le32(&regs->mac_ctl1, 1 << 0);
	399	else
	400	clrbits_le32(&regs->mac_ctl1, 1 << 0);
518ce472 HN	401
	402	/* Enable RX/TX */
	403	setbits_le32(&regs->ctl, 0x7);
	404
	405	return 0;
	406	}
	407
f9f62d2d	408	static int _sunxi_emac_eth_recv(struct emac_eth_dev priv, void packet)
518ce472	409	{
f9f62d2d	410	struct emac_regs *regs = priv->regs;
b70ed300	411	struct emac_rxhdr rxhdr;
518ce472 HN	412	u32 rxcount;
	413	u32 reg_val;
	414	int rx_len;
	415	int rx_status;
	416	int good_packet;
	417
	418	/* Check packet ready or not */
	419
b70ed300	420	/* Race warning: The first packet might arrive with
518ce472 HN	421	* the interrupts disabled, but the second will fix
	422	*/
	423	rxcount = readl(&regs->rx_fbc);
	424	if (!rxcount) {
	425	/* Had one stuck? */
	426	rxcount = readl(&regs->rx_fbc);
	427	if (!rxcount)
f9f62d2d	428	return -EAGAIN;
518ce472 HN	429	}
	430
	431	reg_val = readl(&regs->rx_io_data);
	432	if (reg_val != 0x0143414d) {
	433	/* Disable RX */
b70ed300	434	clrbits_le32(&regs->ctl, 0x1 << 2);
518ce472 HN	435
518ce472 HN	436	/* Flush RX FIFO */
b70ed300 SR	437	setbits_le32(&regs->rx_ctl, 0x1 << 3);
b70ed300 SR	438	while (readl(&regs->rx_ctl) & (0x1 << 3))
518ce472 HN	439	;
	440
	441	/* Enable RX */
b70ed300	442	setbits_le32(&regs->ctl, 0x1 << 2);
518ce472	443
f9f62d2d	444	return -EAGAIN;
518ce472 HN	445	}
518ce472 HN	446
b70ed300	447	/* A packet ready now
518ce472 HN	448	* Get status/length
	449	*/
	450	good_packet = 1;
	451
b70ed300	452	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
518ce472 HN	453
	454	rx_len = rxhdr.rx_len;
	455	rx_status = rxhdr.rx_status;
	456
	457	/* Packet Status check */
	458	if (rx_len < 0x40) {
	459	good_packet = 0;
	460	debug("RX: Bad Packet (runt)\n");
	461	}
	462
	463	/* rx_status is identical to RSR register. */
	464	if (0 & rx_status & (EMAC_CRCERR \| EMAC_LENERR)) {
	465	good_packet = 0;
	466	if (rx_status & EMAC_CRCERR)
	467	printf("crc error\n");
	468	if (rx_status & EMAC_LENERR)
	469	printf("length error\n");
	470	}
	471
b70ed300	472	/* Move data from EMAC */
518ce472	473	if (good_packet) {
d88c2f11	474	if (rx_len > EMAC_RX_BUFSIZE) {
518ce472	475	printf("Received packet is too big (len=%d)\n", rx_len);
f9f62d2d	476	return -EMSGSIZE;
518ce472	477	}
f9f62d2d HG	478	emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
f9f62d2d HG	479	return rx_len;
518ce472 HN	480	}
518ce472 HN	481
f9f62d2d	482	return -EIO; /* Bad packet */
518ce472 HN	483	}
518ce472 HN	484
f9f62d2d HG	485	static int _sunxi_emac_eth_send(struct emac_eth_dev priv, void packet,
f9f62d2d HG	486	int len)
518ce472	487	{
f9f62d2d	488	struct emac_regs *regs = priv->regs;
518ce472 HN	489
	490	/* Select channel 0 */
	491	writel(0, &regs->tx_ins);
	492
	493	/* Write packet */
b70ed300	494	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
518ce472 HN	495
	496	/* Set TX len */
	497	writel(len, &regs->tx_pl0);
	498
	499	/* Start translate from fifo to phy */
	500	setbits_le32(&regs->tx_ctl0, 1);
	501
	502	return 0;
	503	}
	504
0ed8eaf1	505	static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
518ce472	506	{
518ce472 HN	507	struct sunxi_sramc_regs *sram =
518ce472 HN	508	(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
f9f62d2d	509	struct emac_regs *regs = priv->regs;
0ed8eaf1	510	int pin, ret;
f9f62d2d HG	511
	512	/* Map SRAM to EMAC */
	513	setbits_le32(&sram->ctrl1, 0x5 << 2);
	514
	515	/* Configure pin mux settings for MII Ethernet */
	516	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
	517	sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
	518
	519	/* Set up clock gating */
0ed8eaf1 JT	520	ret = clk_enable(&priv->clk);
	521	if (ret) {
	522	dev_err(dev, "failed to enable emac clock\n");
	523	return ret;
	524	}
f9f62d2d HG	525
	526	/* Set MII clock */
	527	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
0ed8eaf1 JT	528
0ed8eaf1 JT	529	return 0;
f9f62d2d HG	530	}
f9f62d2d HG	531
939ed1cb HG	532	static int sunxi_emac_eth_start(struct udevice *dev)
	533	{
	534	struct eth_pdata *pdata = dev_get_platdata(dev);
	535
	536	return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
	537	}
	538
	539	static int sunxi_emac_eth_send(struct udevice dev, void packet, int length)
	540	{
	541	struct emac_eth_dev *priv = dev_get_priv(dev);
	542
	543	return _sunxi_emac_eth_send(priv, packet, length);
	544	}
	545
a1ca92ea	546	static int sunxi_emac_eth_recv(struct udevice dev, int flags, uchar *packetp)
939ed1cb HG	547	{
	548	struct emac_eth_dev *priv = dev_get_priv(dev);
	549	int rx_len;
	550
	551	rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
	552	*packetp = priv->rx_buf;
	553
	554	return rx_len;
	555	}
	556
	557	static void sunxi_emac_eth_stop(struct udevice *dev)
	558	{
	559	/* Nothing to do here */
	560	}
	561
	562	static int sunxi_emac_eth_probe(struct udevice *dev)
	563	{
	564	struct eth_pdata *pdata = dev_get_platdata(dev);
	565	struct emac_eth_dev *priv = dev_get_priv(dev);
0ed8eaf1	566	int ret;
939ed1cb HG	567
939ed1cb HG	568	priv->regs = (struct emac_regs *)pdata->iobase;
0ed8eaf1 JT	569
	570	ret = clk_get_by_index(dev, 0, &priv->clk);
	571	if (ret) {
	572	dev_err(dev, "failed to get emac clock\n");
	573	return ret;
	574	}
	575
	576	ret = sunxi_emac_board_setup(priv);
	577	if (ret)
	578	return ret;
939ed1cb HG	579
	580	return sunxi_emac_init_phy(priv, dev);
	581	}
	582
	583	static const struct eth_ops sunxi_emac_eth_ops = {
	584	.start = sunxi_emac_eth_start,
	585	.send = sunxi_emac_eth_send,
	586	.recv = sunxi_emac_eth_recv,
	587	.stop = sunxi_emac_eth_stop,
	588	};
	589
	590	static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
	591	{
	592	struct eth_pdata *pdata = dev_get_platdata(dev);
	593
a821c4af	594	pdata->iobase = devfdt_get_addr(dev);
939ed1cb HG	595
	596	return 0;
	597	}
	598
	599	static const struct udevice_id sunxi_emac_eth_ids[] = {
	600	{ .compatible = "allwinner,sun4i-a10-emac" },
	601	{ }
	602	};
	603
	604	U_BOOT_DRIVER(eth_sunxi_emac) = {
	605	.name = "eth_sunxi_emac",
	606	.id = UCLASS_ETH,
	607	.of_match = sunxi_emac_eth_ids,
	608	.ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
	609	.probe = sunxi_emac_eth_probe,
	610	.ops = &sunxi_emac_eth_ops,
	611	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
	612	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	613	};