[J-u-boot.git] / drivers / net / rtl8139.c

/*
 * rtl8139.c : U-Boot driver for the RealTek RTL8139
 *
 * Masami Komiya ([email protected])
 *
 * Most part is taken from rtl8139.c of etherboot
 *
 */

/* rtl8139.c - etherboot driver for the Realtek 8139 chipset

  ported from the linux driver written by Donald Becker
  by Rainer Bawidamann ([email protected]) 1999

  This software may be used and distributed according to the terms
  of the GNU Public License, incorporated herein by reference.

  changes to the original driver:
  - removed support for interrupts, switching to polling mode (yuck!)
  - removed support for the 8129 chip (external MII)

*/

/*********************************************************************/
/* Revision History						     */
/*********************************************************************/

/*
  28 Dec 2002	[email protected] (Ken Yap)
     Put in virt_to_bus calls to allow Etherboot relocation.

  06 Apr 2001	[email protected] (Ken Yap)
     Following email from Hyun-Joon Cha, added a disable routine, otherwise
     NIC remains live and can crash the kernel later.

  4 Feb 2000	[email protected] (Klaus Espenlaub)
     Shuffled things around, removed the leftovers from the 8129 support
     that was in the Linux driver and added a bit more 8139 definitions.
     Moved the 8K receive buffer to a fixed, available address outside the
     0x98000-0x9ffff range.  This is a bit of a hack, but currently the only
     way to make room for the Etherboot features that need substantial amounts
     of code like the ANSI console support.  Currently the buffer is just below
     0x10000, so this even conforms to the tagged boot image specification,
     which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000.  My
     interpretation of this "reserved" is that Etherboot may do whatever it
     likes, as long as its environment is kept intact (like the BIOS
     variables).  Hopefully fixed rtl_poll() once and for all.	The symptoms
     were that if Etherboot was left at the boot menu for several minutes, the
     first eth_poll failed.  Seems like I am the only person who does this.
     First of all I fixed the debugging code and then set out for a long bug
     hunting session.  It took me about a week full time work - poking around
     various places in the driver, reading Don Becker's and Jeff Garzik's Linux
     driver and even the FreeBSD driver (what a piece of crap!) - and
     eventually spotted the nasty thing: the transmit routine was acknowledging
     each and every interrupt pending, including the RxOverrun and RxFIFIOver
     interrupts.  This confused the RTL8139 thoroughly.	 It destroyed the
     Rx ring contents by dumping the 2K FIFO contents right where we wanted to
     get the next packet.  Oh well, what fun.

  18 Jan 2000	[email protected] (Marty Connor)
     Drastically simplified error handling.  Basically, if any error
     in transmission or reception occurs, the card is reset.
     Also, pointed all transmit descriptors to the same buffer to
     save buffer space.	 This should decrease driver size and avoid
     corruption because of exceeding 32K during runtime.

  28 Jul 1999	(Matthias Meixner - [email protected])
     rtl_poll was quite broken: it used the RxOK interrupt flag instead
     of the RxBufferEmpty flag which often resulted in very bad
     transmission performace - below 1kBytes/s.

*/

#include <common.h>
#include <cpu_func.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>

#define RTL_TIMEOUT	100000

/* PCI Tuning Parameters
   Threshold is bytes transferred to chip before transmission starts. */
#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
#define RX_FIFO_THRESH	4	/* Rx buffer level before first PCI xfer.  */
#define RX_DMA_BURST	4	/* Maximum PCI burst, '4' is 256 bytes */
#define TX_DMA_BURST	4	/* Calculate as 16<<val. */
#define NUM_TX_DESC	4	/* Number of Tx descriptor registers. */
#define TX_BUF_SIZE	ETH_FRAME_LEN	/* FCS is added by the chip */
#define RX_BUF_LEN_IDX 0	/* 0, 1, 2 is allowed - 8,16,32K rx buffer */
#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)

#define DEBUG_TX	0	/* set to 1 to enable debug code */
#define DEBUG_RX	0	/* set to 1 to enable debug code */

#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)

/* Symbolic offsets to registers. */
enum RTL8139_registers {
	MAC0=0,			/* Ethernet hardware address. */
	MAR0=8,			/* Multicast filter. */
	TxStatus0=0x10,		/* Transmit status (four 32bit registers). */
	TxAddr0=0x20,		/* Tx descriptors (also four 32bit). */
	RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
	ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
	IntrMask=0x3C, IntrStatus=0x3E,
	TxConfig=0x40, RxConfig=0x44,
	Timer=0x48,		/* general-purpose counter. */
	RxMissed=0x4C,		/* 24 bits valid, write clears. */
	Cfg9346=0x50, Config0=0x51, Config1=0x52,
	TimerIntrReg=0x54,	/* intr if gp counter reaches this value */
	MediaStatus=0x58,
	Config3=0x59,
	MultiIntr=0x5C,
	RevisionID=0x5E,	/* revision of the RTL8139 chip */
	TxSummary=0x60,
	MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
	NWayExpansion=0x6A,
	DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
	NWayTestReg=0x70,
	RxCnt=0x72,		/* packet received counter */
	CSCR=0x74,		/* chip status and configuration register */
	PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,	/* undocumented */
	/* from 0x84 onwards are a number of power management/wakeup frame
	 * definitions we will probably never need to know about.  */
};

enum ChipCmdBits {
	CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };

/* Interrupt register bits, using my own meaningful names. */
enum IntrStatusBits {
	PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
	RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
	TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
};
enum TxStatusBits {
	TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
	TxOutOfWindow=0x20000000, TxAborted=0x40000000,
	TxCarrierLost=0x80000000,
};
enum RxStatusBits {
	RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
	RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
	RxBadAlign=0x0002, RxStatusOK=0x0001,
};

enum MediaStatusBits {
	MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
	MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
};

enum MIIBMCRBits {
	BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
	BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
};

enum CSCRBits {
	CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
	CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
	CSCR_LinkDownCmd=0x0f3c0,
};

/* Bits in RxConfig. */
enum rx_mode_bits {
	RxCfgWrap=0x80,
	AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
	AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
};

static int ioaddr;
static unsigned int cur_rx,cur_tx;

/* The RTL8139 can only transmit from a contiguous, aligned memory block.  */
static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));

static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
static int read_eeprom(int location, int addr_len);
static void rtl_reset(struct eth_device *dev);
static int rtl_transmit(struct eth_device *dev, void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
{
	return (0);
}

static struct pci_device_id supported[] = {
       {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
       {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
       {}
};

int rtl8139_initialize(bd_t *bis)
{
	pci_dev_t devno;
	int card_number = 0;
	struct eth_device *dev;
	u32 iobase;
	int idx=0;

	while(1){
		/* Find RTL8139 */
		if ((devno = pci_find_devices(supported, idx++)) < 0)
			break;

		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
		iobase &= ~0xf;

		debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);

		dev = (struct eth_device *)malloc(sizeof *dev);
		if (!dev) {
			printf("Can not allocate memory of rtl8139\n");
			break;
		}
		memset(dev, 0, sizeof(*dev));

		sprintf (dev->name, "RTL8139#%d", card_number);

		dev->priv = (void *) devno;
		dev->iobase = (int)bus_to_phys(iobase);
		dev->init = rtl8139_probe;
		dev->halt = rtl_disable;
		dev->send = rtl_transmit;
		dev->recv = rtl_poll;
		dev->mcast = rtl_bcast_addr;

		eth_register (dev);

		card_number++;

		pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);

		udelay (10 * 1000);
	}

	return card_number;
}

static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
{
	int i;
	int addr_len;
	unsigned short *ap = (unsigned short *)dev->enetaddr;

	ioaddr = dev->iobase;

	/* Bring the chip out of low-power mode. */
	outb(0x00, ioaddr + Config1);

	addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
	for (i = 0; i < 3; i++)
		*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));

	rtl_reset(dev);

	if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
		printf("Cable not connected or other link failure\n");
		return -1 ;
	}

	return 0;
}

/* Serial EEPROM section. */

/*  EEPROM_Ctrl bits. */
#define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
#define EE_CS		0x08	/* EEPROM chip select. */
#define EE_DATA_WRITE	0x02	/* EEPROM chip data in. */
#define EE_WRITE_0	0x00
#define EE_WRITE_1	0x02
#define EE_DATA_READ	0x01	/* EEPROM chip data out. */
#define EE_ENB		(0x80 | EE_CS)

/*
	Delay between EEPROM clock transitions.
	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
*/

#define eeprom_delay()	inl(ee_addr)

/* The EEPROM commands include the alway-set leading bit. */
#define EE_WRITE_CMD	(5)
#define EE_READ_CMD	(6)
#define EE_ERASE_CMD	(7)

static int read_eeprom(int location, int addr_len)
{
	int i;
	unsigned int retval = 0;
	long ee_addr = ioaddr + Cfg9346;
	int read_cmd = location | (EE_READ_CMD << addr_len);

	outb(EE_ENB & ~EE_CS, ee_addr);
	outb(EE_ENB, ee_addr);
	eeprom_delay();

	/* Shift the read command bits out. */
	for (i = 4 + addr_len; i >= 0; i--) {
		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
		outb(EE_ENB | dataval, ee_addr);
		eeprom_delay();
		outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
		eeprom_delay();
	}
	outb(EE_ENB, ee_addr);
	eeprom_delay();

	for (i = 16; i > 0; i--) {
		outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
		eeprom_delay();
		retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
		outb(EE_ENB, ee_addr);
		eeprom_delay();
	}

	/* Terminate the EEPROM access. */
	outb(~EE_CS, ee_addr);
	eeprom_delay();
	return retval;
}

static const unsigned int rtl8139_rx_config =
	(RX_BUF_LEN_IDX << 11) |
	(RX_FIFO_THRESH << 13) |
	(RX_DMA_BURST << 8);

static void set_rx_mode(struct eth_device *dev) {
	unsigned int mc_filter[2];
	int rx_mode;
	/* !IFF_PROMISC */
	rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
	mc_filter[1] = mc_filter[0] = 0xffffffff;

	outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);

	outl(mc_filter[0], ioaddr + MAR0 + 0);
	outl(mc_filter[1], ioaddr + MAR0 + 4);
}

static void rtl_reset(struct eth_device *dev)
{
	int i;

	outb(CmdReset, ioaddr + ChipCmd);

	cur_rx = 0;
	cur_tx = 0;

	/* Give the chip 10ms to finish the reset. */
	for (i=0; i<100; ++i){
		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
		udelay (100); /* wait 100us */
	}


	for (i = 0; i < ETH_ALEN; i++)
		outb(dev->enetaddr[i], ioaddr + MAC0 + i);

	/* Must enable Tx/Rx before setting transfer thresholds! */
	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
	outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
		ioaddr + RxConfig);		/* accept no frames yet!  */
	outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);

	/* The Linux driver changes Config1 here to use a different LED pattern
	 * for half duplex or full/autodetect duplex (for full/autodetect, the
	 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
	 * TX/RX, Link100, Link10).  This is messy, because it doesn't match
	 * the inscription on the mounting bracket.  It should not be changed
	 * from the configuration EEPROM default, because the card manufacturer
	 * should have set that to match the card.  */

	debug_cond(DEBUG_RX,
		"rx ring address is %lX\n",(unsigned long)rx_ring);
	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
	outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);

	/* If we add multicast support, the MAR0 register would have to be
	 * initialized to 0xffffffffffffffff (two 32 bit accesses).  Etherboot
	 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast.	*/

	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);

	outl(rtl8139_rx_config, ioaddr + RxConfig);

	/* Start the chip's Tx and Rx process. */
	outl(0, ioaddr + RxMissed);

	/* set_rx_mode */
	set_rx_mode(dev);

	/* Disable all known interrupts by setting the interrupt mask. */
	outw(0, ioaddr + IntrMask);
}

static int rtl_transmit(struct eth_device *dev, void *packet, int length)
{
	unsigned int status;
	unsigned long txstatus;
	unsigned int len = length;
	int i = 0;

	ioaddr = dev->iobase;

	memcpy((char *)tx_buffer, (char *)packet, (int)length);

	debug_cond(DEBUG_TX, "sending %d bytes\n", len);

	/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
	 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
	while (len < ETH_ZLEN) {
		tx_buffer[len++] = '\0';
	}

	flush_cache((unsigned long)tx_buffer, length);
	outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
		ioaddr + TxStatus0 + cur_tx*4);

	do {
		status = inw(ioaddr + IntrStatus);
		/* Only acknlowledge interrupt sources we can properly handle
		 * here - the RxOverflow/RxFIFOOver MUST be handled in the
		 * rtl_poll() function.	 */
		outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
		if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
		udelay(10);
	} while (i++ < RTL_TIMEOUT);

	txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);

	if (status & TxOK) {
		cur_tx = (cur_tx + 1) % NUM_TX_DESC;

		debug_cond(DEBUG_TX,
			"tx done, status %hX txstatus %lX\n",
			status, txstatus);

		return length;
	} else {

		debug_cond(DEBUG_TX,
			"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
			10*i, status, txstatus);

		rtl_reset(dev);

		return 0;
	}
}

static int rtl_poll(struct eth_device *dev)
{
	unsigned int status;
	unsigned int ring_offs;
	unsigned int rx_size, rx_status;
	int length=0;

	ioaddr = dev->iobase;

	if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
		return 0;
	}

	status = inw(ioaddr + IntrStatus);
	/* See below for the rest of the interrupt acknowledges.  */
	outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);

	debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);

	ring_offs = cur_rx % RX_BUF_LEN;
	/* ring_offs is guaranteed being 4-byte aligned */
	rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
	rx_size = rx_status >> 16;
	rx_status &= 0xffff;

	if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
	    (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
		printf("rx error %hX\n", rx_status);
		rtl_reset(dev); /* this clears all interrupts still pending */
		return 0;
	}

	/* Received a good packet */
	length = rx_size - 4;	/* no one cares about the FCS */
	if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
		int semi_count = RX_BUF_LEN - ring_offs - 4;
		unsigned char rxdata[RX_BUF_LEN];

		memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
		memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);

		net_process_received_packet(rxdata, length);
		debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
			semi_count, rx_size-4-semi_count);
	} else {
		net_process_received_packet(rx_ring + ring_offs + 4, length);
		debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
	}
	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);

	cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
	outw(cur_rx - 16, ioaddr + RxBufPtr);
	/* See RTL8139 Programming Guide V0.1 for the official handling of
	 * Rx overflow situations.  The document itself contains basically no
	 * usable information, except for a few exception handling rules.  */
	outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
	return length;
}

static void rtl_disable(struct eth_device *dev)
{
	int i;

	ioaddr = dev->iobase;

	/* reset the chip */
	outb(CmdReset, ioaddr + ChipCmd);

	/* Give the chip 10ms to finish the reset. */
	for (i=0; i<100; ++i){
		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
		udelay (100); /* wait 100us */
	}
}
Commit	Line	Data
63f34912 WD	1	/*
	2	* rtl8139.c : U-Boot driver for the RealTek RTL8139
	3	*
	4	* Masami Komiya ([email protected])
	5	*
	6	* Most part is taken from rtl8139.c of etherboot
	7	*
	8	*/
	9
	10	/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
	11
	12	ported from the linux driver written by Donald Becker
	13	by Rainer Bawidamann ([email protected]) 1999
	14
	15	This software may be used and distributed according to the terms
	16	of the GNU Public License, incorporated herein by reference.
	17
	18	changes to the original driver:
	19	- removed support for interrupts, switching to polling mode (yuck!)
	20	- removed support for the 8129 chip (external MII)
	21
	22	*/
	23
	24	/*********************************************************************/
	25	/* Revision History */
	26	/*********************************************************************/
	27
	28	/*
	29	28 Dec 2002 [email protected] (Ken Yap)
	30	Put in virt_to_bus calls to allow Etherboot relocation.
	31
	32	06 Apr 2001 [email protected] (Ken Yap)
	33	Following email from Hyun-Joon Cha, added a disable routine, otherwise
	34	NIC remains live and can crash the kernel later.
	35
	36	4 Feb 2000 [email protected] (Klaus Espenlaub)
	37	Shuffled things around, removed the leftovers from the 8129 support
	38	that was in the Linux driver and added a bit more 8139 definitions.
	39	Moved the 8K receive buffer to a fixed, available address outside the
	40	0x98000-0x9ffff range. This is a bit of a hack, but currently the only
	41	way to make room for the Etherboot features that need substantial amounts
	42	of code like the ANSI console support. Currently the buffer is just below
	43	0x10000, so this even conforms to the tagged boot image specification,
	44	which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
	45	interpretation of this "reserved" is that Etherboot may do whatever it
	46	likes, as long as its environment is kept intact (like the BIOS
b6e4c403	47	variables). Hopefully fixed rtl_poll() once and for all. The symptoms
63f34912 WD	48	were that if Etherboot was left at the boot menu for several minutes, the
	49	first eth_poll failed. Seems like I am the only person who does this.
	50	First of all I fixed the debugging code and then set out for a long bug
	51	hunting session. It took me about a week full time work - poking around
	52	various places in the driver, reading Don Becker's and Jeff Garzik's Linux
	53	driver and even the FreeBSD driver (what a piece of crap!) - and
	54	eventually spotted the nasty thing: the transmit routine was acknowledging
	55	each and every interrupt pending, including the RxOverrun and RxFIFIOver
b6e4c403	56	interrupts. This confused the RTL8139 thoroughly. It destroyed the
63f34912 WD	57	Rx ring contents by dumping the 2K FIFO contents right where we wanted to
	58	get the next packet. Oh well, what fun.
	59
b6e4c403	60	18 Jan 2000 [email protected] (Marty Connor)
63f34912 WD	61	Drastically simplified error handling. Basically, if any error
	62	in transmission or reception occurs, the card is reset.
	63	Also, pointed all transmit descriptors to the same buffer to
b6e4c403	64	save buffer space. This should decrease driver size and avoid
63f34912 WD	65	corruption because of exceeding 32K during runtime.
63f34912 WD	66
b6e4c403	67	28 Jul 1999 (Matthias Meixner - [email protected])
63f34912 WD	68	rtl_poll was quite broken: it used the RxOK interrupt flag instead
	69	of the RxBufferEmpty flag which often resulted in very bad
	70	transmission performace - below 1kBytes/s.
	71
	72	*/
	73
	74	#include <common.h>
1eb69ae4	75	#include <cpu_func.h>
63f34912 WD	76	#include <malloc.h>
63f34912 WD	77	#include <net.h>
0b252f50	78	#include <netdev.h>
63f34912 WD	79	#include <asm/io.h>
	80	#include <pci.h>
	81
d1276c76	82	#define RTL_TIMEOUT 100000
63f34912	83
63f34912 WD	84	/* PCI Tuning Parameters
63f34912 WD	85	Threshold is bytes transferred to chip before transmission starts. */
b6e4c403 WD	86	#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
	87	#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
	88	#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
	89	#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
	90	#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
63f34912 WD	91	#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
	92	#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
	93	#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
	94
ecc6aa8c WD	95	#define DEBUG_TX 0 /* set to 1 to enable debug code */
ecc6aa8c WD	96	#define DEBUG_RX 0 /* set to 1 to enable debug code */
63f34912	97
b6e4c403 WD	98	#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
b6e4c403 WD	99	#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
63f34912 WD	100
	101	/* Symbolic offsets to registers. */
	102	enum RTL8139_registers {
	103	MAC0=0, /* Ethernet hardware address. */
	104	MAR0=8, /* Multicast filter. */
	105	TxStatus0=0x10, /* Transmit status (four 32bit registers). */
	106	TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
	107	RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
	108	ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
	109	IntrMask=0x3C, IntrStatus=0x3E,
	110	TxConfig=0x40, RxConfig=0x44,
	111	Timer=0x48, /* general-purpose counter. */
	112	RxMissed=0x4C, /* 24 bits valid, write clears. */
	113	Cfg9346=0x50, Config0=0x51, Config1=0x52,
	114	TimerIntrReg=0x54, /* intr if gp counter reaches this value */
	115	MediaStatus=0x58,
	116	Config3=0x59,
	117	MultiIntr=0x5C,
	118	RevisionID=0x5E, /* revision of the RTL8139 chip */
	119	TxSummary=0x60,
	120	MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
	121	NWayExpansion=0x6A,
	122	DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
	123	NWayTestReg=0x70,
	124	RxCnt=0x72, /* packet received counter */
	125	CSCR=0x74, /* chip status and configuration register */
	126	PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
	127	/* from 0x84 onwards are a number of power management/wakeup frame
	128	* definitions we will probably never need to know about. */
	129	};
	130
	131	enum ChipCmdBits {
	132	CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
	133
	134	/* Interrupt register bits, using my own meaningful names. */
	135	enum IntrStatusBits {
	136	PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
	137	RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
	138	TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
	139	};
	140	enum TxStatusBits {
	141	TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
	142	TxOutOfWindow=0x20000000, TxAborted=0x40000000,
	143	TxCarrierLost=0x80000000,
	144	};
	145	enum RxStatusBits {
	146	RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
	147	RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
	148	RxBadAlign=0x0002, RxStatusOK=0x0001,
	149	};
	150
	151	enum MediaStatusBits {
	152	MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
	153	MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
	154	};
	155
	156	enum MIIBMCRBits {
	157	BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
	158	BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
	159	};
	160
	161	enum CSCRBits {
	162	CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
	163	CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
164	CSCR_LinkDownCmd=0x0f3c0,
165	};
166
167	/* Bits in RxConfig. */
168	enum rx_mode_bits {
169	RxCfgWrap=0x80,
170	AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
171	AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
172	};
173
174	static int ioaddr;
175	static unsigned int cur_rx,cur_tx;
176
177	/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
178	static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
179	static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
180
181	static int rtl8139_probe(struct eth_device dev, bd_t bis);
182	static int read_eeprom(int location, int addr_len);
183	static void rtl_reset(struct eth_device *dev);
86f3cded	184	static int rtl_transmit(struct eth_device dev, void packet, int length);
63f34912 WD	185	static int rtl_poll(struct eth_device *dev);
63f34912 WD	186	static void rtl_disable(struct eth_device *dev);
67bb9842	187	static int rtl_bcast_addr(struct eth_device dev, const u8 bcast_mac, int join)
85eb5caf WD	188	{
	189	return (0);
	190	}
63f34912 WD	191
	192	static struct pci_device_id supported[] = {
	193	{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
da012ab6	194	{PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
63f34912 WD	195	{}
	196	};
	197
	198	int rtl8139_initialize(bd_t *bis)
	199	{
	200	pci_dev_t devno;
	201	int card_number = 0;
	202	struct eth_device *dev;
	203	u32 iobase;
	204	int idx=0;
	205
	206	while(1){
	207	/* Find RTL8139 */
	208	if ((devno = pci_find_devices(supported, idx++)) < 0)
	209	break;
	210
	211	pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
	212	iobase &= ~0xf;
	213
	214	debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
	215
	216	dev = (struct eth_device )malloc(sizeof dev);
986f7278 NI	217	if (!dev) {
	218	printf("Can not allocate memory of rtl8139\n");
	219	break;
	220	}
	221	memset(dev, 0, sizeof(*dev));
63f34912 WD	222
	223	sprintf (dev->name, "RTL8139#%d", card_number);
	224
	225	dev->priv = (void *) devno;
	226	dev->iobase = (int)bus_to_phys(iobase);
	227	dev->init = rtl8139_probe;
	228	dev->halt = rtl_disable;
	229	dev->send = rtl_transmit;
	230	dev->recv = rtl_poll;
53a5c424	231	dev->mcast = rtl_bcast_addr;
63f34912 WD	232
	233	eth_register (dev);
	234
	235	card_number++;
	236
	237	pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
	238
	239	udelay (10 * 1000);
	240	}
	241
	242	return card_number;
	243	}
	244
	245	static int rtl8139_probe(struct eth_device dev, bd_t bis)
	246	{
	247	int i;
63f34912 WD	248	int addr_len;
	249	unsigned short ap = (unsigned short )dev->enetaddr;
	250
	251	ioaddr = dev->iobase;
	252
	253	/* Bring the chip out of low-power mode. */
	254	outb(0x00, ioaddr + Config1);
	255
	256	addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
	257	for (i = 0; i < 3; i++)
756f586a	258	*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
63f34912	259
63f34912 WD	260	rtl_reset(dev);
	261
	262	if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
	263	printf("Cable not connected or other link failure\n");
422b1a01	264	return -1 ;
63f34912 WD	265	}
63f34912 WD	266
422b1a01	267	return 0;
63f34912 WD	268	}
	269
	270	/* Serial EEPROM section. */
	271
	272	/* EEPROM_Ctrl bits. */
b6e4c403 WD	273	#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
	274	#define EE_CS 0x08 /* EEPROM chip select. */
	275	#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
	276	#define EE_WRITE_0 0x00
	277	#define EE_WRITE_1 0x02
	278	#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
63f34912 WD	279	#define EE_ENB (0x80 \| EE_CS)
	280
	281	/*
	282	Delay between EEPROM clock transitions.
8ed44d91	283	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
63f34912 WD	284	*/
63f34912 WD	285
b6e4c403	286	#define eeprom_delay() inl(ee_addr)
63f34912 WD	287
63f34912 WD	288	/* The EEPROM commands include the alway-set leading bit. */
b6e4c403 WD	289	#define EE_WRITE_CMD (5)
	290	#define EE_READ_CMD (6)
	291	#define EE_ERASE_CMD (7)
63f34912 WD	292
	293	static int read_eeprom(int location, int addr_len)
	294	{
	295	int i;
	296	unsigned int retval = 0;
	297	long ee_addr = ioaddr + Cfg9346;
	298	int read_cmd = location \| (EE_READ_CMD << addr_len);
	299
	300	outb(EE_ENB & ~EE_CS, ee_addr);
	301	outb(EE_ENB, ee_addr);
	302	eeprom_delay();
	303
	304	/* Shift the read command bits out. */
	305	for (i = 4 + addr_len; i >= 0; i--) {
	306	int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
	307	outb(EE_ENB \| dataval, ee_addr);
	308	eeprom_delay();
	309	outb(EE_ENB \| dataval \| EE_SHIFT_CLK, ee_addr);
	310	eeprom_delay();
	311	}
	312	outb(EE_ENB, ee_addr);
	313	eeprom_delay();
	314
	315	for (i = 16; i > 0; i--) {
	316	outb(EE_ENB \| EE_SHIFT_CLK, ee_addr);
	317	eeprom_delay();
	318	retval = (retval << 1) \| ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
	319	outb(EE_ENB, ee_addr);
	320	eeprom_delay();
	321	}
	322
	323	/* Terminate the EEPROM access. */
	324	outb(~EE_CS, ee_addr);
	325	eeprom_delay();
	326	return retval;
	327	}
	328
	329	static const unsigned int rtl8139_rx_config =
	330	(RX_BUF_LEN_IDX << 11) \|
	331	(RX_FIFO_THRESH << 13) \|
	332	(RX_DMA_BURST << 8);
	333
	334	static void set_rx_mode(struct eth_device *dev) {
	335	unsigned int mc_filter[2];
	336	int rx_mode;
	337	/* !IFF_PROMISC */
	338	rx_mode = AcceptBroadcast \| AcceptMulticast \| AcceptMyPhys;
	339	mc_filter[1] = mc_filter[0] = 0xffffffff;
	340
	341	outl(rtl8139_rx_config \| rx_mode, ioaddr + RxConfig);
	342
	343	outl(mc_filter[0], ioaddr + MAR0 + 0);
	344	outl(mc_filter[1], ioaddr + MAR0 + 4);
	345	}
	346
	347	static void rtl_reset(struct eth_device *dev)
	348	{
	349	int i;
	350
	351	outb(CmdReset, ioaddr + ChipCmd);
	352
	353	cur_rx = 0;
	354	cur_tx = 0;
	355
356	/* Give the chip 10ms to finish the reset. */
357	for (i=0; i<100; ++i){
358	if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
359	udelay (100); /* wait 100us */
360	}
361
362
363	for (i = 0; i < ETH_ALEN; i++)
364	outb(dev->enetaddr[i], ioaddr + MAC0 + i);
365
366	/* Must enable Tx/Rx before setting transfer thresholds! */
367	outb(CmdRxEnb \| CmdTxEnb, ioaddr + ChipCmd);
368	outl((RX_FIFO_THRESH<<13) \| (RX_BUF_LEN_IDX<<11) \| (RX_DMA_BURST<<8),
369	ioaddr + RxConfig); /* accept no frames yet! */
370	outl((TX_DMA_BURST<<8)\|0x03000000, ioaddr + TxConfig);
371
372	/* The Linux driver changes Config1 here to use a different LED pattern
373	* for half duplex or full/autodetect duplex (for full/autodetect, the
374	* outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
375	* TX/RX, Link100, Link10). This is messy, because it doesn't match
376	* the inscription on the mounting bracket. It should not be changed
377	* from the configuration EEPROM default, because the card manufacturer
378	* should have set that to match the card. */
379
ecc6aa8c WD	380	debug_cond(DEBUG_RX,
ecc6aa8c WD	381	"rx ring address is %lX\n",(unsigned long)rx_ring);
96a23674	382	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
63f34912 WD	383	outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
	384
	385	/* If we add multicast support, the MAR0 register would have to be
	386	* initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
b6e4c403	387	* only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
63f34912 WD	388
	389	outb(CmdRxEnb \| CmdTxEnb, ioaddr + ChipCmd);
	390
	391	outl(rtl8139_rx_config, ioaddr + RxConfig);
	392
	393	/* Start the chip's Tx and Rx process. */
	394	outl(0, ioaddr + RxMissed);
	395
	396	/* set_rx_mode */
	397	set_rx_mode(dev);
	398
	399	/* Disable all known interrupts by setting the interrupt mask. */
	400	outw(0, ioaddr + IntrMask);
	401	}
	402
86f3cded	403	static int rtl_transmit(struct eth_device dev, void packet, int length)
63f34912	404	{
d1276c76	405	unsigned int status;
63f34912 WD	406	unsigned long txstatus;
63f34912 WD	407	unsigned int len = length;
d1276c76	408	int i = 0;
63f34912 WD	409
	410	ioaddr = dev->iobase;
	411
	412	memcpy((char )tx_buffer, (char )packet, (int)length);
	413
ecc6aa8c	414	debug_cond(DEBUG_TX, "sending %d bytes\n", len);
63f34912 WD	415
	416	/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
	417	* bytes are sent automatically for the FCS, totalling to 64 bytes). */
	418	while (len < ETH_ZLEN) {
	419	tx_buffer[len++] = '\0';
	420	}
	421
96a23674	422	flush_cache((unsigned long)tx_buffer, length);
63f34912 WD	423	outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
	424	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) \| len,
	425	ioaddr + TxStatus0 + cur_tx*4);
	426
63f34912 WD	427	do {
	428	status = inw(ioaddr + IntrStatus);
	429	/* Only acknlowledge interrupt sources we can properly handle
	430	* here - the RxOverflow/RxFIFOOver MUST be handled in the
b6e4c403	431	* rtl_poll() function. */
63f34912 WD	432	outw(status & (TxOK \| TxErr \| PCIErr), ioaddr + IntrStatus);
63f34912 WD	433	if ((status & (TxOK \| TxErr \| PCIErr)) != 0) break;
d1276c76 SK	434	udelay(10);
d1276c76 SK	435	} while (i++ < RTL_TIMEOUT);
63f34912 WD	436
	437	txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
	438
	439	if (status & TxOK) {
	440	cur_tx = (cur_tx + 1) % NUM_TX_DESC;
ecc6aa8c WD	441
	442	debug_cond(DEBUG_TX,
	443	"tx done, status %hX txstatus %lX\n",
	444	status, txstatus);
	445
63f34912 WD	446	return length;
63f34912 WD	447	} else {
ecc6aa8c WD	448
	449	debug_cond(DEBUG_TX,
	450	"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
	451	10*i, status, txstatus);
	452
63f34912 WD	453	rtl_reset(dev);
	454
	455	return 0;
	456	}
	457	}
	458
	459	static int rtl_poll(struct eth_device *dev)
	460	{
	461	unsigned int status;
	462	unsigned int ring_offs;
	463	unsigned int rx_size, rx_status;
	464	int length=0;
	465
	466	ioaddr = dev->iobase;
	467
	468	if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
	469	return 0;
	470	}
	471
	472	status = inw(ioaddr + IntrStatus);
	473	/* See below for the rest of the interrupt acknowledges. */
	474	outw(status & ~(RxFIFOOver \| RxOverflow \| RxOK), ioaddr + IntrStatus);
	475
ecc6aa8c	476	debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
63f34912 WD	477
63f34912 WD	478	ring_offs = cur_rx % RX_BUF_LEN;
96a23674	479	/* ring_offs is guaranteed being 4-byte aligned */
c2f896b8	480	rx_status = le32_to_cpu((unsigned int )(rx_ring + ring_offs));
63f34912 WD	481	rx_size = rx_status >> 16;
	482	rx_status &= 0xffff;
	483
	484	if ((rx_status & (RxBadSymbol\|RxRunt\|RxTooLong\|RxCRCErr\|RxBadAlign)) \|\|
	485	(rx_size < ETH_ZLEN) \|\| (rx_size > ETH_FRAME_LEN + 4)) {
	486	printf("rx error %hX\n", rx_status);
b6e4c403	487	rtl_reset(dev); /* this clears all interrupts still pending */
63f34912 WD	488	return 0;
	489	}
	490
	491	/* Received a good packet */
	492	length = rx_size - 4; /* no one cares about the FCS */
	493	if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
	494	int semi_count = RX_BUF_LEN - ring_offs - 4;
	495	unsigned char rxdata[RX_BUF_LEN];
	496
	497	memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
	498	memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
	499
1fd92db8	500	net_process_received_packet(rxdata, length);
ecc6aa8c WD	501	debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
ecc6aa8c WD	502	semi_count, rx_size-4-semi_count);
63f34912	503	} else {
1fd92db8	504	net_process_received_packet(rx_ring + ring_offs + 4, length);
ecc6aa8c	505	debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
63f34912	506	}
96a23674	507	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
63f34912 WD	508
	509	cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
	510	outw(cur_rx - 16, ioaddr + RxBufPtr);
	511	/* See RTL8139 Programming Guide V0.1 for the official handling of
	512	* Rx overflow situations. The document itself contains basically no
	513	* usable information, except for a few exception handling rules. */
	514	outw(status & (RxFIFOOver \| RxOverflow \| RxOK), ioaddr + IntrStatus);
	515	return length;
	516	}
	517
	518	static void rtl_disable(struct eth_device *dev)
	519	{
	520	int i;
	521
b6e4c403 WD	522	ioaddr = dev->iobase;
b6e4c403 WD	523
63f34912 WD	524	/* reset the chip */
	525	outb(CmdReset, ioaddr + ChipCmd);
	526
	527	/* Give the chip 10ms to finish the reset. */
	528	for (i=0; i<100; ++i){
	529	if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
	530	udelay (100); /* wait 100us */
	531	}
	532	}