projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| dd84058d | 1 | CONFIG_PPC=y |
| 278b90ce | 2 | CONFIG_SYS_TEXT_BASE=0xFC000000 |
| a09fea1d TR |
3 | CONFIG_ENV_SIZE=0x2000 |
| 4 | CONFIG_ENV_SECT_SIZE=0x20000 | |
| ff3bb0c4 | 5 | CONFIG_SYS_CLK_FREQ=33333333 |
| dd84058d MY |
6 | CONFIG_MPC83xx=y |
| 7 | CONFIG_TARGET_MPC8308_P1M=y | |
| 21c1502a MS |
8 | CONFIG_SYSTEM_PLL_VCO_DIV_2=y |
| 9 | CONFIG_SYSTEM_PLL_FACTOR_4_1=y | |
| 10 | CONFIG_CORE_PLL_RATIO_3_1=y | |
| 11 | CONFIG_BOOT_MEMORY_SPACE_LOW=y | |
| 12 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
| 30915ab9 MS |
13 | CONFIG_BAT0=y |
| 14 | CONFIG_BAT0_NAME="DDR" | |
| 15 | CONFIG_BAT0_BASE=0x00000000 | |
| 16 | CONFIG_BAT0_LENGTH_128_MBYTES=y | |
| 17 | CONFIG_BAT0_ACCESS_RW=y | |
| 18 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y | |
| 19 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y | |
| 20 | CONFIG_BAT0_USER_MODE_VALID=y | |
| 21 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
| 22 | CONFIG_BAT1=y | |
| 23 | CONFIG_BAT1_NAME="IMMRBAR" | |
| 24 | CONFIG_BAT1_BASE=0xE0000000 | |
| 25 | CONFIG_BAT1_LENGTH_8_MBYTES=y | |
| 26 | CONFIG_BAT1_ACCESS_RW=y | |
| 27 | CONFIG_BAT1_ICACHE_INHIBITED=y | |
| 28 | CONFIG_BAT1_ICACHE_GUARDED=y | |
| 29 | CONFIG_BAT1_DCACHE_INHIBITED=y | |
| 30 | CONFIG_BAT1_DCACHE_GUARDED=y | |
| 31 | CONFIG_BAT1_USER_MODE_VALID=y | |
| 32 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y | |
| 33 | CONFIG_BAT2=y | |
| 34 | CONFIG_BAT2_NAME="FLASH" | |
| 35 | CONFIG_BAT2_BASE=0xFC000000 | |
| 36 | CONFIG_BAT2_LENGTH_8_MBYTES=y | |
| 37 | CONFIG_BAT2_ACCESS_RW=y | |
| 38 | CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y | |
| 39 | CONFIG_BAT2_DCACHE_INHIBITED=y | |
| 40 | CONFIG_BAT2_DCACHE_GUARDED=y | |
| 41 | CONFIG_BAT2_USER_MODE_VALID=y | |
| 42 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y | |
| 43 | CONFIG_BAT3=y | |
| 44 | CONFIG_BAT3_NAME="STACKINDCACHE" | |
| 45 | CONFIG_BAT3_BASE=0xE6000000 | |
| 46 | CONFIG_BAT3_ACCESS_RW=y | |
| 47 | CONFIG_BAT3_USER_MODE_VALID=y | |
| 48 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y | |
| 9c5df7a2 MS |
49 | CONFIG_LBLAW0=y |
| 50 | CONFIG_LBLAW0_BASE=0xFC000000 | |
| 51 | CONFIG_LBLAW0_NAME="FLASH" | |
| 52 | CONFIG_LBLAW0_LENGTH_64_MBYTES=y | |
| 53 | CONFIG_LBLAW1=y | |
| 54 | CONFIG_LBLAW1_BASE=0xFBFF0000 | |
| 55 | CONFIG_LBLAW1_NAME="SJA1000" | |
| 56 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y | |
| 57 | CONFIG_LBLAW2=y | |
| 58 | CONFIG_LBLAW2_BASE=0xFBFF8000 | |
| 59 | CONFIG_LBLAW2_NAME="CPLD" | |
| 60 | CONFIG_LBLAW2_LENGTH_32_KBYTES=y | |
| 344a0e43 TR |
61 | CONFIG_ELBC_BR0_OR0=y |
| 62 | CONFIG_BR0_OR0_NAME="FLASH" | |
| 63 | CONFIG_BR0_OR0_BASE=0xFC000000 | |
| 64 | CONFIG_BR0_PORTSIZE_16BIT=y | |
| 65 | CONFIG_OR0_AM_64_MBYTES=y | |
| 66 | CONFIG_OR0_XAM_SET=y | |
| 67 | CONFIG_OR0_SCY_4=y | |
| 68 | CONFIG_OR0_CSNT_EARLIER=y | |
| 69 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y | |
| 70 | CONFIG_OR0_XACS_EXTENDED=y | |
| 71 | CONFIG_OR0_TRLX_RELAXED=y | |
| 72 | CONFIG_OR0_EHTR_8_CYCLE=y | |
| 73 | CONFIG_ELBC_BR1_OR1=y | |
| 74 | CONFIG_BR1_OR1_NAME="SJA1000" | |
| 75 | CONFIG_BR1_OR1_BASE=0xFBFF0000 | |
| 76 | CONFIG_OR1_SCY_5=y | |
| 77 | CONFIG_OR1_EHTR_1_CYCLE=y | |
| 78 | CONFIG_ELBC_BR2_OR2=y | |
| 79 | CONFIG_BR2_OR2_NAME="CPLD" | |
| 80 | CONFIG_BR2_OR2_BASE=0xFBFF8000 | |
| 81 | CONFIG_OR2_SCY_4=y | |
| 82 | CONFIG_OR2_EHTR_1_CYCLE=y | |
| be5abb0a MS |
83 | CONFIG_HID0_FINAL_EMCP=y |
| 84 | CONFIG_HID0_FINAL_DPM=y | |
| 85 | CONFIG_HID0_FINAL_ICE=y | |
| 86 | CONFIG_HID2_HBE=y | |
| ba463c11 MS |
87 | CONFIG_SICR_ESDHC_A_GPIO=y |
| 88 | CONFIG_SICR_ESDHC_B_GPIO=y | |
| 89 | CONFIG_SICR_ESDHC_C_GTM=y | |
| 90 | CONFIG_SICR_GPIO_A_TSEC2=y | |
| 91 | CONFIG_SICR_GPIO_B_TSEC2=y | |
| 92 | CONFIG_SICR_IEEE1588_A_GPIO=y | |
| 93 | CONFIG_SICR_GTM_GPIO=y | |
| 94 | CONFIG_SICR_GPIOSEL_IEEE1588=y | |
| 73df96a3 MS |
95 | CONFIG_ACR_PIPE_DEP_4=y |
| 96 | CONFIG_ACR_RPTCNT_4=y | |
| e35012e8 | 97 | CONFIG_SPCR_TSECEP_3=y |
| 344a0e43 TR |
98 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
| 99 | CONFIG_LCRR_CLKDIV_2=y | |
| 73223f0e SG |
100 | CONFIG_OF_BOARD_SETUP=y |
| 101 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
| bb597c0e | 102 | CONFIG_BOOTDELAY=5 |
| adad96e6 | 103 | CONFIG_HUSH_PARSER=y |
| d021e942 | 104 | # CONFIG_AUTO_COMPLETE is not set |
| ad12dc18 | 105 | CONFIG_CMD_IMLS=y |
| 78d1e1d0 | 106 | CONFIG_CMD_I2C=y |
| 6500ec7a | 107 | CONFIG_CMD_PCI=y |
| ef0f2f57 | 108 | # CONFIG_CMD_SETEXPR is not set |
| 78d1e1d0 | 109 | CONFIG_CMD_DHCP=y |
| 89cb2b5f | 110 | CONFIG_CMD_MII=y |
| 78d1e1d0 | 111 | CONFIG_CMD_PING=y |
| e91907a1 | 112 | CONFIG_ENV_OVERWRITE=y |
| cb6617a7 | 113 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y |
| a09fea1d TR |
114 | CONFIG_ENV_ADDR=0xFC060000 |
| 115 | CONFIG_ENV_ADDR_REDUND=0xFC080000 | |
| 8728c97e | 116 | # CONFIG_MMC is not set |
| e856bdcf | 117 | CONFIG_MTD_NOR_FLASH=y |
| 2fe88d45 AF |
118 | CONFIG_FLASH_CFI_DRIVER=y |
| 119 | CONFIG_SYS_FLASH_PROTECTION=y | |
| 120 | CONFIG_SYS_FLASH_CFI=y | |
| 306881a0 TR |
121 | CONFIG_PHY_ATHEROS=y |
| 122 | CONFIG_PHY_BROADCOM=y | |
| 123 | CONFIG_PHY_DAVICOM=y | |
| 124 | CONFIG_PHY_LXT=y | |
| a8ca5c8a | 125 | CONFIG_PHY_MARVELL=y |
| 306881a0 TR |
126 | CONFIG_PHY_NATSEMI=y |
| 127 | CONFIG_PHY_REALTEK=y | |
| 128 | CONFIG_PHY_SMSC=y | |
| 129 | CONFIG_PHY_VITESSE=y | |
| d7869b21 | 130 | CONFIG_MII=y |
| 17151052 | 131 | CONFIG_TSEC_ENET=y |
| 9e39003e | 132 | CONFIG_SYS_NS16550=y |
| 69e173eb | 133 | CONFIG_OF_LIBFDT=y |