projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ff3bb0c4 MS |
1 | CONFIG_PPC=y |
| 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 | |
| a09fea1d TR |
3 | CONFIG_ENV_SIZE=0x4000 |
| 4 | CONFIG_ENV_SECT_SIZE=0x10000 | |
| ff3bb0c4 MS |
5 | CONFIG_SYS_CLK_FREQ=66666667 |
| 6 | CONFIG_MPC83xx=y | |
| 7 | CONFIG_TARGET_MPC837XERDB=y | |
| 21c1502a MS |
8 | CONFIG_DDR_MC_CLOCK_MODE_1_1=y |
| 9 | CONFIG_SYSTEM_PLL_FACTOR_5_1=y | |
| 10 | CONFIG_CORE_PLL_RATIO_2_1=y | |
| 11 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
| 12 | CONFIG_TSEC1_MODE_RGMII=y | |
| 13 | CONFIG_TSEC2_MODE_RGMII=y | |
| 14 | CONFIG_LDP_PIN_MUX_STATE_0=y | |
| 30915ab9 MS |
15 | CONFIG_BAT0=y |
| 16 | CONFIG_BAT0_NAME="SDRAM_LOWER" | |
| 17 | CONFIG_BAT0_BASE=0x00000000 | |
| 18 | CONFIG_BAT0_LENGTH_256_MBYTES=y | |
| 19 | CONFIG_BAT0_ACCESS_RW=y | |
| 20 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y | |
| 21 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y | |
| 22 | CONFIG_BAT0_USER_MODE_VALID=y | |
| 23 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
| 24 | CONFIG_BAT1=y | |
| 25 | CONFIG_BAT1_NAME="SDRAM_UPPER" | |
| 26 | CONFIG_BAT1_BASE=0x10000000 | |
| 27 | CONFIG_BAT1_LENGTH_256_MBYTES=y | |
| 28 | CONFIG_BAT1_ACCESS_RW=y | |
| 29 | CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y | |
| 30 | CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y | |
| 31 | CONFIG_BAT1_USER_MODE_VALID=y | |
| 32 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y | |
| 33 | CONFIG_BAT2=y | |
| 34 | CONFIG_BAT2_NAME="IMMR" | |
| 35 | CONFIG_BAT2_BASE=0xE0000000 | |
| 36 | CONFIG_BAT2_LENGTH_8_MBYTES=y | |
| 37 | CONFIG_BAT2_ACCESS_RW=y | |
| 38 | CONFIG_BAT2_ICACHE_INHIBITED=y | |
| 39 | CONFIG_BAT2_ICACHE_GUARDED=y | |
| 40 | CONFIG_BAT2_DCACHE_INHIBITED=y | |
| 41 | CONFIG_BAT2_DCACHE_GUARDED=y | |
| 42 | CONFIG_BAT2_USER_MODE_VALID=y | |
| 43 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y | |
| 44 | CONFIG_BAT3=y | |
| 45 | CONFIG_BAT3_NAME="L2_SWITCH" | |
| 46 | CONFIG_BAT3_BASE=0xF0000000 | |
| 47 | CONFIG_BAT3_ACCESS_RW=y | |
| 48 | CONFIG_BAT3_ICACHE_INHIBITED=y | |
| 49 | CONFIG_BAT3_ICACHE_GUARDED=y | |
| 50 | CONFIG_BAT3_DCACHE_INHIBITED=y | |
| 51 | CONFIG_BAT3_DCACHE_GUARDED=y | |
| 52 | CONFIG_BAT3_USER_MODE_VALID=y | |
| 53 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y | |
| 9c5df7a2 MS |
54 | CONFIG_LBLAW0=y |
| 55 | CONFIG_LBLAW0_BASE=0xFE000000 | |
| 56 | CONFIG_LBLAW0_NAME="FLASH" | |
| 57 | CONFIG_LBLAW0_LENGTH_8_MBYTES=y | |
| 58 | CONFIG_LBLAW1=y | |
| 59 | CONFIG_LBLAW1_BASE=0xE0600000 | |
| 60 | CONFIG_LBLAW1_NAME="NAND" | |
| 61 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y | |
| 62 | CONFIG_LBLAW2=y | |
| 63 | CONFIG_LBLAW2_BASE=0xF0000000 | |
| 64 | CONFIG_LBLAW2_NAME="VSC7385" | |
| 65 | CONFIG_LBLAW2_LENGTH_128_KBYTES=y | |
| 344a0e43 TR |
66 | CONFIG_ELBC_BR0_OR0=y |
| 67 | CONFIG_BR0_OR0_NAME="FLASH" | |
| 68 | CONFIG_BR0_OR0_BASE=0xFE000000 | |
| 69 | CONFIG_BR0_PORTSIZE_16BIT=y | |
| 70 | CONFIG_OR0_AM_8_MBYTES=y | |
| 71 | CONFIG_OR0_SCY_9=y | |
| 72 | CONFIG_OR0_XACS_EXTENDED=y | |
| 73 | CONFIG_OR0_EHTR_1_CYCLE=y | |
| 74 | CONFIG_OR0_EAD_EXTRA=y | |
| 75 | CONFIG_ELBC_BR1_OR1=y | |
| 76 | CONFIG_BR1_OR1_NAME="NAND" | |
| 77 | CONFIG_BR1_OR1_BASE=0xE0600000 | |
| 78 | CONFIG_BR1_ERRORCHECKING_BOTH=y | |
| 79 | CONFIG_BR1_MACHINE_FCM=y | |
| 80 | CONFIG_OR1_SCY_1=y | |
| 81 | CONFIG_OR1_CSCT_8_CYCLE=y | |
| 82 | CONFIG_OR1_CST_ONE_CLOCK=y | |
| 83 | CONFIG_OR1_CHT_TWO_CLOCK=y | |
| 84 | CONFIG_OR1_TRLX_RELAXED=y | |
| 85 | CONFIG_OR1_EHTR_8_CYCLE=y | |
| 86 | CONFIG_ELBC_BR2_OR2=y | |
| 87 | CONFIG_BR2_OR2_NAME="VSC7385" | |
| 88 | CONFIG_BR2_OR2_BASE=0xF0000000 | |
| 89 | CONFIG_OR2_AM_128_KBYTES=y | |
| 90 | CONFIG_OR2_SCY_15=y | |
| 91 | CONFIG_OR2_CSNT_EARLIER=y | |
| 92 | CONFIG_OR2_XACS_EXTENDED=y | |
| 93 | CONFIG_OR2_SETA_EXTERNAL=y | |
| 94 | CONFIG_OR2_TRLX_RELAXED=y | |
| 95 | CONFIG_OR2_EHTR_8_CYCLE=y | |
| 96 | CONFIG_OR2_EAD_EXTRA=y | |
| be5abb0a MS |
97 | CONFIG_HID0_FINAL_EMCP=y |
| 98 | CONFIG_HID0_FINAL_ICE=y | |
| 99 | CONFIG_HID2_HBE=y | |
| 73df96a3 MS |
100 | CONFIG_ACR_PIPE_DEP_4=y |
| 101 | CONFIG_ACR_RPTCNT_4=y | |
| e35012e8 | 102 | CONFIG_SPCR_TSECEP_3=y |
| 344a0e43 TR |
103 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
| 104 | CONFIG_LCRR_CLKDIV_8=y | |
| ff3bb0c4 MS |
105 | CONFIG_OF_BOARD_SETUP=y |
| 106 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
| 107 | CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" | |
| 108 | CONFIG_BOOTDELAY=6 | |
| 109 | CONFIG_HUSH_PARSER=y | |
| 110 | CONFIG_CMD_IMLS=y | |
| 111 | CONFIG_CMD_I2C=y | |
| 112 | CONFIG_CMD_MMC=y | |
| 113 | CONFIG_CMD_PCI=y | |
| 114 | CONFIG_CMD_SATA=y | |
| 115 | CONFIG_CMD_USB=y | |
| 116 | # CONFIG_CMD_SETEXPR is not set | |
| 117 | CONFIG_CMD_MII=y | |
| 118 | CONFIG_CMD_PING=y | |
| 119 | CONFIG_CMD_DATE=y | |
| 120 | CONFIG_CMD_EXT2=y | |
| 121 | CONFIG_CMD_FAT=y | |
| e91907a1 | 122 | CONFIG_ENV_OVERWRITE=y |
| a09fea1d | 123 | CONFIG_ENV_ADDR=0xFE080000 |
| ff3bb0c4 MS |
124 | CONFIG_FSL_SATA=y |
| 125 | CONFIG_MTD_NOR_FLASH=y | |
| ff3bb0c4 MS |
126 | CONFIG_FLASH_CFI_DRIVER=y |
| 127 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
| 128 | CONFIG_SYS_FLASH_CFI=y | |
| 306881a0 TR |
129 | CONFIG_PHY_ATHEROS=y |
| 130 | CONFIG_PHY_BROADCOM=y | |
| 131 | CONFIG_PHY_DAVICOM=y | |
| 132 | CONFIG_PHY_LXT=y | |
| 133 | CONFIG_PHY_NATSEMI=y | |
| 134 | CONFIG_PHY_REALTEK=y | |
| 135 | CONFIG_PHY_SMSC=y | |
| 136 | CONFIG_PHY_VITESSE=y | |
| ff3bb0c4 MS |
137 | CONFIG_TSEC_ENET=y |
| 138 | CONFIG_SYS_NS16550=y | |
| 139 | CONFIG_USB=y | |
| 140 | CONFIG_USB_EHCI_HCD=y | |
| 141 | CONFIG_USB_STORAGE=y | |
| 142 | CONFIG_OF_LIBFDT=y |