projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7429b962 SG |
1 | /* |
| 2 | * Copyright 2016 Google Inc. | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #include <common.h> | |
| 8 | #include <dm.h> | |
| 9 | #include <pwm.h> | |
| 10 | #include <asm/io.h> | |
| 11 | #include <asm/arch/clock.h> | |
| 12 | #include <asm/arch/pwm.h> | |
| 13 | ||
| 7429b962 SG |
14 | struct tegra_pwm_priv { |
| 15 | struct pwm_ctlr *regs; | |
| 16 | }; | |
| 17 | ||
| 18 | static int tegra_pwm_set_config(struct udevice *dev, uint channel, | |
| 19 | uint period_ns, uint duty_ns) | |
| 20 | { | |
| 21 | struct tegra_pwm_priv *priv = dev_get_priv(dev); | |
| 22 | struct pwm_ctlr *regs = priv->regs; | |
| 23 | uint pulse_width; | |
| 24 | u32 reg; | |
| 25 | ||
| 26 | if (channel >= 4) | |
| 27 | return -EINVAL; | |
| 28 | debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); | |
| 29 | /* We ignore the period here and just use 32KHz */ | |
| 30 | clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768); | |
| 31 | ||
| 32 | pulse_width = duty_ns * 255 / period_ns; | |
| 33 | ||
| 34 | reg = pulse_width << PWM_WIDTH_SHIFT; | |
| 35 | reg |= 1 << PWM_DIVIDER_SHIFT; | |
| 36 | writel(reg, ®s[channel].control); | |
| 37 | debug("%s: pulse_width=%u\n", __func__, pulse_width); | |
| 38 | ||
| 39 | return 0; | |
| 40 | } | |
| 41 | ||
| 42 | static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable) | |
| 43 | { | |
| 44 | struct tegra_pwm_priv *priv = dev_get_priv(dev); | |
| 45 | struct pwm_ctlr *regs = priv->regs; | |
| 46 | ||
| 47 | if (channel >= 4) | |
| 48 | return -EINVAL; | |
| 49 | debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel); | |
| 50 | clrsetbits_le32(®s[channel].control, PWM_ENABLE_MASK, | |
| 51 | enable ? PWM_ENABLE_MASK : 0); | |
| 52 | ||
| 53 | return 0; | |
| 54 | } | |
| 55 | ||
| 56 | static int tegra_pwm_ofdata_to_platdata(struct udevice *dev) | |
| 57 | { | |
| 58 | struct tegra_pwm_priv *priv = dev_get_priv(dev); | |
| 59 | ||
| 4b0f21cf | 60 | priv->regs = (struct pwm_ctlr *)dev_read_addr(dev); |
| 7429b962 SG |
61 | |
| 62 | return 0; | |
| 63 | } | |
| 64 | ||
| 65 | static const struct pwm_ops tegra_pwm_ops = { | |
| 66 | .set_config = tegra_pwm_set_config, | |
| 67 | .set_enable = tegra_pwm_set_enable, | |
| 68 | }; | |
| 69 | ||
| 70 | static const struct udevice_id tegra_pwm_ids[] = { | |
| 71 | { .compatible = "nvidia,tegra124-pwm" }, | |
| 72 | { .compatible = "nvidia,tegra20-pwm" }, | |
| 73 | { } | |
| 74 | }; | |
| 75 | ||
| 76 | U_BOOT_DRIVER(tegra_pwm) = { | |
| 77 | .name = "tegra_pwm", | |
| 78 | .id = UCLASS_PWM, | |
| 79 | .of_match = tegra_pwm_ids, | |
| 80 | .ops = &tegra_pwm_ops, | |
| 81 | .ofdata_to_platdata = tegra_pwm_ofdata_to_platdata, | |
| 82 | .priv_auto_alloc_size = sizeof(struct tegra_pwm_priv), | |
| 83 | }; |