[J-u-boot.git] / include / configs / at91rm9200ek.h

/*
 * Copyright (C) 2010 Andreas Bießmann <[email protected]>
 *
 * based on previous work by
 *
 * Ulf Samuelsson <[email protected]>
 * Rick Bronson <[email protected]>
 *
 * Configuration settings for the AT91RM9200EK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __AT91RM9200EK_CONFIG_H__
#define __AT91RM9200EK_CONFIG_H__

#include <asm/sizes.h>

/*
 * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
 * AT91C_MAIN_CLOCK is the frequency of PLLA output
 * AT91C_MASTER_CLOCK is the peripherial clock
 * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
 *  set in arch/arm/cpu/arm920t/at91/timer.c)
 * CONFIG_SYS_HZ is the tick rate for timer tc0
 */
#define AT91C_XTAL_CLOCK		18432000
#define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
#define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3 )
#define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
#define CONFIG_SYS_HZ			1000

/* CPU configuration */
#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_AT91RM9200EK
#define CONFIG_CPUAT91
#define USE_920T_MMU

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Memory Configuration
 */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		SZ_32M

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		\
		(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)

/*
 * LowLevel Init
 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
#define CONFIG_SYS_MCKR_VAL	0x00000202

/* sdram */
#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
#define CONFIG_SYS_SDRAM1	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */

/*
 * Hardware drivers
 */
/*
 * Choose a USART for serial console
 * CONFIG_DBGU is DBGU unit on J10
 * CONFIG_USART1 is USART1 on J14
 */
#define CONFIG_AT91RM9200_USART
#define CONFIG_DBGU

#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_BAUDRATE			115200

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_FPGA

/*
 * Network Driver Setting
 */
#define CONFIG_NET_MULTI
#define CONFIG_DRIVER_AT91EMAC
#define CONFIG_SYS_RX_ETH_BUFFER	16
#define CONFIG_RMII
#define CONFIG_MII

/*
 * NOR Flash
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BASE		0x10000000
#define PHYS_FLASH_1			CONFIG_SYS_FLASH_BASE
#define PHYS_FLASH_SIZE			SZ_8M
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * Environment Settings
 */
#define CONFIG_ENV_IS_IN_FLASH

/*
 * after u-boot.bin
 */
#define CONFIG_ENV_ADDR			\
		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE			SZ_64K /* sectors are 64K here */
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		SZ_256K

/*
 * Boot option
 */
#define CONFIG_BOOTDELAY		3

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
#define CONFIG_ENV_OVERWRITE

/*
 * Shell Settings
 */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT		"U-Boot> "
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
					     SZ_4K)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	128

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
					- CONFIG_SYS_GBL_DATA_SIZE)

#define CONFIG_STACKSIZE		SZ_32K	/* regular stack */
#define CONFIG_STACKSIZE_IRQ		SZ_4K	/* Unsure if to big or to small*/
#define CONFIG_STACKSIZE_FIQ		SZ_4K	/* Unsure if to big or to small*/
#endif /* __AT91RM9200EK_CONFIG_H__ */
Commit	Line	Data
cb82a532	1	/*
99fa97e9 AB	2	* Copyright (C) 2010 Andreas Bießmann <[email protected]>
	3	*
	4	* based on previous work by
	5	*
cb82a532 US	6	* Ulf Samuelsson <[email protected]>
	7	* Rick Bronson <[email protected]>
	8	*
	9	* Configuration settings for the AT91RM9200EK board.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
99fa97e9 AB	30	#ifndef __AT91RM9200EK_CONFIG_H__
99fa97e9 AB	31	#define __AT91RM9200EK_CONFIG_H__
cb82a532	32
99fa97e9	33	#include <asm/sizes.h>
425de62d	34
cb82a532	35	/*
99fa97e9 AB	36	* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
	37	* AT91C_MAIN_CLOCK is the frequency of PLLA output
	38	* AT91C_MASTER_CLOCK is the peripherial clock
	39	* CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
	40	* set in arch/arm/cpu/arm920t/at91/timer.c)
	41	* CONFIG_SYS_HZ is the tick rate for timer tc0
cb82a532	42	*/
99fa97e9 AB	43	#define AT91C_XTAL_CLOCK 18432000
	44	#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
	45	#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
	46	#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
	47	#define CONFIG_SYS_HZ 1000
cb82a532	48
99fa97e9 AB	49	/* CPU configuration */
	50	#define CONFIG_ARM920T
	51	#define CONFIG_AT91RM9200
	52	#define CONFIG_AT91RM9200EK
	53	#define CONFIG_CPUAT91
	54	#define USE_920T_MMU
cb82a532	55
99fa97e9 AB	56	#define CONFIG_CMDLINE_TAG
	57	#define CONFIG_SETUP_MEMORY_TAGS
	58	#define CONFIG_INITRD_TAG
	59
	60	/*
	61	* Memory Configuration
	62	*/
	63	#define CONFIG_NR_DRAM_BANKS 1
	64	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	65	#define CONFIG_SYS_SDRAM_SIZE SZ_32M
cb82a532	66
99fa97e9 AB	67	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	68	#define CONFIG_SYS_MEMTEST_END \
	69	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
cb82a532 US	70
	71	/*
	72	* LowLevel Init
	73	*/
	74	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
99fa97e9	75	#define CONFIG_SYS_USE_MAIN_OSCILLATOR
cb82a532	76	/* flash */
cb82a532 US	77	#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
	78	#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
	79
	80	/* clocks */
	81	#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
	82	#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
	83	/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
	84	#define CONFIG_SYS_MCKR_VAL 0x00000202
	85
	86	/* sdram */
	87	#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
	88	#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
	89	#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
	90	#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
	91	#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
99fa97e9 AB	92	#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
99fa97e9 AB	93	#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
cb82a532 US	94	#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
	95	#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
	96	#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
	97	#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	98	#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	99	#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
cb82a532 US	100	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
cb82a532 US	101
cb82a532 US	102	/*
	103	* Hardware drivers
	104	*/
cb82a532	105	/*
99fa97e9 AB	106	* Choose a USART for serial console
	107	* CONFIG_DBGU is DBGU unit on J10
	108	* CONFIG_USART1 is USART1 on J14
cb82a532	109	*/
beebd851	110	#define CONFIG_AT91RM9200_USART
cb82a532	111	#define CONFIG_DBGU
cb82a532 US	112
	113	#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
	114	#define CONFIG_BAUDRATE 115200
	115
	116	/*
	117	* Command line configuration.
	118	*/
	119	#include <config_cmd_default.h>
	120
	121	#define CONFIG_CMD_DHCP
	122	#define CONFIG_CMD_FAT
	123	#define CONFIG_CMD_MII
	124	#define CONFIG_CMD_PING
cb82a532	125	#undef CONFIG_CMD_FPGA
cb82a532 US	126
	127	/*
	128	* Network Driver Setting
	129	*/
99fa97e9 AB	130	#define CONFIG_NET_MULTI
	131	#define CONFIG_DRIVER_AT91EMAC
	132	#define CONFIG_SYS_RX_ETH_BUFFER 16
	133	#define CONFIG_RMII
	134	#define CONFIG_MII
cb82a532 US	135
	136	/*
	137	* NOR Flash
	138	*/
99fa97e9 AB	139	#define CONFIG_FLASH_CFI_DRIVER
	140	#define CONFIG_SYS_FLASH_CFI
	141	#define CONFIG_SYS_FLASH_BASE 0x10000000
	142	#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
	143	#define PHYS_FLASH_SIZE SZ_8M
	144	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	145	#define CONFIG_SYS_MAX_FLASH_SECT 256
cb82a532 US	146	#define CONFIG_SYS_FLASH_PROTECTION
	147
	148	/*
	149	* Environment Settings
	150	*/
99fa97e9	151	#define CONFIG_ENV_IS_IN_FLASH
cb82a532	152
cb82a532 US	153	/*
	154	* after u-boot.bin
	155	*/
	156	#define CONFIG_ENV_ADDR \
	157	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
99fa97e9	158	#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
cb82a532 US	159	/* The following #defines are needed to get flash environment right */
cb82a532 US	160	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
99fa97e9	161	#define CONFIG_SYS_MONITOR_LEN SZ_256K
cb82a532 US	162
	163	/*
	164	* Boot option
	165	*/
	166	#define CONFIG_BOOTDELAY 3
	167
99fa97e9 AB	168	/* default load address */
	169	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
	170	#define CONFIG_ENV_OVERWRITE
cb82a532 US	171
	172	/*
	173	* Shell Settings
	174	*/
99fa97e9 AB	175	#define CONFIG_CMDLINE_EDITING
	176	#define CONFIG_SYS_LONGHELP
	177	#define CONFIG_AUTO_COMPLETE
	178	#define CONFIG_SYS_HUSH_PARSER
cb82a532 US	179	#define CONFIG_SYS_PROMPT "U-Boot> "
	180	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	181	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	182	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	183	/* Print Buffer Size */
	184	#define CONFIG_SYS_PBSIZE \
	185	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	186
cb82a532 US	187	/*
	188	* Size of malloc() pool
	189	*/
99fa97e9 AB	190	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
99fa97e9 AB	191	SZ_4K)
cb82a532 US	192	/* size in bytes reserved for initial data */
	193	#define CONFIG_SYS_GBL_DATA_SIZE 128
	194
99fa97e9 AB	195	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
	196	- CONFIG_SYS_GBL_DATA_SIZE)
	197
	198	#define CONFIG_STACKSIZE SZ_32K /* regular stack */
	199	#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/
	200	#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/
	201	#endif /* __AT91RM9200EK_CONFIG_H__ */