[J-u-boot.git] / drivers / mmc / sdhci.c

/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * [email protected], 27-Jan-01.
 */

#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>

void *aligned_buffer;

static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
	unsigned long timeout;

	/* Wait max 100 ms */
	timeout = 100;
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
		if (timeout == 0) {
			printf("%s: Reset 0x%x never completed.\n",
			       __func__, (int)mask);
			return;
		}
		timeout--;
		udelay(1000);
	}
}

static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
	int i;
	if (cmd->resp_type & MMC_RSP_136) {
		/* CRC is stripped so we need to do some shifting. */
		for (i = 0; i < 4; i++) {
			cmd->response[i] = sdhci_readl(host,
					SDHCI_RESPONSE + (3-i)*4) << 8;
			if (i != 3)
				cmd->response[i] |= sdhci_readb(host,
						SDHCI_RESPONSE + (3-i)*4-1);
		}
	} else {
		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	}
}

static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
	int i;
	char *offs;
	for (i = 0; i < data->blocksize; i += 4) {
		offs = data->dest + i;
		if (data->flags == MMC_DATA_READ)
			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
		else
			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
	}
}

static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
				unsigned int start_addr)
{
	unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDMA
	unsigned char ctrl;
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif

	timeout = 1000000;
	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR) {
			printf("%s: Error detected in status(0x%X)!\n",
			       __func__, stat);
			return -1;
		}
		if (stat & rdy) {
			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
				continue;
			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
			sdhci_transfer_pio(host, data);
			data->dest += data->blocksize;
			if (++block >= data->blocks)
				break;
		}
#ifdef CONFIG_MMC_SDMA
		if (stat & SDHCI_INT_DMA_END) {
			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		}
#endif
		if (timeout-- > 0)
			udelay(10);
		else {
			printf("%s: Transfer data timeout\n", __func__);
			return -1;
		}
	} while (!(stat & SDHCI_INT_DATA_END));
	return 0;
}

/*
 * No command will be sent by driver if card is busy, so driver must wait
 * for card ready state.
 * Every time when card is busy after timeout then (last) timeout value will be
 * increased twice but only if it doesn't exceed global defined maximum.
 * Each function call will use last timeout value. Max timeout can be redefined
 * in board config file.
 */
#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
#define CONFIG_SDHCI_CMD_MAX_TIMEOUT		3200
#endif
#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100

int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
		       struct mmc_data *data)
{
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
	unsigned int stat = 0;
	int ret = 0;
	int trans_bytes = 0, is_aligned = 1;
	u32 mask, flags, mode;
	unsigned int time = 0, start_addr = 0;
	unsigned int retry = 10000;
	int mmc_dev = mmc->block_dev.dev;

	/* Timeout unit - ms */
	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;

	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		mask &= ~SDHCI_DATA_INHIBIT;

	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
		if (time >= cmd_timeout) {
			printf("%s: MMC: %d busy ", __func__, mmc_dev);
			if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
				cmd_timeout += cmd_timeout;
				printf("timeout increasing to: %u ms.\n",
				       cmd_timeout);
			} else {
				puts("timeout.\n");
				return COMM_ERR;
			}
		}
		time++;
		udelay(1000);
	}

	mask = SDHCI_INT_RESPONSE;
	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->resp_type & MMC_RSP_BUSY) {
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
		mask |= SDHCI_INT_DATA_END;
	} else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
	if (data)
		flags |= SDHCI_CMD_DATA;

	/* Set Transfer mode regarding to data flag */
	if (data != 0) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
		mode = SDHCI_TRNS_BLK_CNT_EN;
		trans_bytes = data->blocks * data->blocksize;
		if (data->blocks > 1)
			mode |= SDHCI_TRNS_MULTI;

		if (data->flags == MMC_DATA_READ)
			mode |= SDHCI_TRNS_READ;

#ifdef CONFIG_MMC_SDMA
		if (data->flags == MMC_DATA_READ)
			start_addr = (unsigned int)data->dest;
		else
			start_addr = (unsigned int)data->src;
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				(start_addr & 0x7) != 0x0) {
			is_aligned = 0;
			start_addr = (unsigned int)aligned_buffer;
			if (data->flags != MMC_DATA_READ)
				memcpy(aligned_buffer, data->src, trans_bytes);
		}

		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		mode |= SDHCI_TRNS_DMA;
#endif
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
				data->blocksize),
				SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	}

	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDMA
	flush_cache(start_addr, trans_bytes);
#endif
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR)
			break;
		if (--retry == 0)
			break;
	} while ((stat & mask) != mask);

	if (retry == 0) {
		if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
			return 0;
		else {
			printf("%s: Timeout for status update!\n", __func__);
			return TIMEOUT;
		}
	}

	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
		sdhci_cmd_done(host, cmd);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
	} else
		ret = -1;

	if (!ret && data)
		ret = sdhci_transfer_data(host, data, start_addr);

	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
		udelay(1000);

	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	if (!ret) {
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				!is_aligned && (data->flags == MMC_DATA_READ))
			memcpy(data->dest, aligned_buffer, trans_bytes);
		return 0;
	}

	sdhci_reset(host, SDHCI_RESET_CMD);
	sdhci_reset(host, SDHCI_RESET_DATA);
	if (stat & SDHCI_INT_TIMEOUT)
		return TIMEOUT;
	else
		return COMM_ERR;
}

static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
	unsigned int div, clk, timeout;

	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return 0;

	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		/* Version 3.00 divisors must be a multiple of 2. */
		if (mmc->f_max <= clock)
			div = 1;
		else {
			for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
				if ((mmc->f_max / div) <= clock)
					break;
			}
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
			if ((mmc->f_max / div) <= clock)
				break;
		}
	}
	div >>= 1;

	if (host->set_clock)
		host->set_clock(host->index, div);

	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			printf("%s: Internal clock never stabilised.\n",
			       __func__);
			return -1;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	return 0;
}

static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
	u8 pwr = 0;

	if (power != (unsigned short)-1) {
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		}
	}

	if (pwr == 0) {
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
		return;
	}

	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

	pwr |= SDHCI_POWER_ON;

	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}

void sdhci_set_ios(struct mmc *mmc)
{
	u32 ctrl;
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;

	if (host->set_control_reg)
		host->set_control_reg(host);

	if (mmc->clock != host->clock)
		sdhci_set_clock(mmc, mmc->clock);

	/* Set bus width */
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (mmc->bus_width == 8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (mmc->bus_width == 4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}

	if (mmc->clock > 26000000)
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
		ctrl &= ~SDHCI_CTRL_HISPD;

	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

int sdhci_init(struct mmc *mmc)
{
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;

	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
		aligned_buffer = memalign(8, 512*1024);
		if (!aligned_buffer) {
			printf("%s: Aligned buffer alloc failed!!!\n",
			       __func__);
			return -1;
		}
	}

	sdhci_set_power(host, fls(mmc->voltages) - 1);

	if (host->quirks & SDHCI_QUIRK_NO_CD) {
		unsigned int status;

		sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
			SDHCI_HOST_CONTROL);

		status = sdhci_readl(host, SDHCI_PRESENT_STATE);
		while ((!(status & SDHCI_CARD_PRESENT)) ||
		    (!(status & SDHCI_CARD_STATE_STABLE)) ||
		    (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
			status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	}

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}


static const struct mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
	.init		= sdhci_init,
};

int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
	struct mmc *mmc;
	unsigned int caps;

	mmc = malloc(sizeof(struct mmc));
	if (!mmc) {
		printf("%s: mmc malloc fail!\n", __func__);
		return -1;
	}

	mmc->priv = host;
	host->mmc = mmc;

	sprintf(mmc->name, "%s", host->name);
	mmc->ops = &sdhci_ops;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
	if (!(caps & SDHCI_CAN_DO_SDMA)) {
		printf("%s: Your controller doesn't support SDMA!!\n",
		       __func__);
		return -1;
	}
#endif

	if (max_clk)
		mmc->f_max = max_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
				>> SDHCI_CLOCK_BASE_SHIFT;
		else
			mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
				>> SDHCI_CLOCK_BASE_SHIFT;
		mmc->f_max *= 1000000;
	}
	if (mmc->f_max == 0) {
		printf("%s: Hardware doesn't specify base clock frequency\n",
		       __func__);
		return -1;
	}
	if (min_clk)
		mmc->f_min = min_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
		else
			mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
	}

	mmc->voltages = 0;
	if (caps & SDHCI_CAN_VDD_330)
		mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
	if (caps & SDHCI_CAN_VDD_300)
		mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & SDHCI_CAN_VDD_180)
		mmc->voltages |= MMC_VDD_165_195;

	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
		mmc->voltages |= host->voltages;

	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		if (caps & SDHCI_CAN_DO_8BIT)
			mmc->host_caps |= MMC_MODE_8BIT;
	}
	if (host->host_caps)
		mmc->host_caps |= host->host_caps;

	sdhci_reset(host, SDHCI_RESET_ALL);
	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
af62a557 LW	1	/*
	2	* Copyright 2011, Marvell Semiconductor Inc.
	3	* Lei Wen <[email protected]>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
af62a557 LW	6	*
	7	* Back ported to the 8xx platform (from the 8260 platform) by
	8	* [email protected], 27-Jan-01.
	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13	#include <mmc.h>
	14	#include <sdhci.h>
	15
	16	void *aligned_buffer;
	17
	18	static void sdhci_reset(struct sdhci_host *host, u8 mask)
	19	{
	20	unsigned long timeout;
	21
	22	/* Wait max 100 ms */
	23	timeout = 100;
	24	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	25	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
	26	if (timeout == 0) {
30e6d979 DR	27	printf("%s: Reset 0x%x never completed.\n",
30e6d979 DR	28	__func__, (int)mask);
af62a557 LW	29	return;
	30	}
	31	timeout--;
	32	udelay(1000);
	33	}
	34	}
	35
	36	static void sdhci_cmd_done(struct sdhci_host host, struct mmc_cmd cmd)
	37	{
	38	int i;
	39	if (cmd->resp_type & MMC_RSP_136) {
	40	/* CRC is stripped so we need to do some shifting. */
	41	for (i = 0; i < 4; i++) {
	42	cmd->response[i] = sdhci_readl(host,
	43	SDHCI_RESPONSE + (3-i)*4) << 8;
	44	if (i != 3)
	45	cmd->response[i] \|= sdhci_readb(host,
	46	SDHCI_RESPONSE + (3-i)*4-1);
	47	}
	48	} else {
	49	cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	50	}
	51	}
	52
	53	static void sdhci_transfer_pio(struct sdhci_host host, struct mmc_data data)
	54	{
	55	int i;
	56	char *offs;
	57	for (i = 0; i < data->blocksize; i += 4) {
	58	offs = data->dest + i;
	59	if (data->flags == MMC_DATA_READ)
	60	(u32 )offs = sdhci_readl(host, SDHCI_BUFFER);
	61	else
	62	sdhci_writel(host, (u32 )offs, SDHCI_BUFFER);
	63	}
	64	}
	65
	66	static int sdhci_transfer_data(struct sdhci_host host, struct mmc_data data,
	67	unsigned int start_addr)
	68	{
a004abde	69	unsigned int stat, rdy, mask, timeout, block = 0;
804c7f42 JC	70	#ifdef CONFIG_MMC_SDMA
804c7f42 JC	71	unsigned char ctrl;
2c011847	72	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
804c7f42	73	ctrl &= ~SDHCI_CTRL_DMA_MASK;
2c011847	74	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
804c7f42	75	#endif
af62a557	76
5d48e422	77	timeout = 1000000;
af62a557 LW	78	rdy = SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_AVAIL;
	79	mask = SDHCI_DATA_AVAILABLE \| SDHCI_SPACE_AVAILABLE;
	80	do {
	81	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	82	if (stat & SDHCI_INT_ERROR) {
30e6d979 DR	83	printf("%s: Error detected in status(0x%X)!\n",
30e6d979 DR	84	__func__, stat);
af62a557 LW	85	return -1;
	86	}
	87	if (stat & rdy) {
	88	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
	89	continue;
	90	sdhci_writel(host, rdy, SDHCI_INT_STATUS);
	91	sdhci_transfer_pio(host, data);
	92	data->dest += data->blocksize;
	93	if (++block >= data->blocks)
	94	break;
	95	}
	96	#ifdef CONFIG_MMC_SDMA
	97	if (stat & SDHCI_INT_DMA_END) {
	98	sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
3e81c772	99	start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
af62a557 LW	100	start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
	101	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	102	}
	103	#endif
a004abde LW	104	if (timeout-- > 0)
	105	udelay(10);
	106	else {
30e6d979	107	printf("%s: Transfer data timeout\n", __func__);
a004abde LW	108	return -1;
a004abde LW	109	}
af62a557 LW	110	} while (!(stat & SDHCI_INT_DATA_END));
	111	return 0;
	112	}
	113
56b34bc6 PM	114	/*
	115	* No command will be sent by driver if card is busy, so driver must wait
	116	* for card ready state.
	117	* Every time when card is busy after timeout then (last) timeout value will be
	118	* increased twice but only if it doesn't exceed global defined maximum.
	119	* Each function call will use last timeout value. Max timeout can be redefined
	120	* in board config file.
	121	*/
	122	#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
	123	#define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
	124	#endif
	125	#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
	126
af62a557 LW	127	int sdhci_send_command(struct mmc mmc, struct mmc_cmd cmd,
	128	struct mmc_data *data)
	129	{
	130	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	131	unsigned int stat = 0;
	132	int ret = 0;
	133	int trans_bytes = 0, is_aligned = 1;
	134	u32 mask, flags, mode;
56b34bc6	135	unsigned int time = 0, start_addr = 0;
3a638320	136	unsigned int retry = 10000;
56b34bc6	137	int mmc_dev = mmc->block_dev.dev;
af62a557	138
56b34bc6 PM	139	/* Timeout unit - ms */
56b34bc6 PM	140	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
af62a557 LW	141
	142	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	143	mask = SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT;
	144
	145	/* We shouldn't wait for data inihibit for stop commands, even
	146	though they might use busy signaling */
	147	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	148	mask &= ~SDHCI_DATA_INHIBIT;
	149
	150	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
56b34bc6	151	if (time >= cmd_timeout) {
30e6d979	152	printf("%s: MMC: %d busy ", __func__, mmc_dev);
56b34bc6 PM	153	if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
	154	cmd_timeout += cmd_timeout;
	155	printf("timeout increasing to: %u ms.\n",
	156	cmd_timeout);
	157	} else {
	158	puts("timeout.\n");
	159	return COMM_ERR;
	160	}
af62a557	161	}
56b34bc6	162	time++;
af62a557 LW	163	udelay(1000);
	164	}
	165
	166	mask = SDHCI_INT_RESPONSE;
	167	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	168	flags = SDHCI_CMD_RESP_NONE;
	169	else if (cmd->resp_type & MMC_RSP_136)
	170	flags = SDHCI_CMD_RESP_LONG;
	171	else if (cmd->resp_type & MMC_RSP_BUSY) {
	172	flags = SDHCI_CMD_RESP_SHORT_BUSY;
	173	mask \|= SDHCI_INT_DATA_END;
	174	} else
	175	flags = SDHCI_CMD_RESP_SHORT;
	176
	177	if (cmd->resp_type & MMC_RSP_CRC)
	178	flags \|= SDHCI_CMD_CRC;
	179	if (cmd->resp_type & MMC_RSP_OPCODE)
	180	flags \|= SDHCI_CMD_INDEX;
	181	if (data)
	182	flags \|= SDHCI_CMD_DATA;
	183
30e6d979	184	/* Set Transfer mode regarding to data flag */
af62a557 LW	185	if (data != 0) {
	186	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	187	mode = SDHCI_TRNS_BLK_CNT_EN;
	188	trans_bytes = data->blocks * data->blocksize;
	189	if (data->blocks > 1)
	190	mode \|= SDHCI_TRNS_MULTI;
	191
	192	if (data->flags == MMC_DATA_READ)
	193	mode \|= SDHCI_TRNS_READ;
	194
	195	#ifdef CONFIG_MMC_SDMA
	196	if (data->flags == MMC_DATA_READ)
	197	start_addr = (unsigned int)data->dest;
	198	else
	199	start_addr = (unsigned int)data->src;
	200	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	201	(start_addr & 0x7) != 0x0) {
	202	is_aligned = 0;
	203	start_addr = (unsigned int)aligned_buffer;
	204	if (data->flags != MMC_DATA_READ)
	205	memcpy(aligned_buffer, data->src, trans_bytes);
	206	}
	207
	208	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	209	mode \|= SDHCI_TRNS_DMA;
	210	#endif
	211	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
	212	data->blocksize),
	213	SDHCI_BLOCK_SIZE);
	214	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	215	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	216	}
	217
	218	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
	219	#ifdef CONFIG_MMC_SDMA
2c2ec4c9	220	flush_cache(start_addr, trans_bytes);
af62a557 LW	221	#endif
	222	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	223	do {
	224	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	225	if (stat & SDHCI_INT_ERROR)
	226	break;
3a638320 JC	227	if (--retry == 0)
3a638320 JC	228	break;
af62a557 LW	229	} while ((stat & mask) != mask);
af62a557 LW	230
3a638320 JC	231	if (retry == 0) {
	232	if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
	233	return 0;
	234	else {
30e6d979	235	printf("%s: Timeout for status update!\n", __func__);
3a638320 JC	236	return TIMEOUT;
	237	}
	238	}
	239
af62a557 LW	240	if ((stat & (SDHCI_INT_ERROR \| mask)) == mask) {
	241	sdhci_cmd_done(host, cmd);
	242	sdhci_writel(host, mask, SDHCI_INT_STATUS);
	243	} else
	244	ret = -1;
	245
	246	if (!ret && data)
	247	ret = sdhci_transfer_data(host, data, start_addr);
	248
13243f2e TB	249	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
	250	udelay(1000);
	251
af62a557 LW	252	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	253	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	254	if (!ret) {
	255	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	256	!is_aligned && (data->flags == MMC_DATA_READ))
	257	memcpy(data->dest, aligned_buffer, trans_bytes);
	258	return 0;
	259	}
	260
	261	sdhci_reset(host, SDHCI_RESET_CMD);
	262	sdhci_reset(host, SDHCI_RESET_DATA);
	263	if (stat & SDHCI_INT_TIMEOUT)
	264	return TIMEOUT;
	265	else
	266	return COMM_ERR;
	267	}
	268
	269	static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
	270	{
	271	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	272	unsigned int div, clk, timeout;
	273
	274	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
	275
	276	if (clock == 0)
	277	return 0;
	278
113e5dfc	279	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
af62a557 LW	280	/* Version 3.00 divisors must be a multiple of 2. */
	281	if (mmc->f_max <= clock)
	282	div = 1;
	283	else {
	284	for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
	285	if ((mmc->f_max / div) <= clock)
	286	break;
	287	}
	288	}
	289	} else {
	290	/* Version 2.00 divisors must be a power of 2. */
	291	for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
	292	if ((mmc->f_max / div) <= clock)
	293	break;
	294	}
	295	}
	296	div >>= 1;
	297
b09ed6e4 JC	298	if (host->set_clock)
	299	host->set_clock(host->index, div);
	300
af62a557 LW	301	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	302	clk \|= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
	303	<< SDHCI_DIVIDER_HI_SHIFT;
	304	clk \|= SDHCI_CLOCK_INT_EN;
	305	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	306
	307	/* Wait max 20 ms */
	308	timeout = 20;
	309	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	310	& SDHCI_CLOCK_INT_STABLE)) {
	311	if (timeout == 0) {
30e6d979 DR	312	printf("%s: Internal clock never stabilised.\n",
30e6d979 DR	313	__func__);
af62a557 LW	314	return -1;
	315	}
	316	timeout--;
	317	udelay(1000);
	318	}
	319
	320	clk \|= SDHCI_CLOCK_CARD_EN;
	321	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	322	return 0;
	323	}
	324
	325	static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
	326	{
	327	u8 pwr = 0;
	328
	329	if (power != (unsigned short)-1) {
	330	switch (1 << power) {
	331	case MMC_VDD_165_195:
	332	pwr = SDHCI_POWER_180;
	333	break;
	334	case MMC_VDD_29_30:
	335	case MMC_VDD_30_31:
	336	pwr = SDHCI_POWER_300;
	337	break;
	338	case MMC_VDD_32_33:
	339	case MMC_VDD_33_34:
	340	pwr = SDHCI_POWER_330;
	341	break;
	342	}
	343	}
	344
	345	if (pwr == 0) {
	346	sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
	347	return;
	348	}
	349
688c2d14 MC	350	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
	351	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	352
af62a557 LW	353	pwr \|= SDHCI_POWER_ON;
	354
	355	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	356	}
	357
	358	void sdhci_set_ios(struct mmc *mmc)
	359	{
	360	u32 ctrl;
	361	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	362
236bfecf JC	363	if (host->set_control_reg)
	364	host->set_control_reg(host);
	365
af62a557 LW	366	if (mmc->clock != host->clock)
	367	sdhci_set_clock(mmc, mmc->clock);
	368
	369	/* Set bus width */
	370	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	371	if (mmc->bus_width == 8) {
	372	ctrl &= ~SDHCI_CTRL_4BITBUS;
113e5dfc JC	373	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
113e5dfc JC	374	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	375	ctrl \|= SDHCI_CTRL_8BITBUS;
af62a557 LW	376	} else {
113e5dfc	377	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
af62a557 LW	378	ctrl &= ~SDHCI_CTRL_8BITBUS;
	379	if (mmc->bus_width == 4)
	380	ctrl \|= SDHCI_CTRL_4BITBUS;
	381	else
	382	ctrl &= ~SDHCI_CTRL_4BITBUS;
	383	}
	384
	385	if (mmc->clock > 26000000)
	386	ctrl \|= SDHCI_CTRL_HISPD;
	387	else
	388	ctrl &= ~SDHCI_CTRL_HISPD;
	389
236bfecf JC	390	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
	391	ctrl &= ~SDHCI_CTRL_HISPD;
	392
af62a557 LW	393	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
	394	}
	395
	396	int sdhci_init(struct mmc *mmc)
	397	{
	398	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	399
	400	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
	401	aligned_buffer = memalign(8, 512*1024);
	402	if (!aligned_buffer) {
30e6d979 DR	403	printf("%s: Aligned buffer alloc failed!!!\n",
30e6d979 DR	404	__func__);
af62a557 LW	405	return -1;
	406	}
	407	}
	408
470dcc75 JH	409	sdhci_set_power(host, fls(mmc->voltages) - 1);
	410
	411	if (host->quirks & SDHCI_QUIRK_NO_CD) {
	412	unsigned int status;
	413
	414	sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS \| SDHCI_CTRL_CD_TEST,
	415	SDHCI_HOST_CONTROL);
	416
	417	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	418	while ((!(status & SDHCI_CARD_PRESENT)) \|\|
	419	(!(status & SDHCI_CARD_STATE_STABLE)) \|\|
	420	(!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
	421	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	422	}
	423
ce0c1bc1	424	/* Enable only interrupts served by the SD controller */
30e6d979 DR	425	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
30e6d979 DR	426	SDHCI_INT_ENABLE);
ce0c1bc1 ŁM	427	/* Mask all sdhci interrupt sources */
ce0c1bc1 ŁM	428	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557	429
af62a557 LW	430	return 0;
	431	}
	432
ab769f22 PA	433
	434	static const struct mmc_ops sdhci_ops = {
	435	.send_cmd = sdhci_send_command,
	436	.set_ios = sdhci_set_ios,
	437	.init = sdhci_init,
	438	};
	439
af62a557 LW	440	int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
	441	{
	442	struct mmc *mmc;
	443	unsigned int caps;
	444
	445	mmc = malloc(sizeof(struct mmc));
	446	if (!mmc) {
30e6d979	447	printf("%s: mmc malloc fail!\n", __func__);
af62a557 LW	448	return -1;
	449	}
	450
	451	mmc->priv = host;
6cf1b17c	452	host->mmc = mmc;
af62a557 LW	453
af62a557 LW	454	sprintf(mmc->name, "%s", host->name);
ab769f22	455	mmc->ops = &sdhci_ops;
af62a557 LW	456
	457	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	458	#ifdef CONFIG_MMC_SDMA
	459	if (!(caps & SDHCI_CAN_DO_SDMA)) {
30e6d979 DR	460	printf("%s: Your controller doesn't support SDMA!!\n",
30e6d979 DR	461	__func__);
af62a557 LW	462	return -1;
	463	}
	464	#endif
	465
	466	if (max_clk)
	467	mmc->f_max = max_clk;
	468	else {
113e5dfc	469	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
af62a557 LW	470	mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
	471	>> SDHCI_CLOCK_BASE_SHIFT;
	472	else
	473	mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
	474	>> SDHCI_CLOCK_BASE_SHIFT;
	475	mmc->f_max *= 1000000;
	476	}
	477	if (mmc->f_max == 0) {
30e6d979 DR	478	printf("%s: Hardware doesn't specify base clock frequency\n",
30e6d979 DR	479	__func__);
af62a557 LW	480	return -1;
	481	}
	482	if (min_clk)
	483	mmc->f_min = min_clk;
	484	else {
113e5dfc	485	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
af62a557 LW	486	mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
	487	else
	488	mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
	489	}
	490
	491	mmc->voltages = 0;
	492	if (caps & SDHCI_CAN_VDD_330)
	493	mmc->voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
	494	if (caps & SDHCI_CAN_VDD_300)
	495	mmc->voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
	496	if (caps & SDHCI_CAN_VDD_180)
	497	mmc->voltages \|= MMC_VDD_165_195;
236bfecf JC	498
	499	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
	500	mmc->voltages \|= host->voltages;
	501
af62a557	502	mmc->host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;
113e5dfc	503	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
1695b29a JT	504	if (caps & SDHCI_CAN_DO_8BIT)
	505	mmc->host_caps \|= MMC_MODE_8BIT;
	506	}
236bfecf JC	507	if (host->host_caps)
236bfecf JC	508	mmc->host_caps \|= host->host_caps;
af62a557 LW	509
	510	sdhci_reset(host, SDHCI_RESET_ALL);
	511	mmc_register(mmc);
	512
	513	return 0;
	514	}