projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 49249e13 PA |
2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
| 2703e640 | 4 | * Copyright 2020 NXP |
| 49249e13 PA |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * P010 RDB board configuration file | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 1af3c7f4 SG |
14 | #include <linux/stringify.h> |
| 15 | ||
| 74fa22ed | 16 | #include <asm/config_mpc85xx.h> |
| 49249e13 PA |
17 | |
| 18 | #ifdef CONFIG_SDCARD | |
| c9e1f588 YZ |
19 | #define CONFIG_SPL_FLUSH_IMAGE |
| 20 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 YZ |
21 | #define CONFIG_SPL_PAD_TO 0x18000 |
| 22 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
| 23 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) | |
| 24 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) | |
| 25 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
| 26 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) | |
| 27 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c9e1f588 YZ |
28 | #ifdef CONFIG_SPL_BUILD |
| 29 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 30 | #endif | |
| 49249e13 PA |
31 | #endif |
| 32 | ||
| 33 | #ifdef CONFIG_SPIFLASH | |
| bef18454 | 34 | #ifdef CONFIG_NXP_ESBC |
| 49249e13 | 35 | #define CONFIG_RAMBOOT_SPIFLASH |
| 84e0fb40 | 36 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| c9e1f588 | 37 | #else |
| c9e1f588 YZ |
38 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 39 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 40 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 YZ |
41 | #define CONFIG_SPL_PAD_TO 0x18000 |
| 42 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
| 43 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) | |
| 44 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) | |
| 45 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
| 46 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) | |
| 47 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c9e1f588 YZ |
48 | #ifdef CONFIG_SPL_BUILD |
| 49 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 50 | #endif | |
| 51 | #endif | |
| 49249e13 PA |
52 | #endif |
| 53 | ||
| 88718be3 | 54 | #ifdef CONFIG_MTD_RAW_NAND |
| bef18454 | 55 | #ifdef CONFIG_NXP_ESBC |
| 0fa934d2 | 56 | #define CONFIG_SPL_INIT_MINIMAL |
| 0fa934d2 PK |
57 | #define CONFIG_SPL_FLUSH_IMAGE |
| 58 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 59 | ||
| 0fa934d2 PK |
60 | #define CONFIG_SPL_MAX_SIZE 8192 |
| 61 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 | |
| 62 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
| e222b1f3 | 63 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
| 0fa934d2 PK |
64 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
| 65 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| c9e1f588 | 66 | #else |
| c9e1f588 | 67 | #ifdef CONFIG_TPL_BUILD |
| c9e1f588 | 68 | #define CONFIG_SPL_FLUSH_IMAGE |
| c9e1f588 | 69 | #define CONFIG_SPL_NAND_INIT |
| c9e1f588 YZ |
70 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 71 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
| c9e1f588 YZ |
72 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 73 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) | |
| 74 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) | |
| 75 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
| c9e1f588 YZ |
76 | #elif defined(CONFIG_SPL_BUILD) |
| 77 | #define CONFIG_SPL_INIT_MINIMAL | |
| c9e1f588 YZ |
78 | #define CONFIG_SPL_NAND_MINIMAL |
| 79 | #define CONFIG_SPL_FLUSH_IMAGE | |
| c9e1f588 YZ |
80 | #define CONFIG_SPL_MAX_SIZE 8192 |
| 81 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
| 82 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 | |
| 83 | #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 | |
| ab37df9d T |
84 | #else |
| 85 | #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR | |
| 86 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 87 | #endif | |
| c9e1f588 YZ |
88 | #endif |
| 89 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 90 | #define CONFIG_TPL_PAD_TO 0x20000 | |
| 91 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 | 92 | #endif |
| d793e5a8 | 93 | #endif |
| 2f439e80 RG |
94 | |
| 95 | #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ | |
| 96 | #define CONFIG_RAMBOOT_NAND | |
| e222b1f3 | 97 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| 2f439e80 RG |
98 | #endif |
| 99 | ||
| 49249e13 PA |
100 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 101 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 102 | #endif | |
| 103 | ||
| 49249e13 | 104 | /* High Level Configuration Options */ |
| 49249e13 | 105 | |
| 49249e13 | 106 | #if defined(CONFIG_PCI) |
| b38eaec5 RD |
107 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| 108 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
| 49249e13 | 109 | |
| 49249e13 PA |
110 | /* |
| 111 | * PCI Windows | |
| 112 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 113 | */ | |
| 114 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 49249e13 PA |
115 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 116 | #ifdef CONFIG_PHYS_64BIT | |
| 49249e13 PA |
117 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 118 | #else | |
| 49249e13 PA |
119 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
| 120 | #endif | |
| 49249e13 | 121 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
| 49249e13 PA |
122 | #ifdef CONFIG_PHYS_64BIT |
| 123 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
| 124 | #else | |
| 125 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
| 126 | #endif | |
| 127 | ||
| 128 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 9de7c76b HZ |
129 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 130 | #ifdef CONFIG_PHYS_64BIT | |
| 131 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 132 | #else | |
| 133 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 134 | #endif | |
| 135 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
| 136 | #ifdef CONFIG_PHYS_64BIT | |
| 137 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 138 | #else | |
| 139 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
| 140 | #endif | |
| 141 | ||
| 49249e13 | 142 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 49249e13 PA |
143 | #endif |
| 144 | ||
| 49249e13 PA |
145 | #define CONFIG_HWCONFIG |
| 146 | /* | |
| 147 | * These can be toggled for performance analysis, otherwise use default. | |
| 148 | */ | |
| 149 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 49249e13 | 150 | |
| 49249e13 PA |
151 | |
| 152 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 153 | ||
| 49249e13 | 154 | /* DDR Setup */ |
| 1ba62f10 | 155 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 49249e13 PA |
156 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
| 157 | #define SPD_EEPROM_ADDRESS 0x52 | |
| 158 | ||
| 159 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 160 | ||
| 161 | #ifndef __ASSEMBLY__ | |
| 162 | extern unsigned long get_sdram_size(void); | |
| 163 | #endif | |
| 164 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ | |
| 165 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 166 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 167 | ||
| 49249e13 PA |
168 | /* DDR3 Controller Settings */ |
| 169 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
| 170 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
| 171 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 172 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 173 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 174 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 175 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 49249e13 PA |
176 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| 177 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 178 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 179 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| e512c50b SL |
180 | #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ |
| 181 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 | |
| 49249e13 PA |
182 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 |
| 183 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
| 184 | ||
| e512c50b SL |
185 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 |
| 186 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 | |
| 187 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 | |
| 49249e13 PA |
188 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF |
| 189 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
| e512c50b SL |
190 | #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 |
| 191 | #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 | |
| 49249e13 | 192 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 |
| e512c50b | 193 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 |
| 49249e13 PA |
194 | |
| 195 | /* settings for DDR3 at 667MT/s */ | |
| 196 | #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 | |
| 197 | #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 | |
| 198 | #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 | |
| 199 | #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD | |
| 200 | #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 | |
| 201 | #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 | |
| 202 | #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 | |
| 203 | #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 | |
| 204 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 | |
| 205 | ||
| 206 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
| 207 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 208 | ||
| d793e5a8 | 209 | /* Don't relocate CCSRBAR while in NAND_SPL */ |
| 0fa934d2 | 210 | #ifdef CONFIG_SPL_BUILD |
| d793e5a8 DD |
211 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| 212 | #endif | |
| 213 | ||
| 49249e13 PA |
214 | /* |
| 215 | * Memory map | |
| 216 | * | |
| 217 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheable | |
| 218 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable | |
| 219 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
| 220 | * | |
| 221 | * Localbus non-cacheable | |
| 222 | * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable | |
| 223 | * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable | |
| 224 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 225 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 226 | */ | |
| 227 | ||
| 49249e13 PA |
228 | /* |
| 229 | * IFC Definitions | |
| 230 | */ | |
| 231 | /* NOR Flash on IFC */ | |
| 0fa934d2 | 232 | |
| 49249e13 PA |
233 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
| 234 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ | |
| 235 | ||
| 236 | #ifdef CONFIG_PHYS_64BIT | |
| 237 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 238 | #else | |
| 239 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 240 | #endif | |
| 241 | ||
| 242 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 243 | CSPR_PORT_SIZE_16 | \ | |
| 244 | CSPR_MSEL_NOR | \ | |
| 245 | CSPR_V) | |
| 246 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) | |
| 247 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) | |
| 248 | /* NOR Flash Timing Params */ | |
| 249 | #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ | |
| 250 | FTIM0_NOR_TEADC(0x5) | \ | |
| 251 | FTIM0_NOR_TEAHC(0x5) | |
| 252 | #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ | |
| 253 | FTIM1_NOR_TRAD_NOR(0x0f) | |
| 254 | #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ | |
| 255 | FTIM2_NOR_TCH(0x4) | \ | |
| 256 | FTIM2_NOR_TWP(0x1c) | |
| 257 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 258 | ||
| 259 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 260 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 261 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 49249e13 PA |
262 | |
| 263 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 264 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 265 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 266 | ||
| 267 | /* CFI for NOR Flash */ | |
| 49249e13 | 268 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 49249e13 PA |
269 | |
| 270 | /* NAND Flash on IFC */ | |
| 271 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 272 | #ifdef CONFIG_PHYS_64BIT | |
| 273 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
| 274 | #else | |
| 275 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 276 | #endif | |
| 277 | ||
| ac688078 | 278 | #define CONFIG_MTD_PARTITION |
| ac688078 | 279 | |
| 49249e13 PA |
280 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 281 | | CSPR_PORT_SIZE_8 \ | |
| 282 | | CSPR_MSEL_NAND \ | |
| 283 | | CSPR_V) | |
| 284 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| e512c50b | 285 | |
| 7601686c | 286 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 49249e13 PA |
287 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 288 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 289 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 290 | | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ | |
| 291 | | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | |
| 292 | | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | |
| 293 | | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ | |
| e512c50b | 294 | |
| 7601686c | 295 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
296 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 297 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 298 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 299 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 300 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
| 301 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
| 302 | | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ | |
| e512c50b | 303 | #endif |
| 49249e13 | 304 | |
| d793e5a8 DD |
305 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 306 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| d793e5a8 | 307 | |
| 7601686c | 308 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 49249e13 PA |
309 | /* NAND Flash Timing Params */ |
| 310 | #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ | |
| 311 | FTIM0_NAND_TWP(0x0C) | \ | |
| 312 | FTIM0_NAND_TWCHT(0x04) | \ | |
| 313 | FTIM0_NAND_TWH(0x05) | |
| 314 | #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ | |
| 315 | FTIM1_NAND_TWBE(0x1d) | \ | |
| 316 | FTIM1_NAND_TRR(0x07) | \ | |
| 317 | FTIM1_NAND_TRP(0x0c) | |
| 318 | #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ | |
| 319 | FTIM2_NAND_TREH(0x05) | \ | |
| 320 | FTIM2_NAND_TWHRE(0x0f) | |
| 321 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
| 322 | ||
| 7601686c | 323 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
324 | /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ |
| 325 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 326 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ | |
| 327 | FTIM0_NAND_TWP(0x18) | \ | |
| 328 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 329 | FTIM0_NAND_TWH(0x0a)) | |
| 330 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ | |
| 331 | FTIM1_NAND_TWBE(0x39) | \ | |
| 332 | FTIM1_NAND_TRR(0x0e) | \ | |
| 333 | FTIM1_NAND_TRP(0x18)) | |
| 334 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 335 | FTIM2_NAND_TREH(0x0a) | \ | |
| 336 | FTIM2_NAND_TWHRE(0x1e)) | |
| 337 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 338 | #endif | |
| 339 | ||
| 49249e13 PA |
340 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 341 | ||
| 342 | /* Set up IFC registers for boot location NOR/NAND */ | |
| 88718be3 | 343 | #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) |
| d793e5a8 DD |
344 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 345 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 346 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 347 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 348 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 349 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 350 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 351 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
| 352 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 353 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 354 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 355 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 356 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 357 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 358 | #else | |
| 49249e13 PA |
359 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 360 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 361 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 362 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 363 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 364 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 365 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 366 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 367 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 368 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 369 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 370 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 371 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 372 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| d793e5a8 DD |
373 | #endif |
| 374 | ||
| 49249e13 PA |
375 | /* CPLD on IFC */ |
| 376 | #define CONFIG_SYS_CPLD_BASE 0xffb00000 | |
| 377 | ||
| 378 | #ifdef CONFIG_PHYS_64BIT | |
| 379 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull | |
| 380 | #else | |
| 381 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
| 382 | #endif | |
| 383 | ||
| 384 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
| 385 | | CSPR_PORT_SIZE_8 \ | |
| 386 | | CSPR_MSEL_GPCM \ | |
| 387 | | CSPR_V) | |
| 388 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
| 389 | #define CONFIG_SYS_CSOR3 0x0 | |
| 390 | /* CPLD Timing parameters for IFC CS3 */ | |
| 391 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 392 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 393 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 394 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 395 | FTIM1_GPCM_TRAD(0x1f)) | |
| 396 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 397 | FTIM2_GPCM_TCH(0x8) | \ |
| 49249e13 PA |
398 | FTIM2_GPCM_TWP(0x1f)) |
| 399 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 49249e13 | 400 | |
| 76c9aaf5 AB |
401 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ |
| 402 | defined(CONFIG_RAMBOOT_NAND) | |
| 49249e13 | 403 | #define CONFIG_SYS_RAMBOOT |
| 49249e13 PA |
404 | #else |
| 405 | #undef CONFIG_SYS_RAMBOOT | |
| 406 | #endif | |
| 407 | ||
| 49249e13 PA |
408 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 409 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| b39d1213 | 410 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ |
| 49249e13 | 411 | |
| b39d1213 | 412 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
| 49249e13 PA |
413 | - GENERATED_GBL_DATA_SIZE) |
| 414 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 415 | ||
| 9307cbab | 416 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 49249e13 | 417 | |
| c9e1f588 YZ |
418 | /* |
| 419 | * Config the L2 Cache as L2 SRAM | |
| 420 | */ | |
| 421 | #if defined(CONFIG_SPL_BUILD) | |
| 422 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
| 423 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 424 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 425 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 426 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 427 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
| 428 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) | |
| c9e1f588 YZ |
429 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) |
| 430 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) | |
| 431 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) | |
| 88718be3 | 432 | #elif defined(CONFIG_MTD_RAW_NAND) |
| c9e1f588 YZ |
433 | #ifdef CONFIG_TPL_BUILD |
| 434 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 435 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 436 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 437 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 438 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
| 439 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
| 440 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
| 441 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
| 442 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
| 443 | #else | |
| 444 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 445 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 446 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 447 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 448 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) | |
| 449 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 450 | #endif | |
| 451 | #endif | |
| 452 | #endif | |
| 453 | ||
| 49249e13 | 454 | /* Serial Port */ |
| 49249e13 | 455 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 49249e13 PA |
456 | #define CONFIG_SYS_NS16550_SERIAL |
| 457 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 458 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| c9e1f588 | 459 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| d793e5a8 DD |
460 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 461 | #endif | |
| 49249e13 | 462 | |
| 49249e13 PA |
463 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 464 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 465 | ||
| 466 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 467 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 468 | ||
| 00f792e0 | 469 | /* I2C */ |
| ad89da0c | 470 | #define I2C_PCA9557_ADDR1 0x18 |
| e512c50b | 471 | #define I2C_PCA9557_ADDR2 0x19 |
| ad89da0c | 472 | #define I2C_PCA9557_BUS_NUM 0 |
| 49249e13 PA |
473 | |
| 474 | /* I2C EEPROM */ | |
| 7601686c | 475 | #if defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
476 | #ifdef CONFIG_ID_EEPROM |
| 477 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 478 | #endif | |
| e512c50b SL |
479 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 480 | #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ | |
| 481 | #endif | |
| 49249e13 | 482 | /* enable read and write access to EEPROM */ |
| 49249e13 PA |
483 | |
| 484 | /* RTC */ | |
| 485 | #define CONFIG_RTC_PT7C4338 | |
| 486 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 487 | ||
| 49249e13 PA |
488 | /* |
| 489 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
| 490 | * used for SLIC | |
| 491 | */ | |
| 88718be3 | 492 | #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) |
| 49249e13 | 493 | /* eSPI - Enhanced SPI */ |
| d793e5a8 | 494 | #endif |
| 49249e13 PA |
495 | |
| 496 | #if defined(CONFIG_TSEC_ENET) | |
| 49249e13 PA |
497 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 498 | #define CONFIG_TSEC1 1 | |
| 499 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 500 | #define CONFIG_TSEC2 1 | |
| 501 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 502 | #define CONFIG_TSEC3 1 | |
| 503 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 504 | ||
| 505 | #define TSEC1_PHY_ADDR 1 | |
| 506 | #define TSEC2_PHY_ADDR 0 | |
| 507 | #define TSEC3_PHY_ADDR 2 | |
| 508 | ||
| 509 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 510 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 511 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 512 | ||
| 513 | #define TSEC1_PHYIDX 0 | |
| 514 | #define TSEC2_PHYIDX 0 | |
| 515 | #define TSEC3_PHYIDX 0 | |
| 516 | ||
| 49249e13 PA |
517 | /* TBI PHY configuration for SGMII mode */ |
| 518 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
| 519 | TBICR_PHY_RESET \ | |
| 520 | | TBICR_ANEG_ENABLE \ | |
| 521 | | TBICR_FULL_DUPLEX \ | |
| 522 | | TBICR_SPEED1_SET \ | |
| 523 | ) | |
| 524 | ||
| 525 | #endif /* CONFIG_TSEC_ENET */ | |
| 526 | ||
| 49249e13 | 527 | /* SATA */ |
| 9760b274 | 528 | #define CONFIG_FSL_SATA_V2 |
| 49249e13 PA |
529 | |
| 530 | #ifdef CONFIG_FSL_SATA | |
| 49249e13 PA |
531 | #define CONFIG_SATA1 |
| 532 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 533 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 534 | #define CONFIG_SATA2 | |
| 535 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 536 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 537 | ||
| 49249e13 PA |
538 | #define CONFIG_LBA48 |
| 539 | #endif /* #ifdef CONFIG_FSL_SATA */ | |
| 540 | ||
| 49249e13 | 541 | #ifdef CONFIG_MMC |
| 49249e13 PA |
542 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 543 | #endif | |
| 544 | ||
| 545 | #define CONFIG_HAS_FSL_DR_USB | |
| 546 | ||
| 547 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
| 8850c5d5 | 548 | #ifdef CONFIG_USB_EHCI_HCD |
| 49249e13 | 549 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 49249e13 PA |
550 | #endif |
| 551 | #endif | |
| 552 | ||
| 553 | /* | |
| 554 | * Environment | |
| 555 | */ | |
| c9e1f588 | 556 | #if defined(CONFIG_SDCARD) |
| 4394d0c2 | 557 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| 88718be3 | 558 | #elif defined(CONFIG_MTD_RAW_NAND) |
| c9e1f588 | 559 | #ifdef CONFIG_TPL_BUILD |
| a09fea1d | 560 | #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
| c9e1f588 | 561 | #else |
| 7601686c | 562 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| e512c50b | 563 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ |
| 7601686c | 564 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
565 | #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ |
| 566 | #endif | |
| c9e1f588 | 567 | #endif |
| 49249e13 PA |
568 | #endif |
| 569 | ||
| 570 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 571 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 572 | ||
| 8850c5d5 | 573 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ |
| 49249e13 | 574 | || defined(CONFIG_FSL_SATA) |
| 49249e13 PA |
575 | #endif |
| 576 | ||
| 577 | /* | |
| 578 | * Miscellaneous configurable options | |
| 579 | */ | |
| 49249e13 | 580 | |
| 49249e13 PA |
581 | /* |
| 582 | * For booting Linux, the board info and command line data | |
| 583 | * have to be in the first 64 MB of memory, since this is | |
| 584 | * the maximum mapped by the Linux kernel during initialization. | |
| 585 | */ | |
| 586 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
| 587 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 588 | ||
| 49249e13 PA |
589 | /* |
| 590 | * Environment Configuration | |
| 591 | */ | |
| 592 | ||
| 8b3637c6 | 593 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| 49249e13 PA |
594 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
| 595 | ||
| 49249e13 | 596 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 5368c55d | 597 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ |
| 49249e13 | 598 | "netdev=eth0\0" \ |
| 5368c55d | 599 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 49249e13 PA |
600 | "loadaddr=1000000\0" \ |
| 601 | "consoledev=ttyS0\0" \ | |
| 602 | "ramdiskaddr=2000000\0" \ | |
| 603 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| b24a4f62 | 604 | "fdtaddr=1e00000\0" \ |
| 49249e13 PA |
605 | "fdtfile=p1010rdb.dtb\0" \ |
| 606 | "bdev=sda1\0" \ | |
| 607 | "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ | |
| 608 | "othbootargs=ramdisk_size=600000\0" \ | |
| 609 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
| 610 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 611 | "usb start;" \ | |
| 612 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
| 613 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
| 614 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
| 615 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 616 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 617 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 618 | "usb start;" \ | |
| 619 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 620 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 621 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| e512c50b | 622 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ |
| 028aa094 | 623 | BOOTMODE |
| e512c50b | 624 | |
| 7601686c | 625 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 028aa094 | 626 | #define BOOTMODE \ |
| e512c50b SL |
627 | "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ |
| 628 | "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ | |
| 629 | "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
| 630 | "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ | |
| 631 | "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ | |
| 632 | "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" | |
| 633 | ||
| 7601686c | 634 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| 028aa094 | 635 | #define BOOTMODE \ |
| e512c50b SL |
636 | "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ |
| 637 | "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ | |
| 638 | "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
| 639 | "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ | |
| 640 | "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ | |
| 641 | "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ | |
| 642 | "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ | |
| 643 | "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ | |
| 644 | "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ | |
| 645 | "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" | |
| 646 | #endif | |
| 49249e13 | 647 | |
| 2f439e80 | 648 | #include <asm/fsl_secure_boot.h> |
| 2f439e80 | 649 | |
| 49249e13 | 650 | #endif /* __CONFIG_H */ |