[J-u-boot.git] / include / configs / CANBT.h

/*
 * (C) Copyright 2001
 * Matthias Fuchs, esd gmbh germany, [email protected]
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CANBT		1	/* ...on a CANBT board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; "	\
	"bootm ffe00000 ffe80000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/

#define CONFIG_PHY_ADDR		0	/* PHY address			*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IRQ
#define CONFIG_CMD_EEPROM

#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#define CONFIG_SYS_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* Use FLASH for environment variables */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/

#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address	*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (CAN/USB) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
#define CONFIG_SYS_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (CAN Features) initialization					*/
#define CONFIG_SYS_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
#define CONFIG_SYS_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in RAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#endif	/* __CONFIG_H */
Commit	Line	Data
ab255f26 WD	1	/*
	2	* (C) Copyright 2001
	3	* Matthias Fuchs, esd gmbh germany, [email protected]
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ab255f26 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405CR 1 /* This is a PPC405CR CPU */
c837dcb1 WD	21	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	22	#define CONFIG_CANBT 1 /* ...on a CANBT board */
ab255f26	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	25
c837dcb1	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
ab255f26	27
c837dcb1	28	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
ab255f26 WD	29
	30	#define CONFIG_BAUDRATE 115200
	31	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
	32
	33	#undef CONFIG_BOOTARGS
	34	#define CONFIG_BOOTCOMMAND \
	35	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
	36	"bootm ffe00000 ffe80000"
	37
	38	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	39	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
ab255f26	40
c837dcb1	41	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
ab255f26	42
c837dcb1	43	#define CONFIG_PHY_ADDR 0 /* PHY address */
ab255f26	44
ab255f26	45
11799434 JL	46	/*
	47	* BOOTP options
	48	*/
	49	#define CONFIG_BOOTP_BOOTFILESIZE
	50	#define CONFIG_BOOTP_BOOTPATH
	51	#define CONFIG_BOOTP_GATEWAY
	52	#define CONFIG_BOOTP_HOSTNAME
	53
	54
49cf7e8e JL	55	/*
	56	* Command line configuration.
	57	*/
	58	#include <config_cmd_default.h>
	59
	60	#define CONFIG_CMD_IRQ
5728be38	61	#define CONFIG_CMD_EEPROM
49cf7e8e JL	62
49cf7e8e JL	63	#undef CONFIG_CMD_NET
ee8028b7	64	#undef CONFIG_CMD_NFS
ab255f26 WD	65
	66	#undef CONFIG_WATCHDOG /* watchdog disabled */
	67
c837dcb1	68	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
ab255f26 WD	69
	70	/*
	71	* Miscellaneous configurable options
	72	*/
6d0f6bcf JCPV	73	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	74	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
49cf7e8e	75	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	76	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
ab255f26	77	#else
6d0f6bcf	78	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
ab255f26	79	#endif
6d0f6bcf JCPV	80	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	81	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	82	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
ab255f26	83
6d0f6bcf	84	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
ab255f26	85
6d0f6bcf JCPV	86	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	87	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
ab255f26	88
550650dd SR	89	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	90	#define CONFIG_SYS_NS16550
	91	#define CONFIG_SYS_NS16550_SERIAL
	92	#define CONFIG_SYS_NS16550_REG_SIZE 1
	93	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	94
6d0f6bcf	95	#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
ab255f26 WD	96
ab255f26 WD	97	/* The following table includes the supported baudrates */
6d0f6bcf	98	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	99	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	100	57600, 115200, 230400, 460800, 921600 }
ab255f26	101
6d0f6bcf JCPV	102	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	103	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
ab255f26	104
6d0f6bcf	105	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
ab255f26 WD	106
	107	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	108
	109	/*-----------------------------------------------------------------------
	110	* Start addresses for the final memory configuration
	111	* (Set up by the startup code)
6d0f6bcf	112	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
ab255f26	113	*/
6d0f6bcf	114	#define CONFIG_SYS_SDRAM_BASE 0x00000000
a00c137e	115	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
14d0a02a WD	116	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
14d0a02a WD	117	#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
6d0f6bcf	118	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
ab255f26 WD	119
	120	/*
	121	* For booting Linux, the board info and command line data
	122	* have to be in the first 8 MB of memory, since this is
	123	* the maximum mapped by the Linux kernel during initialization.
	124	*/
6d0f6bcf	125	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ab255f26 WD	126	/*-----------------------------------------------------------------------
	127	* FLASH organization
	128	*/
6d0f6bcf JCPV	129	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	130	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
ab255f26	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	133	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
ab255f26	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	136	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	137	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
ab255f26 WD	138	/*
	139	* The following defines are added for buggy IOP480 byte interface.
	140	* All other boards should use the standard values (CPCI405 etc.)
	141	*/
6d0f6bcf JCPV	142	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	143	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	144	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
ab255f26	145
6d0f6bcf	146	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
ab255f26 WD	147
	148	#if 0 /* Use FLASH for environment variables */
	149
5a1aceb0	150	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	151	#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
0e8d1586 JCPV	152	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
ab255f26	153
0e8d1586	154	#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
ab255f26 WD	155
	156	#else /* Use EEPROM for environment variables */
	157
bb1f8b4f	158	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	159	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	160	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
8bde7f77	161	/* total size of a CAT24WC08 is 1024 bytes */
ab255f26 WD	162	#endif
	163
	164	/*-----------------------------------------------------------------------
	165	* I2C EEPROM (CAT24WC08) for environment
	166	*/
880540de DE	167	#define CONFIG_SYS_I2C
	168	#define CONFIG_SYS_I2C_PPC4XX
	169	#define CONFIG_SYS_I2C_PPC4XX_CH0
	170	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	171	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
	172
	173	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
	174	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
ab255f26	175	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf	176	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
ab255f26	177
ab255f26 WD	178	/*
	179	* Init Memory Controller:
	180	*
	181	* BR0/1 and OR0/1 (FLASH)
	182	*/
	183
	184	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	185	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	186
	187	/*-----------------------------------------------------------------------
	188	* External Bus Controller (EBC) Setup
	189	*/
	190
c837dcb1	191	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	192	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	193	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
ab255f26	194
c837dcb1	195	/* Memory Bank 1 (CAN/USB) initialization */
6d0f6bcf JCPV	196	#define CONFIG_SYS_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
6d0f6bcf JCPV	197	#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
ab255f26	198
c837dcb1	199	/* Memory Bank 2 (Misc-IO/LEDs) initialization */
6d0f6bcf JCPV	200	#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
6d0f6bcf JCPV	201	#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
ab255f26	202
c837dcb1	203	/* Memory Bank 3 (CAN Features) initialization */
6d0f6bcf JCPV	204	#define CONFIG_SYS_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
6d0f6bcf JCPV	205	#define CONFIG_SYS_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
ab255f26 WD	206
	207	/*-----------------------------------------------------------------------
	208	* Definitions for initial stack pointer and data area (in RAM)
	209	*/
6d0f6bcf	210	#define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
553f0982	211	#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
25ddd1fb	212	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	213	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
ab255f26	214
ab255f26	215	#endif /* __CONFIG_H */