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Commit | Line | Data |
---|---|---|
13ea307f CG |
1 | CONFIG_PPC=y |
2 | CONFIG_SYS_TEXT_BASE=0xEFF40000 | |
3 | CONFIG_SYS_MEMTEST_START=0x00200000 | |
4 | CONFIG_SYS_MEMTEST_END=0x00400000 | |
5 | CONFIG_ENV_SIZE=0x2000 | |
6 | CONFIG_ENV_SECT_SIZE=0x20000 | |
7 | CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" | |
8 | CONFIG_MPC85xx=y | |
9 | CONFIG_TARGET_T2080RDB=y | |
10 | CONFIG_MPC85XX_HAVE_RESET_VECTOR=y | |
11 | CONFIG_T2080RDB_REV_D=y | |
12 | CONFIG_FIT=y | |
13 | CONFIG_FIT_VERBOSE=y | |
14 | CONFIG_OF_BOARD_SETUP=y | |
15 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
16 | CONFIG_BOOTDELAY=10 | |
17 | CONFIG_BOARD_EARLY_INIT_R=y | |
18 | CONFIG_HUSH_PARSER=y | |
19 | CONFIG_CMD_IMLS=y | |
88cd7d0e | 20 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 |
13ea307f CG |
21 | CONFIG_CMD_MEMTEST=y |
22 | CONFIG_SYS_ALT_MEMTEST=y | |
23 | CONFIG_CMD_DM=y | |
24 | CONFIG_CMD_I2C=y | |
25 | CONFIG_CMD_MMC=y | |
26 | CONFIG_CMD_USB=y | |
27 | CONFIG_CMD_DHCP=y | |
28 | CONFIG_CMD_MII=y | |
29 | CONFIG_CMD_PING=y | |
30 | CONFIG_MP=y | |
31 | CONFIG_CMD_EXT2=y | |
32 | CONFIG_CMD_FAT=y | |
33 | CONFIG_CMD_MTDPARTS=y | |
34 | CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" | |
35 | CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" | |
36 | # CONFIG_CMD_IRQ is not set | |
37 | CONFIG_OF_CONTROL=y | |
38 | CONFIG_ENV_OVERWRITE=y | |
39 | CONFIG_ENV_IS_IN_FLASH=y | |
40 | CONFIG_ENV_ADDR=0xEFF20000 | |
41 | CONFIG_DM=y | |
42 | CONFIG_FSL_CAAM=y | |
efb5dab7 | 43 | CONFIG_DDR_CLK_FREQ=133330000 |
95372165 TR |
44 | CONFIG_DDR_ECC=y |
45 | CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y | |
13ea307f | 46 | CONFIG_DM_I2C=y |
55dabcc8 | 47 | CONFIG_SPL_SYS_I2C_LEGACY=y |
fc8d3b9a | 48 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
6d5d0c95 TR |
49 | CONFIG_SYS_I2C_FSL=y |
50 | CONFIG_SYS_FSL_I2C_OFFSET=0x118000 | |
51 | CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y | |
52 | CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 | |
53 | CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y | |
54 | CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 | |
55 | CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y | |
56 | CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 | |
88cd7d0e | 57 | CONFIG_SYS_I2C_EEPROM_ADDR=0x50 |
13ea307f CG |
58 | CONFIG_FSL_ESDHC=y |
59 | CONFIG_MTD=y | |
60 | CONFIG_MTD_NOR_FLASH=y | |
61 | CONFIG_FLASH_CFI_DRIVER=y | |
62 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
63 | CONFIG_FLASH_CFI_MTD=y | |
64 | CONFIG_SYS_FLASH_CFI=y | |
65 | CONFIG_DM_SPI_FLASH=y | |
13ea307f CG |
66 | CONFIG_SF_DEFAULT_SPEED=10000000 |
67 | CONFIG_SPI_FLASH_STMICRO=y | |
68 | CONFIG_PHYLIB=y | |
69 | CONFIG_PHY_AQUANTIA=y | |
70 | CONFIG_PHY_CORTINA=y | |
e99b1dfc | 71 | CONFIG_CORTINA_FW_ADDR=0xEFE00000 |
13ea307f CG |
72 | CONFIG_PHY_REALTEK=y |
73 | CONFIG_DM_ETH=y | |
74 | CONFIG_DM_MDIO=y | |
75 | CONFIG_E1000=y | |
76 | CONFIG_FMAN_ENET=y | |
a97a071d | 77 | CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 |
13ea307f | 78 | CONFIG_MII=y |
13ea307f CG |
79 | CONFIG_DM_PCI_COMPAT=y |
80 | CONFIG_PCIE_FSL=y | |
81 | CONFIG_SYS_QE_FMAN_FW_IN_NOR=y | |
82 | CONFIG_DM_RTC=y | |
83 | CONFIG_RTC_DS1307=y | |
84 | CONFIG_SYS_NS16550=y | |
85 | CONFIG_SPI=y | |
86 | CONFIG_DM_SPI=y | |
87 | CONFIG_FSL_ESPI=y | |
88 | CONFIG_USB=y | |
13ea307f CG |
89 | CONFIG_USB_STORAGE=y |
90 | CONFIG_ADDR_MAP=y | |
91 | CONFIG_SYS_NUM_ADDR_MAP=64 |