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4e675ff2 TW |
1 | /* |
2 | * NVIDIA Tegra210 QSPI controller driver | |
3 | * | |
4 | * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <dm.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/arch/clock.h> | |
13 | #include <asm/arch-tegra/clk_rst.h> | |
14 | #include <spi.h> | |
15 | #include <fdtdec.h> | |
16 | #include "tegra_spi.h" | |
17 | ||
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
20 | /* COMMAND1 */ | |
21 | #define QSPI_CMD1_GO BIT(31) | |
22 | #define QSPI_CMD1_M_S BIT(30) | |
23 | #define QSPI_CMD1_MODE_MASK GENMASK(1,0) | |
24 | #define QSPI_CMD1_MODE_SHIFT 28 | |
25 | #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0) | |
26 | #define QSPI_CMD1_CS_SEL_SHIFT 26 | |
27 | #define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22) | |
28 | #define QSPI_CMD1_CS_SW_HW BIT(21) | |
29 | #define QSPI_CMD1_CS_SW_VAL BIT(20) | |
30 | #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0) | |
31 | #define QSPI_CMD1_IDLE_SDA_SHIFT 18 | |
32 | #define QSPI_CMD1_BIDIR BIT(17) | |
33 | #define QSPI_CMD1_LSBI_FE BIT(16) | |
34 | #define QSPI_CMD1_LSBY_FE BIT(15) | |
35 | #define QSPI_CMD1_BOTH_EN_BIT BIT(14) | |
36 | #define QSPI_CMD1_BOTH_EN_BYTE BIT(13) | |
37 | #define QSPI_CMD1_RX_EN BIT(12) | |
38 | #define QSPI_CMD1_TX_EN BIT(11) | |
39 | #define QSPI_CMD1_PACKED BIT(5) | |
40 | #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0) | |
41 | #define QSPI_CMD1_BITLEN_SHIFT 0 | |
42 | ||
43 | /* COMMAND2 */ | |
44 | #define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) | |
45 | #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) | |
46 | #define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) | |
47 | #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) | |
48 | ||
49 | /* TRANSFER STATUS */ | |
50 | #define QSPI_XFER_STS_RDY BIT(30) | |
51 | ||
52 | /* FIFO STATUS */ | |
53 | #define QSPI_FIFO_STS_CS_INACTIVE BIT(31) | |
54 | #define QSPI_FIFO_STS_FRAME_END BIT(30) | |
55 | #define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) | |
56 | #define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) | |
57 | #define QSPI_FIFO_STS_ERR BIT(8) | |
58 | #define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7) | |
59 | #define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6) | |
60 | #define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5) | |
61 | #define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4) | |
62 | #define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3) | |
63 | #define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) | |
64 | #define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1) | |
65 | #define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) | |
66 | ||
67 | #define QSPI_TIMEOUT 1000 | |
68 | ||
69 | struct qspi_regs { | |
70 | u32 command1; /* 000:QSPI_COMMAND1 register */ | |
71 | u32 command2; /* 004:QSPI_COMMAND2 register */ | |
72 | u32 timing1; /* 008:QSPI_CS_TIM1 register */ | |
73 | u32 timing2; /* 00c:QSPI_CS_TIM2 register */ | |
74 | u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */ | |
75 | u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */ | |
76 | u32 tx_data; /* 018:QSPI_TX_DATA register */ | |
77 | u32 rx_data; /* 01c:QSPI_RX_DATA register */ | |
78 | u32 dma_ctl; /* 020:QSPI_DMA_CTL register */ | |
79 | u32 dma_blk; /* 024:QSPI_DMA_BLK register */ | |
80 | u32 rsvd[56]; /* 028-107 reserved */ | |
81 | u32 tx_fifo; /* 108:QSPI_FIFO1 register */ | |
82 | u32 rsvd2[31]; /* 10c-187 reserved */ | |
83 | u32 rx_fifo; /* 188:QSPI_FIFO2 register */ | |
84 | u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */ | |
85 | }; | |
86 | ||
87 | struct tegra210_qspi_priv { | |
88 | struct qspi_regs *regs; | |
89 | unsigned int freq; | |
90 | unsigned int mode; | |
91 | int periph_id; | |
92 | int valid; | |
93 | int last_transaction_us; | |
94 | }; | |
95 | ||
96 | static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) | |
97 | { | |
98 | struct tegra_spi_platdata *plat = bus->platdata; | |
99 | const void *blob = gd->fdt_blob; | |
e160f7d4 | 100 | int node = dev_of_offset(bus); |
4e675ff2 | 101 | |
a821c4af | 102 | plat->base = devfdt_get_addr(bus); |
4e675ff2 TW |
103 | plat->periph_id = clock_decode_periph_id(blob, node); |
104 | ||
105 | if (plat->periph_id == PERIPH_ID_NONE) { | |
106 | debug("%s: could not decode periph id %d\n", __func__, | |
107 | plat->periph_id); | |
108 | return -FDT_ERR_NOTFOUND; | |
109 | } | |
110 | ||
111 | /* Use 500KHz as a suitable default */ | |
112 | plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", | |
113 | 500000); | |
114 | plat->deactivate_delay_us = fdtdec_get_int(blob, node, | |
115 | "spi-deactivate-delay", 0); | |
116 | debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", | |
117 | __func__, plat->base, plat->periph_id, plat->frequency, | |
118 | plat->deactivate_delay_us); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | static int tegra210_qspi_probe(struct udevice *bus) | |
124 | { | |
125 | struct tegra_spi_platdata *plat = dev_get_platdata(bus); | |
126 | struct tegra210_qspi_priv *priv = dev_get_priv(bus); | |
127 | ||
128 | priv->regs = (struct qspi_regs *)plat->base; | |
129 | ||
130 | priv->last_transaction_us = timer_get_us(); | |
131 | priv->freq = plat->frequency; | |
132 | priv->periph_id = plat->periph_id; | |
133 | ||
4832c7f5 SW |
134 | /* Change SPI clock to correct frequency, PLLP_OUT0 source */ |
135 | clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); | |
136 | ||
4e675ff2 TW |
137 | return 0; |
138 | } | |
139 | ||
140 | static int tegra210_qspi_claim_bus(struct udevice *bus) | |
141 | { | |
142 | struct tegra210_qspi_priv *priv = dev_get_priv(bus); | |
143 | struct qspi_regs *regs = priv->regs; | |
144 | ||
145 | /* Change SPI clock to correct frequency, PLLP_OUT0 source */ | |
146 | clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); | |
147 | ||
148 | debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); | |
149 | ||
150 | /* Set master mode and sw controlled CS */ | |
151 | setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | | |
152 | (priv->mode << QSPI_CMD1_MODE_SHIFT)); | |
153 | debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | /** | |
159 | * Activate the CS by driving it LOW | |
160 | * | |
161 | * @param slave Pointer to spi_slave to which controller has to | |
162 | * communicate with | |
163 | */ | |
164 | static void spi_cs_activate(struct udevice *dev) | |
165 | { | |
166 | struct udevice *bus = dev->parent; | |
167 | struct tegra_spi_platdata *pdata = dev_get_platdata(bus); | |
168 | struct tegra210_qspi_priv *priv = dev_get_priv(bus); | |
169 | ||
170 | /* If it's too soon to do another transaction, wait */ | |
171 | if (pdata->deactivate_delay_us && | |
172 | priv->last_transaction_us) { | |
173 | ulong delay_us; /* The delay completed so far */ | |
174 | delay_us = timer_get_us() - priv->last_transaction_us; | |
175 | if (delay_us < pdata->deactivate_delay_us) | |
176 | udelay(pdata->deactivate_delay_us - delay_us); | |
177 | } | |
178 | ||
179 | clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); | |
180 | } | |
181 | ||
182 | /** | |
183 | * Deactivate the CS by driving it HIGH | |
184 | * | |
185 | * @param slave Pointer to spi_slave to which controller has to | |
186 | * communicate with | |
187 | */ | |
188 | static void spi_cs_deactivate(struct udevice *dev) | |
189 | { | |
190 | struct udevice *bus = dev->parent; | |
191 | struct tegra_spi_platdata *pdata = dev_get_platdata(bus); | |
192 | struct tegra210_qspi_priv *priv = dev_get_priv(bus); | |
193 | ||
194 | setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); | |
195 | ||
196 | /* Remember time of this transaction so we can honour the bus delay */ | |
197 | if (pdata->deactivate_delay_us) | |
198 | priv->last_transaction_us = timer_get_us(); | |
199 | ||
200 | debug("Deactivate CS, bus '%s'\n", bus->name); | |
201 | } | |
202 | ||
203 | static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, | |
204 | const void *data_out, void *data_in, | |
205 | unsigned long flags) | |
206 | { | |
207 | struct udevice *bus = dev->parent; | |
208 | struct tegra210_qspi_priv *priv = dev_get_priv(bus); | |
209 | struct qspi_regs *regs = priv->regs; | |
210 | u32 reg, tmpdout, tmpdin = 0; | |
211 | const u8 *dout = data_out; | |
212 | u8 *din = data_in; | |
213 | int num_bytes, tm, ret; | |
214 | ||
215 | debug("%s: slave %u:%u dout %p din %p bitlen %u\n", | |
216 | __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); | |
217 | if (bitlen % 8) | |
218 | return -1; | |
219 | num_bytes = bitlen / 8; | |
220 | ||
221 | ret = 0; | |
222 | ||
223 | /* clear all error status bits */ | |
224 | reg = readl(®s->fifo_status); | |
225 | writel(reg, ®s->fifo_status); | |
226 | ||
227 | /* flush RX/TX FIFOs */ | |
228 | setbits_le32(®s->fifo_status, | |
229 | (QSPI_FIFO_STS_RX_FIFO_FLUSH | | |
230 | QSPI_FIFO_STS_TX_FIFO_FLUSH)); | |
231 | ||
232 | tm = QSPI_TIMEOUT; | |
233 | while ((tm && readl(®s->fifo_status) & | |
234 | (QSPI_FIFO_STS_RX_FIFO_FLUSH | | |
235 | QSPI_FIFO_STS_TX_FIFO_FLUSH))) { | |
236 | tm--; | |
237 | udelay(1); | |
238 | } | |
239 | ||
240 | if (!tm) { | |
241 | printf("%s: timeout during QSPI FIFO flush!\n", | |
242 | __func__); | |
243 | return -1; | |
244 | } | |
245 | ||
246 | /* | |
247 | * Notes: | |
248 | * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; | |
249 | * 2. don't set RX_EN and TX_EN yet. | |
250 | * (SW needs to make sure that while programming the blk_size, | |
251 | * tx_en and rx_en bits must be zero) | |
252 | * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set | |
253 | * i.e., both dout and din are not NULL. | |
254 | */ | |
255 | clrsetbits_le32(®s->command1, | |
256 | (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE | | |
257 | QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN), | |
258 | (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT)); | |
259 | ||
260 | /* set xfer size to 1 block (32 bits) */ | |
261 | writel(0, ®s->dma_blk); | |
262 | ||
263 | if (flags & SPI_XFER_BEGIN) | |
264 | spi_cs_activate(dev); | |
265 | ||
266 | /* handle data in 32-bit chunks */ | |
267 | while (num_bytes > 0) { | |
268 | int bytes; | |
269 | ||
270 | tmpdout = 0; | |
271 | bytes = (num_bytes > 4) ? 4 : num_bytes; | |
272 | ||
273 | if (dout != NULL) { | |
274 | memcpy((void *)&tmpdout, (void *)dout, bytes); | |
275 | dout += bytes; | |
276 | num_bytes -= bytes; | |
277 | writel(tmpdout, ®s->tx_fifo); | |
278 | setbits_le32(®s->command1, QSPI_CMD1_TX_EN); | |
279 | } | |
280 | ||
281 | if (din != NULL) | |
282 | setbits_le32(®s->command1, QSPI_CMD1_RX_EN); | |
283 | ||
284 | /* clear ready bit */ | |
285 | setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY); | |
286 | ||
287 | clrsetbits_le32(®s->command1, | |
288 | QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT, | |
289 | (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); | |
290 | ||
291 | /* Need to stabilize other reg bits before GO bit set. | |
292 | * As per the TRM: | |
293 | * "For successful operation at various freq combinations, | |
294 | * a minimum of 4-5 spi_clk cycle delay might be required | |
295 | * before enabling the PIO or DMA bits. The worst case delay | |
296 | * calculation can be done considering slowest qspi_clk as | |
297 | * 1MHz. Based on that 1us delay should be enough before | |
298 | * enabling PIO or DMA." Padded another 1us for safety. | |
299 | */ | |
300 | udelay(2); | |
301 | setbits_le32(®s->command1, QSPI_CMD1_GO); | |
302 | udelay(1); | |
303 | ||
304 | /* | |
305 | * Wait for SPI transmit FIFO to empty, or to time out. | |
306 | * The RX FIFO status will be read and cleared last | |
307 | */ | |
308 | for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { | |
309 | u32 fifo_status, xfer_status; | |
310 | ||
311 | xfer_status = readl(®s->xfer_status); | |
312 | if (!(xfer_status & QSPI_XFER_STS_RDY)) | |
313 | continue; | |
314 | ||
315 | fifo_status = readl(®s->fifo_status); | |
316 | if (fifo_status & QSPI_FIFO_STS_ERR) { | |
317 | debug("%s: got a fifo error: ", __func__); | |
318 | if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF) | |
319 | debug("tx FIFO overflow "); | |
320 | if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR) | |
321 | debug("tx FIFO underrun "); | |
322 | if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF) | |
323 | debug("rx FIFO overflow "); | |
324 | if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR) | |
325 | debug("rx FIFO underrun "); | |
326 | if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL) | |
327 | debug("tx FIFO full "); | |
328 | if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY) | |
329 | debug("tx FIFO empty "); | |
330 | if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL) | |
331 | debug("rx FIFO full "); | |
332 | if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY) | |
333 | debug("rx FIFO empty "); | |
334 | debug("\n"); | |
335 | break; | |
336 | } | |
337 | ||
338 | if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) { | |
339 | tmpdin = readl(®s->rx_fifo); | |
340 | if (din != NULL) { | |
341 | memcpy(din, &tmpdin, bytes); | |
342 | din += bytes; | |
343 | num_bytes -= bytes; | |
344 | } | |
345 | } | |
346 | break; | |
347 | } | |
348 | ||
349 | if (tm >= QSPI_TIMEOUT) | |
350 | ret = tm; | |
351 | ||
352 | /* clear ACK RDY, etc. bits */ | |
353 | writel(readl(®s->fifo_status), ®s->fifo_status); | |
354 | } | |
355 | ||
356 | if (flags & SPI_XFER_END) | |
357 | spi_cs_deactivate(dev); | |
358 | ||
359 | debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", | |
360 | __func__, tmpdin, readl(®s->fifo_status)); | |
361 | ||
362 | if (ret) { | |
363 | printf("%s: timeout during SPI transfer, tm %d\n", | |
364 | __func__, ret); | |
365 | return -1; | |
366 | } | |
367 | ||
368 | return ret; | |
369 | } | |
370 | ||
371 | static int tegra210_qspi_set_speed(struct udevice *bus, uint speed) | |
372 | { | |
373 | struct tegra_spi_platdata *plat = bus->platdata; | |
374 | struct tegra210_qspi_priv *priv = dev_get_priv(bus); | |
375 | ||
376 | if (speed > plat->frequency) | |
377 | speed = plat->frequency; | |
378 | priv->freq = speed; | |
379 | debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | static int tegra210_qspi_set_mode(struct udevice *bus, uint mode) | |
385 | { | |
386 | struct tegra210_qspi_priv *priv = dev_get_priv(bus); | |
387 | ||
388 | priv->mode = mode; | |
389 | debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | static const struct dm_spi_ops tegra210_qspi_ops = { | |
395 | .claim_bus = tegra210_qspi_claim_bus, | |
396 | .xfer = tegra210_qspi_xfer, | |
397 | .set_speed = tegra210_qspi_set_speed, | |
398 | .set_mode = tegra210_qspi_set_mode, | |
399 | /* | |
400 | * cs_info is not needed, since we require all chip selects to be | |
401 | * in the device tree explicitly | |
402 | */ | |
403 | }; | |
404 | ||
405 | static const struct udevice_id tegra210_qspi_ids[] = { | |
406 | { .compatible = "nvidia,tegra210-qspi" }, | |
407 | { } | |
408 | }; | |
409 | ||
410 | U_BOOT_DRIVER(tegra210_qspi) = { | |
411 | .name = "tegra210-qspi", | |
412 | .id = UCLASS_SPI, | |
413 | .of_match = tegra210_qspi_ids, | |
414 | .ops = &tegra210_qspi_ops, | |
415 | .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata, | |
416 | .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), | |
417 | .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv), | |
418 | .per_child_auto_alloc_size = sizeof(struct spi_slave), | |
419 | .probe = tegra210_qspi_probe, | |
420 | }; |