[J-u-boot.git] / drivers / serial / serial_mpc8xx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 */

#include <command.h>
#include <dm.h>
#include <serial.h>
#include <watchdog.h>
#include <asm/cpm_8xx.h>
#include <asm/global_data.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_8xx_CONS_SMC1)	/* Console on SMC1 */
#define	SMC_INDEX	0
#define PROFF_SMC	PROFF_SMC1
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
#define IOPINS		0xc0

#elif defined(CONFIG_8xx_CONS_SMC2)	/* Console on SMC2 */
#define SMC_INDEX	1
#define PROFF_SMC	PROFF_SMC2
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC2
#define IOPINS		0xc00

#endif /* CONFIG_8xx_CONS_SMCx */

struct serialbuffer {
	cbd_t	rxbd;		/* Rx BD */
	cbd_t	txbd;		/* Tx BD */
	uint	rxindex;	/* index for next character to read */
	uchar	rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	uchar	txbuf;	/* tx buffers */
};

static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
{
	int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;

	if (divisor / 16 > 0x1000) {
		/* bad divisor, assume 50MHz clock and 9600 baud */
		divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
	}

	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;

	if (divisor <= 0x1000)
		out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
	else
		out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
			 CPM_BRG_DIV16);
}

/*
 * Minimal serial functions needed to use one of the SMC ports
 * as serial console interface.
 */

static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
{
	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t __iomem *cp = &(im->im_cpm);

	/* Set up the baud rate generator.
	 * See 8xx_io/commproc.c for details.
	 *
	 * Wire BRG1 to SMCx
	 */

	out_be32(&cp->cp_simode, 0);

	serial_setdivisor(cp, baudrate);

	return 0;
}

static int serial_mpc8xx_probe(struct udevice *dev)
{
	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	smc_t __iomem *sp;
	smc_uart_t __iomem *up;
	u16 smc_rpbase;
	cpm8xx_t __iomem *cp = &(im->im_cpm);
	struct serialbuffer __iomem *rtx;

	/* initialize pointers to SMC */

	sp = cp->cp_smc + SMC_INDEX;
	up = (smc_uart_t __iomem *)&cp->cp_dpmem[PROFF_SMC];

	smc_rpbase = in_be16(&up->smc_rpbase);
	if (smc_rpbase)
		up = (smc_uart_t __iomem *)&cp->cp_dpmem[smc_rpbase];

	/* Disable transmitter/receiver. */
	clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	/* Enable SDMA. */
	out_be32(&im->im_siu_conf.sc_sdcr, 1);

	/* clear error conditions */
	out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);

	/* clear SDMA interrupt mask */
	out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);

	/* Use Port B for SMCx instead of other functions. */
	setbits_be32(&cp->cp_pbpar, IOPINS);
	clrbits_be32(&cp->cp_pbdir, IOPINS);
	clrbits_be16(&cp->cp_pbodr, IOPINS);

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
	/* Allocate space for two buffer descriptors in the DP ram.
	 * For now, this address seems OK, but it may have to
	 * change with newer versions of the firmware.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
	out_be16(&rtx->rxbd.cbd_sc, 0);

	out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
	out_be16(&rtx->txbd.cbd_sc, 0);

	/* Set up the uart parameters in the parameter ram. */
	out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
	out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
	out_8(&up->smc_rfcr, SMC_EB);
	out_8(&up->smc_tfcr, SMC_EB);

	/* Set UART mode, 8 bit, no parity, one stop.
	 * Enable receive and transmit.
	 */
	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);

	/* Mask all interrupts and remove anything pending.
	*/
	out_8(&sp->smc_smcm, 0);
	out_8(&sp->smc_smce, 0xff);

	/* Set up the baud rate generator */
	serial_mpc8xx_setbrg(dev, gd->baudrate);

	/* Make the first buffer the only buffer. */
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);

	/* single/multi character receive. */
	out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
	out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
	out_be32(&rtx->rxindex, 0);

	out_be32(&up->smc_rstate, 0);
	out_be32(&up->smc_tstate, 0);
	out_be16(&up->smc_rbptr, CPM_SERIAL_BASE);
	out_be16(&up->smc_tbptr, CPM_SERIAL_BASE + sizeof(cbd_t));
	out_be16(&up->smc_brkcr, 1);
	out_be16(&up->smc_brkec, 0);

	/* Enable transmitter/receiver.	*/
	setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	return 0;
}

static int serial_mpc8xx_putc(struct udevice *dev, const char c)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
		return -EAGAIN;

	out_8(&rtx->txbuf, c);
	out_be16(&rtx->txbd.cbd_datlen, 1);
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);

	return 0;
}

static int serial_mpc8xx_getc(struct udevice *dev)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;
	unsigned char  c;
	uint rxindex;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
		return -EAGAIN;

	/* the characters are read one by one,
	 * use the rxindex to know the next char to deliver
	 */
	rxindex = in_be32(&rtx->rxindex);
	c = in_8(rtx->rxbuf + rxindex);
	rxindex++;

	/* check if all char are readout, then make prepare for next receive */
	if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
		rxindex = 0;
		setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
	}
	out_be32(&rtx->rxindex, rxindex);
	return c;
}

static int serial_mpc8xx_pending(struct udevice *dev, bool input)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;

	if (!input)
		return 0;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}

static const struct dm_serial_ops serial_mpc8xx_ops = {
	.putc = serial_mpc8xx_putc,
	.pending = serial_mpc8xx_pending,
	.getc = serial_mpc8xx_getc,
	.setbrg = serial_mpc8xx_setbrg,
};

static const struct udevice_id serial_mpc8xx_ids[] = {
	{ .compatible = "fsl,pq1-smc" },
	{ }
};

U_BOOT_DRIVER(serial_mpc8xx) = {
	.name	= "serial_mpc8xx",
	.id	= UCLASS_SERIAL,
	.of_match = serial_mpc8xx_ids,
	.probe = serial_mpc8xx_probe,
	.ops	= &serial_mpc8xx_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
907208c4 CL	2	/*
	3	* (C) Copyright 2000
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
907208c4 CL	5	*/
907208c4 CL	6
907208c4	7	#include <command.h>
bdfa11eb	8	#include <dm.h>
907208c4 CL	9	#include <serial.h>
907208c4 CL	10	#include <watchdog.h>
18f8d4c6	11	#include <asm/cpm_8xx.h>
401d1c4f	12	#include <asm/global_data.h>
907208c4 CL	13	#include <linux/compiler.h>
	14
	15	DECLARE_GLOBAL_DATA_PTR;
	16
907208c4 CL	17	#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
	18	#define SMC_INDEX 0
	19	#define PROFF_SMC PROFF_SMC1
	20	#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
ba3da734	21	#define IOPINS 0xc0
907208c4 CL	22
	23	#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
	24	#define SMC_INDEX 1
	25	#define PROFF_SMC PROFF_SMC2
	26	#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
ba3da734	27	#define IOPINS 0xc00
907208c4 CL	28
	29	#endif /* CONFIG_8xx_CONS_SMCx */
	30
ba3da734	31	struct serialbuffer {
907208c4 CL	32	cbd_t rxbd; /* Rx BD */
	33	cbd_t txbd; /* Tx BD */
	34	uint rxindex; /* index for next character to read */
ba3da734 CL	35	uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	36	uchar txbuf; /* tx buffers */
	37	};
907208c4	38
bdfa11eb	39	static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
907208c4	40	{
bdfa11eb	41	int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;
907208c4	42
70fd0710	43	if (divisor / 16 > 0x1000) {
907208c4	44	/* bad divisor, assume 50MHz clock and 9600 baud */
70fd0710	45	divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
907208c4 CL	46	}
907208c4 CL	47
907208c4	48	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
907208c4	49
ba3da734 CL	50	if (divisor <= 0x1000)
	51	out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) \| CPM_BRG_EN);
	52	else
	53	out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) \| CPM_BRG_EN \|
	54	CPM_BRG_DIV16);
907208c4 CL	55	}
	56
	57	/*
	58	* Minimal serial functions needed to use one of the SMC ports
	59	* as serial console interface.
	60	*/
	61
42b54013	62	static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
907208c4	63	{
ba3da734 CL	64	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
ba3da734 CL	65	cpm8xx_t __iomem *cp = &(im->im_cpm);
907208c4 CL	66
	67	/* Set up the baud rate generator.
	68	* See 8xx_io/commproc.c for details.
	69	*
	70	* Wire BRG1 to SMCx
	71	*/
	72
ba3da734	73	out_be32(&cp->cp_simode, 0);
907208c4	74
42b54013 CL	75	serial_setdivisor(cp, baudrate);
	76
	77	return 0;
907208c4 CL	78	}
907208c4 CL	79
42b54013	80	static int serial_mpc8xx_probe(struct udevice *dev)
907208c4	81	{
ba3da734 CL	82	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	83	smc_t __iomem *sp;
	84	smc_uart_t __iomem *up;
388cb1a1	85	u16 smc_rpbase;
ba3da734 CL	86	cpm8xx_t __iomem *cp = &(im->im_cpm);
ba3da734 CL	87	struct serialbuffer __iomem *rtx;
907208c4 CL	88
	89	/* initialize pointers to SMC */
	90
ba3da734	91	sp = cp->cp_smc + SMC_INDEX;
fdd243d8	92	up = (smc_uart_t __iomem *)&cp->cp_dpmem[PROFF_SMC];
388cb1a1 CL	93
	94	smc_rpbase = in_be16(&up->smc_rpbase);
	95	if (smc_rpbase)
	96	up = (smc_uart_t __iomem *)&cp->cp_dpmem[smc_rpbase];
907208c4 CL	97
907208c4 CL	98	/* Disable transmitter/receiver. */
ba3da734	99	clrbits_be16(&sp->smc_smcmr, SMCMR_REN \| SMCMR_TEN);
907208c4 CL	100
907208c4 CL	101	/* Enable SDMA. */
ba3da734	102	out_be32(&im->im_siu_conf.sc_sdcr, 1);
907208c4 CL	103
907208c4 CL	104	/* clear error conditions */
ba3da734	105	out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
907208c4 CL	106
907208c4 CL	107	/* clear SDMA interrupt mask */
ba3da734	108	out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
907208c4	109
ba3da734 CL	110	/* Use Port B for SMCx instead of other functions. */
	111	setbits_be32(&cp->cp_pbpar, IOPINS);
	112	clrbits_be32(&cp->cp_pbdir, IOPINS);
	113	clrbits_be16(&cp->cp_pbodr, IOPINS);
907208c4 CL	114
	115	/* Set the physical address of the host memory buffers in
	116	* the buffer descriptors.
	117	*/
ba3da734	118	rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
907208c4 CL	119	/* Allocate space for two buffer descriptors in the DP ram.
	120	* For now, this address seems OK, but it may have to
	121	* change with newer versions of the firmware.
	122	* damm: allocating space after the two buffers for rx/tx data
	123	*/
	124
ba3da734 CL	125	out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
ba3da734 CL	126	out_be16(&rtx->rxbd.cbd_sc, 0);
907208c4	127
ba3da734 CL	128	out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
ba3da734 CL	129	out_be16(&rtx->txbd.cbd_sc, 0);
907208c4 CL	130
907208c4 CL	131	/* Set up the uart parameters in the parameter ram. */
ba3da734 CL	132	out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
	133	out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
	134	out_8(&up->smc_rfcr, SMC_EB);
	135	out_8(&up->smc_tfcr, SMC_EB);
907208c4 CL	136
	137	/* Set UART mode, 8 bit, no parity, one stop.
	138	* Enable receive and transmit.
	139	*/
ba3da734	140	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) \| SMCMR_SM_UART);
907208c4 CL	141
	142	/* Mask all interrupts and remove anything pending.
	143	*/
ba3da734 CL	144	out_8(&sp->smc_smcm, 0);
ba3da734 CL	145	out_8(&sp->smc_smce, 0xff);
907208c4 CL	146
907208c4 CL	147	/* Set up the baud rate generator */
42b54013	148	serial_mpc8xx_setbrg(dev, gd->baudrate);
907208c4 CL	149
907208c4 CL	150	/* Make the first buffer the only buffer. */
ba3da734 CL	151	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
ba3da734 CL	152	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY \| BD_SC_WRAP);
907208c4 CL	153
907208c4 CL	154	/* single/multi character receive. */
ba3da734 CL	155	out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
	156	out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
	157	out_be32(&rtx->rxindex, 0);
907208c4	158
388cb1a1 CL	159	out_be32(&up->smc_rstate, 0);
	160	out_be32(&up->smc_tstate, 0);
	161	out_be16(&up->smc_rbptr, CPM_SERIAL_BASE);
	162	out_be16(&up->smc_tbptr, CPM_SERIAL_BASE + sizeof(cbd_t));
	163	out_be16(&up->smc_brkcr, 1);
	164	out_be16(&up->smc_brkec, 0);
907208c4 CL	165
907208c4 CL	166	/* Enable transmitter/receiver. */
ba3da734	167	setbits_be16(&sp->smc_smcmr, SMCMR_REN \| SMCMR_TEN);
907208c4	168
70fd0710	169	return 0;
907208c4 CL	170	}
907208c4 CL	171
42b54013	172	static int serial_mpc8xx_putc(struct udevice *dev, const char c)
907208c4	173	{
ba3da734 CL	174	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	175	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	176	struct serialbuffer __iomem *rtx;
907208c4	177
ba3da734	178	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4	179
1138bbe0 T	180	if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
	181	return -EAGAIN;
	182
ba3da734 CL	183	out_8(&rtx->txbuf, c);
	184	out_be16(&rtx->txbd.cbd_datlen, 1);
	185	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
907208c4	186
42b54013	187	return 0;
907208c4 CL	188	}
907208c4 CL	189
42b54013	190	static int serial_mpc8xx_getc(struct udevice *dev)
907208c4	191	{
ba3da734 CL	192	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	193	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	194	struct serialbuffer __iomem *rtx;
907208c4	195	unsigned char c;
ba3da734	196	uint rxindex;
907208c4	197
ba3da734	198	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4	199
1138bbe0 T	200	if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
1138bbe0 T	201	return -EAGAIN;
907208c4 CL	202
	203	/* the characters are read one by one,
	204	* use the rxindex to know the next char to deliver
	205	*/
ba3da734 CL	206	rxindex = in_be32(&rtx->rxindex);
	207	c = in_8(rtx->rxbuf + rxindex);
	208	rxindex++;
907208c4 CL	209
907208c4 CL	210	/* check if all char are readout, then make prepare for next receive */
ba3da734 CL	211	if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
	212	rxindex = 0;
	213	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
907208c4	214	}
ba3da734	215	out_be32(&rtx->rxindex, rxindex);
70fd0710	216	return c;
907208c4 CL	217	}
907208c4 CL	218
42b54013	219	static int serial_mpc8xx_pending(struct udevice *dev, bool input)
907208c4	220	{
ba3da734 CL	221	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	222	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	223	struct serialbuffer __iomem *rtx;
907208c4	224
42b54013 CL	225	if (!input)
	226	return 0;
	227
ba3da734	228	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4	229
ba3da734	230	return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
907208c4 CL	231	}
907208c4 CL	232
bdfa11eb CL	233	static const struct dm_serial_ops serial_mpc8xx_ops = {
	234	.putc = serial_mpc8xx_putc,
	235	.pending = serial_mpc8xx_pending,
	236	.getc = serial_mpc8xx_getc,
	237	.setbrg = serial_mpc8xx_setbrg,
	238	};
	239
	240	static const struct udevice_id serial_mpc8xx_ids[] = {
	241	{ .compatible = "fsl,pq1-smc" },
	242	{ }
	243	};
	244
	245	U_BOOT_DRIVER(serial_mpc8xx) = {
	246	.name = "serial_mpc8xx",
	247	.id = UCLASS_SERIAL,
	248	.of_match = serial_mpc8xx_ids,
	249	.probe = serial_mpc8xx_probe,
	250	.ops = &serial_mpc8xx_ops,
	251	.flags = DM_FLAG_PRE_RELOC,
	252	};